Note: this is a candidate for the stable branches.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
CHIPSET(0x6778, CAICOS_6778, CAICOS)
CHIPSET(0x6779, CAICOS_6779, CAICOS)
CHIPSET(0x677B, CAICOS_677B, CAICOS)
+
+CHIPSET(0x9900, ARUBA_9900, ARUBA)
+CHIPSET(0x9901, ARUBA_9901, ARUBA)
+CHIPSET(0x9903, ARUBA_9903, ARUBA)
+CHIPSET(0x9904, ARUBA_9904, ARUBA)
+CHIPSET(0x990F, ARUBA_990F, ARUBA)
+CHIPSET(0x9990, ARUBA_9990, ARUBA)
+CHIPSET(0x9991, ARUBA_9991, ARUBA)
int r;
/* add blocks */
- if (ctx->family == CHIP_CAYMAN)
+ if (ctx->family >= CHIP_CAYMAN)
r = r600_context_add_block(ctx, cayman_config_reg_list,
Elements(cayman_config_reg_list), PKT3_SET_CONFIG_REG, EVERGREEN_CONFIG_REG_OFFSET);
else
Elements(evergreen_config_reg_list), PKT3_SET_CONFIG_REG, EVERGREEN_CONFIG_REG_OFFSET);
if (r)
goto out_err;
- if (ctx->family == CHIP_CAYMAN)
+ if (ctx->family >= CHIP_CAYMAN)
r = r600_context_add_block(ctx, cayman_context_reg_list,
Elements(cayman_context_reg_list), PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET);
else
CHIP_TURKS,
CHIP_CAICOS,
CHIP_CAYMAN,
+ CHIP_ARUBA,
CHIP_LAST,
};
ctx->family == CHIP_SUMO ||
ctx->family == CHIP_SUMO2 ||
ctx->family == CHIP_CAICOS ||
- ctx->family == CHIP_CAYMAN) {
+ ctx->family == CHIP_CAYMAN ||
+ ctx->family == CHIP_ARUBA) {
/* Some GPUs don't have the vertex cache and must use the texture cache instead. */
ctx->surface_sync_cmd.flush_flags |= S_0085F0_TC_ACTION_ENA(1);
} else {
case CHIP_TURKS: return "AMD TURKS";
case CHIP_CAICOS: return "AMD CAICOS";
case CHIP_CAYMAN: return "AMD CAYMAN";
+ case CHIP_ARUBA: return "AMD ARUBA";
default: return "AMD unknown";
}
}
}
/* setup class */
- if (rscreen->family == CHIP_CAYMAN) {
+ if (rscreen->family >= CHIP_CAYMAN) {
rscreen->chip_class = CAYMAN;
} else if (rscreen->family >= CHIP_CEDAR) {
rscreen->chip_class = EVERGREEN;