r600g: add support for TN (trinity) APUs
authorAlex Deucher <alexander.deucher@amd.com>
Tue, 20 Mar 2012 23:43:59 +0000 (19:43 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Tue, 20 Mar 2012 23:43:59 +0000 (19:43 -0400)
Note: this is a candidate for the stable branches.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
include/pci_ids/r600_pci_ids.h
src/gallium/drivers/r600/evergreen_hw_context.c
src/gallium/drivers/r600/r600.h
src/gallium/drivers/r600/r600_hw_context.c
src/gallium/drivers/r600/r600_pipe.c

index a55d45cf5879a5b56803081b12e238b0e5a62815..360c73d51791d6391877406a08f6e384e0e97da4 100644 (file)
@@ -279,3 +279,11 @@ CHIPSET(0x6772, CAICOS_6772, CAICOS)
 CHIPSET(0x6778, CAICOS_6778, CAICOS)
 CHIPSET(0x6779, CAICOS_6779, CAICOS)
 CHIPSET(0x677B, CAICOS_677B, CAICOS)
+
+CHIPSET(0x9900, ARUBA_9900, ARUBA)
+CHIPSET(0x9901, ARUBA_9901, ARUBA)
+CHIPSET(0x9903, ARUBA_9903, ARUBA)
+CHIPSET(0x9904, ARUBA_9904, ARUBA)
+CHIPSET(0x990F, ARUBA_990F, ARUBA)
+CHIPSET(0x9990, ARUBA_9990, ARUBA)
+CHIPSET(0x9991, ARUBA_9991, ARUBA)
index a05f3f3b1e727952400aa5128b3e606986f56b8f..0d2228d388582923513143b5c2eb494e04b692d0 100644 (file)
@@ -669,7 +669,7 @@ int evergreen_context_init(struct r600_context *ctx)
        int r;
 
        /* add blocks */
-       if (ctx->family == CHIP_CAYMAN)
+       if (ctx->family >= CHIP_CAYMAN)
                r = r600_context_add_block(ctx, cayman_config_reg_list,
                                           Elements(cayman_config_reg_list), PKT3_SET_CONFIG_REG, EVERGREEN_CONFIG_REG_OFFSET);
        else
@@ -677,7 +677,7 @@ int evergreen_context_init(struct r600_context *ctx)
                                           Elements(evergreen_config_reg_list), PKT3_SET_CONFIG_REG, EVERGREEN_CONFIG_REG_OFFSET);
        if (r)
                goto out_err;
-       if (ctx->family == CHIP_CAYMAN)
+       if (ctx->family >= CHIP_CAYMAN)
                r = r600_context_add_block(ctx, cayman_context_reg_list,
                                           Elements(cayman_context_reg_list), PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET);
        else
index e0d81d854de59d376fe0a0d15a281d0d955f9bd9..e77e185dd1c25b0cb93723652eb52e8f8caf89e5 100644 (file)
@@ -61,6 +61,7 @@ enum radeon_family {
        CHIP_TURKS,
        CHIP_CAICOS,
        CHIP_CAYMAN,
+       CHIP_ARUBA,
        CHIP_LAST,
 };
 
index 1e1b78247eaa7848bca32d48da610b92a497f29b..6205a20142ec309711bbb638a34dfbdf894c05ff 100644 (file)
@@ -1173,7 +1173,8 @@ void r600_inval_vertex_cache(struct r600_context *ctx)
            ctx->family == CHIP_SUMO ||
            ctx->family == CHIP_SUMO2 ||
            ctx->family == CHIP_CAICOS ||
-           ctx->family == CHIP_CAYMAN) {
+           ctx->family == CHIP_CAYMAN ||
+           ctx->family == CHIP_ARUBA) {
                /* Some GPUs don't have the vertex cache and must use the texture cache instead. */
                ctx->surface_sync_cmd.flush_flags |= S_0085F0_TC_ACTION_ENA(1);
        } else {
index 113dad6e88eb2bb0c58c9e97d82bf7b9ba4b8ea3..8daa67a9952c4a87fde7f07e06c66d5b500bd139 100644 (file)
@@ -347,6 +347,7 @@ static const char *r600_get_family_name(enum radeon_family family)
        case CHIP_TURKS: return "AMD TURKS";
        case CHIP_CAICOS: return "AMD CAICOS";
        case CHIP_CAYMAN: return "AMD CAYMAN";
+       case CHIP_ARUBA: return "AMD ARUBA";
        default: return "AMD unknown";
        }
 }
@@ -803,7 +804,7 @@ struct pipe_screen *r600_screen_create(struct radeon_winsys *ws)
        }
 
        /* setup class */
-       if (rscreen->family == CHIP_CAYMAN) {
+       if (rscreen->family >= CHIP_CAYMAN) {
                rscreen->chip_class = CAYMAN;
        } else if (rscreen->family >= CHIP_CEDAR) {
                rscreen->chip_class = EVERGREEN;