+2011-01-13 Michael Meissner <meissner@linux.vnet.ibm.com>
+
+ PR target/47251
+ * config/rs6000/rs6000.md (floatunsdidf2): Add check for hardware
+ floating point.
+ (floatunsdidf2_fcfidu): Ditto.
+
2011-01-13 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
* config/s390/s390.c (print_operand_address): Replace 'error' with
[(set (match_operand:DF 0 "gpc_reg_operand" "")
(unsigned_float:DF
(match_operand:DI 1 "gpc_reg_operand" "")))]
- "TARGET_FCFIDU || VECTOR_UNIT_VSX_P (DFmode)"
+ "TARGET_HARD_FLOAT && (TARGET_FCFIDU || VECTOR_UNIT_VSX_P (DFmode))"
"")
(define_insn "*floatunsdidf2_fcfidu"
[(set (match_operand:DF 0 "gpc_reg_operand" "=d")
(unsigned_float:DF (match_operand:DI 1 "gpc_reg_operand" "d")))]
- "TARGET_FCFIDU && !VECTOR_UNIT_VSX_P (DFmode)"
+ "TARGET_HARD_FLOAT && TARGET_FCFIDU && !VECTOR_UNIT_VSX_P (DFmode)"
"fcfidu %0,%1"
[(set_attr "type" "fp")
(set_attr "length" "4")])
[(set (match_operand:DF 0 "gpc_reg_operand" "=d")
(unsigned_float:DF (match_operand:DI 1 "memory_operand" "m")))
(clobber (match_scratch:DI 2 "=d"))]
- "TARGET_FCFIDU || VECTOR_UNIT_VSX_P (DFmode)"
+ "TARGET_HARD_FLOAT && (TARGET_FCFIDU || VECTOR_UNIT_VSX_P (DFmode))"
"#"
"&& reload_completed"
[(set (match_dup 2) (match_dup 1))
+2011-01-13 Michael Meissner <meissner@linux.vnet.ibm.com>
+
+ PR target/47251
+ * gcc.target/powerpc/pr47251.c: New file, test PR 47251 fix.
+
2011-01-13 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
* gcc.dg/guality/pr36728-1.c: Disable arg1/2 checks for s390 and
--- /dev/null
+/* { dg-do compile { target { powerpc*-*-* && ip32 } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O2 -msoft-float -mcpu=power7" } */
+
+/* PR 47151: libgcc fails to build when using --with-cpu=power7 due to a missed
+ TARGET_HARD_FLOAT test. */
+unsigned int
+__fixunssfdi (float a)
+{
+ const float dfa = a;
+ const unsigned int hi = dfa / 0x1p32f;
+ const unsigned int lo = dfa - (float) hi * 0x1p32f;
+ return ((unsigned int) hi << (4 * 8)) | lo;
+}