(no commit message)

diff --git a/3d_gpu/architecture/regfile.mdwn b/3d_gpu/architecture/regfile.mdwn
index 3aa7ba12c91683a2c19bf6c8df608b3788f3f61c..bc63a572896c4b26ddff64a9da45fc135e9580f1 100644 (file)
--- a/3d_gpu/architecture/regfile.mdwn
+++ b/3d_gpu/architecture/regfile.mdwn
@@ -22,7 +22,7 @@ For a GPU, the FP and Integer registers need to be a massive 128 x 64-bit.
 Video walkthrough of regfile relationship to Function Units in core:
 <https://youtu.be/7Th1b-jq40k>
 
-[[!img core_regfiles_fus_pickers.jpg size="500px"]]
+[[!img core_regfiles_fus_pickers.jpg size="700x"]]
 
 # Regfile groups, Port Allocations and bit-widths
 
@@ -103,7 +103,7 @@ Notes:
 
 Click on the image to expand it full-screen:
 
-[[!img regfile_hilo_32_odd_even.png size="500px"]]
+[[!img regfile_hilo_32_odd_even.png size="900x"]]
 
 # Regspecs