build/xilinx: minor cleanup

diff --git a/migen/build/xilinx/ise.py b/migen/build/xilinx/ise.py
index 1989603824ec195aee536f6f06feaec34482e319..65126a108e9f5f85962cb681009f747701e11c37 100644 (file)
--- a/migen/build/xilinx/ise.py
+++ b/migen/build/xilinx/ise.py
@@ -4,7 +4,6 @@ import sys
 
 from migen.fhdl.std import *
 from migen.fhdl.structure import _Fragment
-
 from migen.build.generic_platform import *
 from migen.build import tools
 from migen.build.xilinx import common
@@ -134,7 +133,7 @@ def _default_ise_path():
 
 
 def _default_source():
-    return False if sys.platform == "win32" else True
+    return sys.platform != "win32"
 
 
 class XilinxISEToolchain:

diff --git a/migen/build/xilinx/platform.py b/migen/build/xilinx/platform.py
index c5422282dfd9b26c487f0c411e570b68cf8832a5..d4ca4b18d4f8c8b6866e5dedb4e494d997f7a669 100644 (file)
--- a/migen/build/xilinx/platform.py
+++ b/migen/build/xilinx/platform.py
@@ -17,7 +17,7 @@ class XilinxPlatform(GenericPlatform):
     def get_verilog(self, *args, special_overrides=dict(), **kwargs):
         so = dict(common.xilinx_special_overrides)
         if self.device[:3] == "xc7":
-            so.update(dict(common.xilinx_s7_special_overrides))
+            so.update(common.xilinx_s7_special_overrides)
         so.update(special_overrides)
         return GenericPlatform.get_verilog(self, *args, special_overrides=so, **kwargs)