cpus/isa: add a != operator for pcstate

diff --git a/src/arch/arm/types.hh b/src/arch/arm/types.hh
index 9e7c0ff7f030d641ab74c65cc17976a103668e87..15f9f4d0af3b86f3b225834669028c66549cf2ec 100644 (file)
--- a/src/arch/arm/types.hh
+++ b/src/arch/arm/types.hh
@@ -433,6 +433,12 @@ namespace ArmISA
                 _itstate == opc._itstate && _nextItstate == opc._nextItstate;
         }
 
+        bool
+        operator != (const PCState &opc) const
+        {
+            return !(*this == opc);
+        }
+
         void
         serialize(std::ostream &os)
         {

diff --git a/src/arch/generic/types.hh b/src/arch/generic/types.hh
index 931349ac4b771431d02a3d41c4f214a49c43f100..050fbd56e99546450b0ee98ea83c7fdf665ab186 100644 (file)
--- a/src/arch/generic/types.hh
+++ b/src/arch/generic/types.hh
@@ -98,6 +98,12 @@ class PCStateBase
         return _pc == opc._pc && _npc == opc._npc;
     }
 
+    bool
+    operator != (const PCStateBase &opc) const
+    {
+        return !(*this == opc);
+    }
+
     void
     serialize(std::ostream &os)
     {
@@ -235,6 +241,12 @@ class UPCState : public SimplePCState<MachInst>
                _upc == opc._upc && _nupc == opc._nupc;
     }
 
+    bool
+    operator != (const UPCState<MachInst> &opc) const
+    {
+        return !(*this == opc);
+    }
+
     void
     serialize(std::ostream &os)
     {
@@ -310,6 +322,12 @@ class DelaySlotPCState : public SimplePCState<MachInst>
                _nnpc == opc._nnpc;
     }
 
+    bool
+    operator != (const DelaySlotPCState<MachInst> &opc) const
+    {
+        return !(*this == opc);
+    }
+
     void
     serialize(std::ostream &os)
     {
@@ -401,6 +419,12 @@ class DelaySlotUPCState : public DelaySlotPCState<MachInst>
                _upc == opc._upc && _nupc == opc._nupc;
     }
 
+    bool
+    operator != (const DelaySlotUPCState<MachInst> &opc) const
+    {
+        return !(*this == opc);
+    }
+
     void
     serialize(std::ostream &os)
     {