i965: Set Line Stipple enable bit in 3DSTATE_SF for Haswell.

Apparently this needs to be the same as in 3DSTATE_WM.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>

diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h
index 41534b645f963fcf51ad61c4d98e279fa63fbaf3..a0931121475f1300f3d3f81f96449b9c954e00d0 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -1210,6 +1210,8 @@ enum brw_message_target {
  */
 /* GEN7/DW1: */
 # define GEN7_SF_DEPTH_BUFFER_SURFACE_FORMAT_SHIFT     12
+/* GEN7/DW2: */
+# define HSW_SF_LINE_STIPPLE_ENABLE                    14
 
 #define _3DSTATE_SBE                           0x781F /* GEN7+ */
 /* DW1 */

diff --git a/src/mesa/drivers/dri/i965/gen7_sf_state.c b/src/mesa/drivers/dri/i965/gen7_sf_state.c
index c8f4393a529f57558f167166b072a999a0a9b003..5c51abc5a0e980b5eafecc345564167c7049ee11 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen7_sf_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_sf_state.c
@@ -249,6 +249,9 @@ upload_sf_state(struct brw_context *brw)
       dw2 |= GEN6_SF_LINE_AA_MODE_TRUE;
       dw2 |= GEN6_SF_LINE_END_CAP_WIDTH_1_0;
    }
+   if (ctx->Line.StippleFlag && intel->is_haswell) {
+      dw2 |= HSW_SF_LINE_STIPPLE_ENABLE;
+   }
 
    /* FINISHME: Last Pixel Enable?  Vertex Sub Pixel Precision Select?
     * FINISHME: AA Line Distance Mode?