(no commit message)

diff --git a/openpower/sv/overview.mdwn b/openpower/sv/overview.mdwn
index f7f34be17aa4829f2f19c0d3e564643ffc72334a..62c7a961bd8d2969fd1375b1de5e6418ca62231e 100644 (file)
--- a/openpower/sv/overview.mdwn
+++ b/openpower/sv/overview.mdwn
@@ -305,7 +305,7 @@ structure, where all types uint16_t etc. are in little-endian order:
 
 This means that Vector elements start from locations specified by 64 bit "register" but that from that location onwards the elements *overlap subsequent registers*.
 
-Here is another way to view the same concept:
+Here is another way to view the same concept, bearing in mind that it is assumed a LE memory order:
 
     uint8_t reg_sram[8*128];
     uint8_t *actual_bytes = &reg_sram[RA*8];