/* normal case */
/* gen code for children */
- for (i = 0; i < info->NumParams; i++)
+ for (i = 0; i < info->NumParams; i++) {
emit(emitInfo, n->Children[i]);
+ if (!n->Children[i] || !n->Children[i]->Store) {
+ /* error recovery */
+ return NULL;
+ }
+ }
/* gen this instruction and src registers */
inst = new_instruction(emitInfo, info->InstOpcode);
/* emit code for the expression */
inst = emit(emitInfo, n->Children[0]);
+ if (!n->Children[0]->Store) {
+ /* error recovery */
+ return NULL;
+ }
+
assert(n->Children[0]->Store);
/*assert(n->Children[0]->Store->Size == 1);*/
inst = emit(emitInfo, n->Children[0]); /* the condition */
if (emitInfo->EmitCondCodes) {
- assert(inst);
+ if (!inst) {
+ /* error recovery */
+ return NULL;
+ }
condWritemask = inst->DstReg.WriteMask;
}