r600g: really fix multi target support
authorJerome Glisse <jglisse@redhat.com>
Fri, 6 Aug 2010 21:12:37 +0000 (17:12 -0400)
committerJerome Glisse <jglisse@redhat.com>
Fri, 6 Aug 2010 21:13:28 +0000 (17:13 -0400)
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
src/gallium/drivers/r600/r600_context.c
src/gallium/drivers/r600/r600_shader.c
src/gallium/drivers/r600/r600_shader.h
src/gallium/drivers/r600/r600_state.c

index 29dc93bae6cd501b9bc623308f66ff51f90cc50c..052eb1cd6ddde93fa8c03a8cfd9e1288782f7771 100644 (file)
@@ -55,7 +55,7 @@ void r600_flush(struct pipe_context *ctx, unsigned flags,
         * without throwing bad code
         */
        sprintf(dname, "gallium-%08d.bof", dc);
-       if (dc < 10)
+       if (dc < 1)
                radeon_ctx_dump_bof(rctx->ctx, dname);
 #if 1
        radeon_ctx_submit(rctx->ctx);
@@ -204,24 +204,6 @@ static void r600_init_config(struct r600_context *rctx)
                num_es_stack_entries = 0;
                break;
        }
-       printf("ps_prio : %d\n", ps_prio);
-       printf("vs_prio : %d\n", vs_prio);
-       printf("gs_prio : %d\n", gs_prio);
-       printf("es_prio : %d\n", es_prio);
-       printf("num_ps_gprs : %d\n", num_ps_gprs);
-       printf("num_vs_gprs : %d\n", num_vs_gprs);
-       printf("num_gs_gprs : %d\n", num_gs_gprs);
-       printf("num_es_gprs : %d\n", num_es_gprs);
-       printf("num_temp_gprs : %d\n", num_temp_gprs);
-       printf("num_ps_threads : %d\n", num_ps_threads);
-       printf("num_vs_threads : %d\n", num_vs_threads);
-       printf("num_gs_threads : %d\n", num_gs_threads);
-       printf("num_es_threads : %d\n", num_es_threads);
-       printf("num_ps_stack_entries : %d\n", num_ps_stack_entries);
-       printf("num_vs_stack_entries : %d\n", num_vs_stack_entries);
-       printf("num_gs_stack_entries : %d\n", num_gs_stack_entries);
-       printf("num_es_stack_entries : %d\n", num_es_stack_entries);
-
        rctx->hw_states.config = radeon_state(rctx->rw, R600_CONFIG_TYPE, R600_CONFIG);
 
        rctx->hw_states.config->states[R600_CONFIG__SQ_CONFIG] = 0x00000000;
index 33dff97d22f670dd00c30b152438756b8def1d2d..8a778f5fd6f33db108c788662edc5f9e36eb70b8 100644 (file)
@@ -105,8 +105,8 @@ int r600_pipe_shader_create(struct pipe_context *ctx,
        struct r600_screen *rscreen = r600_screen(ctx->screen);
        int r;
 
-fprintf(stderr, "--------------------------------------------------------------\n");
-tgsi_dump(tokens, 0);
+//fprintf(stderr, "--------------------------------------------------------------\n");
+//tgsi_dump(tokens, 0);
        if (rpshader == NULL)
                return -ENOMEM;
        rpshader->shader.family = radeon_get_family(rscreen->rw);
@@ -120,7 +120,7 @@ tgsi_dump(tokens, 0);
                R600_ERR("building bytecode failed !\n");
                return r;
        }
-fprintf(stderr, "______________________________________________________________\n");
+//fprintf(stderr, "______________________________________________________________\n");
        return 0;
 }
 
@@ -340,6 +340,7 @@ int r600_shader_from_tgsi(const struct tgsi_token *tokens, struct r600_shader *s
        struct tgsi_full_immediate *immediate;
        struct r600_shader_ctx ctx;
        struct r600_bc_output output[32];
+       unsigned output_done;
        unsigned opcode;
        int i, r = 0, pos0;
 
@@ -431,9 +432,7 @@ int r600_shader_from_tgsi(const struct tgsi_token *tokens, struct r600_shader *s
                output[i].inst = V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT;
                switch (ctx.type == TGSI_PROCESSOR_VERTEX) {
                case TGSI_PROCESSOR_VERTEX:
-                       shader->output[i].type = r600_export_parameter;
                        if (shader->output[i].name == TGSI_SEMANTIC_POSITION) {
-                               shader->output[i].type = r600_export_position;
                                output[i].array_base = 60;
                                output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
                                /* position doesn't count in array_base */
@@ -441,12 +440,10 @@ int r600_shader_from_tgsi(const struct tgsi_token *tokens, struct r600_shader *s
                        }
                        break;
                case TGSI_PROCESSOR_FRAGMENT:
-                       shader->output[i].type = r600_export_framebuffer;
                        if (shader->output[i].name == TGSI_SEMANTIC_COLOR) {
-                               output[i].array_base = 0;
+                               output[i].array_base = shader->output[i].sid;
                                output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
                        } else if (shader->output[i].name == TGSI_SEMANTIC_POSITION) {
-                               shader->output[i].type = r600_export_position;
                                output[i].array_base = 61;
                                output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
                        } else {
@@ -464,9 +461,9 @@ int r600_shader_from_tgsi(const struct tgsi_token *tokens, struct r600_shader *s
                        output[i].end_of_program = 1;
                }
        }
-       for (i = shader->noutput - 1, shader->output_done = 0; i >= 0; i--) {
-               if (!(shader->output_done & (1 << output[i].type))) {
-                       shader->output_done |= (1 << output[i].type);
+       for (i = shader->noutput - 1, output_done = 0; i >= 0; i--) {
+               if (!(output_done & (1 << output[i].type))) {
+                       output_done |= (1 << output[i].type);
                        output[i].inst = V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE;
                }
        }
index 15562c19a52885fc71ae61f7e350cdc60ab1e60e..2ee7780ead0a6e611d10aeb6556c9ec8c5f05afd 100644 (file)
 
 #include "r600_asm.h"
 
-enum r600_export_type {
-       r600_export_position = 0,
-       r600_export_parameter,
-       r600_export_framebuffer,
-};
-
 struct r600_shader_io {
        unsigned                name;
        unsigned                gpr;
        unsigned                done;
-       unsigned                type;
        int                     sid;
        unsigned                interpolate;
 };
@@ -49,7 +42,6 @@ struct r600_shader {
        struct r600_shader_io   input[32];
        struct r600_shader_io   output[32];
        enum radeon_family      family;
-       unsigned                output_done;
 };
 
 #endif
index ef6c1bedeb426e8dab0e12bc41875a7fd9a9e8cb..223f2f390083d2baf0bf4ef95d02679f53834d93 100644 (file)
@@ -1205,7 +1205,7 @@ static struct radeon_state *r600_cb_cntl(struct r600_context *rctx)
        struct r600_screen *rscreen = rctx->screen;
        struct radeon_state *rstate;
        const struct pipe_blend_state *pbs = &rctx->blend->state.blend;
-       int nr_cbufs = rctx->framebuffer->state.framebuffer.nr_cbufs;   
+       int nr_cbufs = rctx->framebuffer->state.framebuffer.nr_cbufs;
        uint32_t color_control, target_mask, shader_mask;
        int i;
 
@@ -1214,20 +1214,29 @@ static struct radeon_state *r600_cb_cntl(struct r600_context *rctx)
        color_control = S_028808_PER_MRT_BLEND(1);
 
        for (i = 0; i < nr_cbufs; i++) {
-               shader_mask |= 0xf << i;
+               shader_mask |= 0xf << (i * 4);
        }
 
        if (pbs->logicop_enable) {
                color_control |= (pbs->logicop_func) << 16;
-       } else
+       } else {
                color_control |= (0xcc << 16);
+       }
 
-       for (i = 0; i < 8; i++) {
-               if (pbs->rt[i].blend_enable) {
-                       color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
+       if (pbs->independent_blend_enable) {
+               for (i = 0; i < 8; i++) {
+                       if (pbs->rt[i].blend_enable) {
+                               color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
+                       }
+                       target_mask |= (pbs->rt[i].colormask << (4 * i));
+               }
+       } else {
+               for (i = 0; i < 8; i++) {
+                       if (pbs->rt[0].blend_enable) {
+                               color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
+                       }
+                       target_mask |= (pbs->rt[0].colormask << (4 * i));
                }
-               target_mask |= (pbs->rt[i].colormask << (4 * i));
-               
        }
        rstate = radeon_state(rscreen->rw, R600_CB_CNTL_TYPE, R600_CB_CNTL);
        rstate->states[R600_CB_CNTL__CB_SHADER_MASK] = shader_mask;