(no commit message)

diff --git a/openpower/sv/setvl.mdwn b/openpower/sv/setvl.mdwn
index aac1c47d7f4c632927b5b06e906f48d51ccc0a85..cd6a10f685d825670a12ec5acba883e14c37dde6 100644 (file)
--- a/openpower/sv/setvl.mdwn
+++ b/openpower/sv/setvl.mdwn
@@ -39,13 +39,15 @@ Page Faults etc. aside this is *guaranteed* 100% without fail to perform 64 unit
 
 # Format
 
-*(Allocation of opcode TBD pending OPF ISA WG approval)*
+*(Allocation of opcode TBD pending OPF ISA WG approval)*,
+using EXT22 temporarily and fitting into the
+[[sv/bitmanip]] space
 
 Form: SVL-Form (see [[isatables/fields.text]])
 
-| 0.5|6.10|11.15|16..23  | 24.25  | 26...30 |31|  name   |
-| -- | -- | --- | ------ | ------ | ------- |--| ------- |
-|OPCD| RT | RA  | SVi /  | vs ms  | XO[0:4] |Rc| setvl   |
+| 0.5|6.10|11.15|16..23  | 24.25  | 26.30 |31|  name   |
+| -- | -- | --- | ------ | ------ | ----- |--| ------- |
+|OPCD| RT | RA  | SVi /  | vs ms  | 11110 |Rc| setvl   |
 
 Note that the immediate (`SVi`) spans 7 bits (16 to 22), and that bit 23 is reserved and must be zero.  Setting bit 23 to 1 causes an illegal exception.