remove numbering from primer summary

diff --git a/openpower/simple_v_spec.tex b/openpower/simple_v_spec.tex
index df481533b0903126066ab94ea53d83e310a3f7a1..e7360f504b1fa9204a5a6db3783e8a5b545bf5d5 100644 (file)
--- a/openpower/simple_v_spec.tex
+++ b/openpower/simple_v_spec.tex
@@ -168,8 +168,8 @@ at:
 
 
 \part{Scalable Vectors Primer}
-\chapter{Executive Summary}
 \input{svp64-primer/acronyms}
+\chapter*{Executive Summary}
 \include{svp64-primer/summary}
 \bibliography{svp64-primer/references}
 \bibliographystyle{ieeetr}

diff --git a/openpower/svp64-primer/acronyms.tex b/openpower/svp64-primer/acronyms.tex
index 99d84855479f2d3482636c6c4daad673268c5645..dffc2bb1082cf8dc4882d6030dbce3aa1e69c775 100644 (file)
--- a/openpower/svp64-primer/acronyms.tex
+++ b/openpower/svp64-primer/acronyms.tex
@@ -1,4 +1,4 @@
-\section{List of Acronyms}
+\section*{List of Acronyms}
 \begin{acronym}
        \acro{ASIC}{Application Specific Integrated Circuit}
        \acro{AVX-512}{Intel Advanced Vector Extensions 512-bit}

diff --git a/openpower/svp64-primer/summary.tex b/openpower/svp64-primer/summary.tex
index 9523bfdf337a2c8d145c97356b433db0c835b3d2..cea39b10e6cb91d20086445b414d3eda3360f437 100644 (file)
--- a/openpower/svp64-primer/summary.tex
+++ b/openpower/svp64-primer/summary.tex
@@ -1,4 +1,4 @@
-\section{Summary}
+\section*{Summary}
 The proposed \acs{SV} is a Scalable Vector Specification for a hardware for-loop \textbf{that
 ONLY uses scalar instructions}.
 
@@ -51,7 +51,7 @@ the Power ISA's Supercomputing pedigree.
 
 \pagebreak
 
-\subsection{What is SIMD?}
+\subsection*{What is SIMD?}
 
 \acs{SIMD} is a way of partitioning existing \acs{CPU}
 registers of 64-bit length into smaller 8-, 16-, 32-bit pieces.
@@ -78,7 +78,7 @@ scalar-only instructions.
 \textit{As long as the data width fits the workload, everything is fine}.
 \par
 
-\subsection{Shortfalls of SIMD}
+\subsection*{Shortfalls of SIMD}
 SIMD registers are of a fixed length and thus to achieve greater
 performance, CPU architects typically increase the width of registers
 (to 128-, 256-, 512-bit etc) for more partitions.\par Additionally,
@@ -103,7 +103,7 @@ the number of instructions increase:
        Multi-issue decoding
 \end{itemize}
 
-\subsection{Scalable Vector Architectures}
+\subsection*{Scalable Vector Architectures}
 An older alternative exists to utilise data parallelism - vector
 architectures. Vector CPUs collect operands from the main memory, and
 store them in large, sequential vector registers.\par
@@ -159,7 +159,7 @@ how a Vector's elements are sequentially and linearly mapped onto the
 
 \pagebreak
 
-\subsection{Simple Vectorisation}
+\subsection*{Simple Vectorisation}
 \acs{SV} is a Scalable Vector ISA designed for hybrid workloads (CPU, GPU,
 VPU, 3D).  Includes features normally found only on Cray-style Supercomputers
 (Cray-1, NEC SX-Aurora) and GPUs.  Keeps to a strict uniform RISC paradigm,