techmap.CONSTMAP: Handle outputs before inputs.

Fixes #2321.

diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc
index c22ae8ef0e2448ad9e6cf2764d5b5c57bdaddaa1..8d16a2baefecc6c51a964c80f121f23289578d7a 100644 (file)
--- a/passes/techmap/techmap.cc
+++ b/passes/techmap/techmap.cc
@@ -801,11 +801,31 @@ struct TechmapWorker
                                                                        }
                                                                }
 
+                                                               // Handle outputs first, as these cannot be remapped.
                                                                for (auto &conn : cell->connections())
+                                                               {
+                                                                       Wire *twire = tpl->wire(conn.first);
+                                                                       if (!twire->port_output)
+                                                                               continue;
+
+                                                                       for (int i = 0; i < GetSize(conn.second); i++) {
+                                                                               RTLIL::SigBit bit = sigmap(conn.second[i]);
+                                                                               RTLIL::SigBit tplbit(twire, i);
+                                                                               cellbits_to_tplbits[bit] = tplbit;
+                                                                       }
+                                                               }
+
+                                                               // Now handle inputs, remapping as necessary.
+                                                               for (auto &conn : cell->connections())
+                                                               {
+                                                                       Wire *twire = tpl->wire(conn.first);
+                                                                       if (twire->port_output)
+                                                                               continue;
+
                                                                        for (int i = 0; i < GetSize(conn.second); i++)
                                                                        {
                                                                                RTLIL::SigBit bit = sigmap(conn.second[i]);
-                                                                               RTLIL::SigBit tplbit(tpl->wire(conn.first), i);
+                                                                               RTLIL::SigBit tplbit(twire, i);
 
                                                                                if (bit.wire == nullptr)
                                                                                {
@@ -820,6 +840,7 @@ struct TechmapWorker
                                                                                else
                                                                                        cellbits_to_tplbits[bit] = tplbit;
                                                                        }
+                                                               }
 
                                                                RTLIL::SigSig port_conn;
                                                                for (auto &it : port_connmap) {

diff --git a/tests/techmap/bug2321.ys b/tests/techmap/bug2321.ys
new file mode 100644 (file)
index 0000000..637528b
--- /dev/null
+++ b/tests/techmap/bug2321.ys
@@ -0,0 +1,15 @@
+read_verilog <<EOT
+module m (input i, output o);
+wire [1023:0] _TECHMAP_DO_00_ = "CONSTMAP; ";
+endmodule
+EOT
+
+design -stash map
+
+read_verilog <<EOT
+module top(output o);
+m m (.o(o), .i(o));
+endmodule
+EOT
+
+techmap -map %map