mention concurrent units, update regfile image to double-up the pipelines

diff --git a/3d_gpu/architecture/regfile.mdwn b/3d_gpu/architecture/regfile.mdwn
index b59ebad67f82ac09d0d4e204941ba1f87da4c275..444f62da051beb9eb7bd118dd7472423a4533821 100644 (file)
--- a/3d_gpu/architecture/regfile.mdwn
+++ b/3d_gpu/architecture/regfile.mdwn
@@ -24,8 +24,9 @@ This then requires some Bus Architecture to connect and keep the pipelines
 busy.  Below is the connectivity diagram:
 
 * A single Dynamic PartitionedSignal capable 64-bit-wide pipeline is at the
-  top (a second Dynamic pipeline is off-page, with its own FUs)
-* A **pair** of 32-bit Function Units connect to the (shared) pipeline.
+  top left and top right.
+* Multiple **pairs** of 32-bit Function Units (making up a 64-bit data
+  path) connect, as "Concurrent Units", to each pipeline.
 * The number of **pairs** of Function Units **must** match (or preferably
   exceed) the number of pipeline stages.
 * Connected to each of the Operand and Result Ports on each Function Unit
@@ -64,5 +65,6 @@ Notes:
   of an FMAC is extended by 3 cycles: this being the fact that only one
   CDB is available to deliver operands.
 
+Click on the image to expand it full-screen:
 
 [[!img regfile_hilo_32_odd_even.png size="500px"]]

diff --git a/3d_gpu/regfile_hilo_32_odd_even.png b/3d_gpu/regfile_hilo_32_odd_even.png
index c2d7f26882bb6d55f9c493d570d64ab8cc7688ee..7fa3e426c041d0650264083d90f234c9c7deb1ef 100644 (file)
Binary files a/3d_gpu/regfile_hilo_32_odd_even.png and b/3d_gpu/regfile_hilo_32_odd_even.png differ