cores/clock/S7: just reset the generated clock, not the PLL/MMCM

diff --git a/litex/soc/cores/clock.py b/litex/soc/cores/clock.py
index c11dfb16f11d51d1feed897c3cde45a8eea95835..a4cbb6336392b94f551468ef97a46717a4171240 100644 (file)
--- a/litex/soc/cores/clock.py
+++ b/litex/soc/cores/clock.py
@@ -138,7 +138,7 @@ class S7PLL(S7Clocking):
         config = self.compute_config()
         pll_fb = Signal()
         self.params.update(
-            p_STARTUP_WAIT="FALSE", i_RST=self.reset, o_LOCKED=self.locked,
+            p_STARTUP_WAIT="FALSE", o_LOCKED=self.locked,
 
             # VCO
             p_REF_JITTER1=0.01, p_CLKIN1_PERIOD=period_ns(self.clkin_freq),
@@ -174,7 +174,7 @@ class S7MMCM(S7Clocking):
         config = self.compute_config()
         mmcm_fb = Signal()
         self.params.update(
-            p_BANDWIDTH="OPTIMIZED", i_RST=self.reset, o_LOCKED=self.locked,
+            p_BANDWIDTH="OPTIMIZED", o_LOCKED=self.locked,
 
             # VCO
             p_REF_JITTER1=0.01, p_CLKIN1_PERIOD=period_ns(self.clkin_freq),