Fix early-clobber in amdgcn vec_extract

2020-01-06  Andrew Stubbs  <ams@codesourcery.com>

	gcc/
	* config/gcn/gcn-valu.md (vec_extract<mode><scalar_mode>): Add early
	clobber.

From-SVN: r279904

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 820a86f353d2261a8d8a8fbcf99679dd42b79b74..8084d5ca5125ba3a1f4ce8015c97b84344a86836 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2020-01-06  Andrew Stubbs  <ams@codesourcery.com>
+
+       * config/gcn/gcn-valu.md (vec_extract<mode><scalar_mode>): Add early
+       clobber.
+
 2020-01-06  Richard Sandiford  <richard.sandiford@arm.com>
 
        * config/aarch64/t-aarch64 ($(srcdir)/config/aarch64/aarch64-tune.md):

diff --git a/gcc/config/gcn/gcn-valu.md b/gcc/config/gcn/gcn-valu.md
index 457a66c1505a06da8849c4a721c0c2ddd3cb6c7d..9baef24b1c8777800e07926f23d0bbf81c85dac3 100644 (file)
--- a/gcc/config/gcn/gcn-valu.md
+++ b/gcc/config/gcn/gcn-valu.md
@@ -580,10 +580,10 @@
    (set_attr "laneselect" "yes")])
 
 (define_insn "vec_extract<mode><scalar_mode>"
-  [(set (match_operand:<SCALAR_MODE> 0 "register_operand"   "=Sg")
+  [(set (match_operand:<SCALAR_MODE> 0 "register_operand"   "=&Sg")
        (vec_select:<SCALAR_MODE>
-         (match_operand:VEC_2REG_MODE 1 "register_operand" "  v")
-         (parallel [(match_operand:SI 2 "gcn_alu_operand"  "SvB")])))]
+         (match_operand:VEC_2REG_MODE 1 "register_operand" "   v")
+         (parallel [(match_operand:SI 2 "gcn_alu_operand"  " SvB")])))]
   ""
   "v_readlane_b32 %L0, %L1, %2\;v_readlane_b32 %H0, %H1, %2"
   [(set_attr "type" "vmult")