Use default parameter value in getParam

Fixes #1822.

diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 0e934726765acba8da125627905328d090aaa8a7..2aefe30b1543f3f663c40a202344458232c2ad5b 100644 (file)
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -2619,7 +2619,16 @@ void RTLIL::Cell::setParam(RTLIL::IdString paramname, RTLIL::Const value)
 
 const RTLIL::Const &RTLIL::Cell::getParam(RTLIL::IdString paramname) const
 {
-       return parameters.at(paramname);
+       static const RTLIL::Const empty;
+       const auto &it = parameters.find(paramname);
+       if (it != parameters.end())
+               return it->second;
+       if (module && module->design) {
+               RTLIL::Module *m = module->design->module(type);
+               if (m)
+                       return m->parameter_default_values.at(paramname, empty);
+       }
+       return empty;
 }
 
 void RTLIL::Cell::sort()

diff --git a/techlibs/xilinx/xilinx_dffopt.cc b/techlibs/xilinx/xilinx_dffopt.cc
index ac9b57fe14e549e87a536198bfdada26d45a0f04..c608db883302183c3186afe96b66abe0ff45a3f8 100644 (file)
--- a/techlibs/xilinx/xilinx_dffopt.cc
+++ b/techlibs/xilinx/xilinx_dffopt.cc
@@ -209,7 +209,7 @@ lut_sigin_done:
                                        continue;
                                LutData lut_d = it_D->second.first;
                                Cell *cell_d = it_D->second.second;
-                               if (cell->hasParam(ID(IS_D_INVERTED)) && cell->getParam(ID(IS_D_INVERTED)).as_bool()) {
+                               if (cell->getParam(ID(IS_D_INVERTED)).as_bool()) {
                                        // Flip all bits in the LUT.
                                        for (int i = 0; i < GetSize(lut_d.first); i++)
                                                lut_d.first.bits[i] = (lut_d.first.bits[i] == State::S1) ? State::S0 : State::S1;
@@ -249,7 +249,7 @@ lut_sigin_done:
                                if (has_s) {
                                        SigBit sig_S = sigmap(cell->getPort(ID::S));
                                        LutData lut_s = LutData(Const(2, 2), {sig_S});
-                                       bool inv_s = cell->hasParam(ID(IS_S_INVERTED)) && cell->getParam(ID(IS_S_INVERTED)).as_bool();
+                                       bool inv_s = cell->getParam(ID(IS_S_INVERTED)).as_bool();
                                        auto it_S = bit_to_lut.find(sig_S);
                                        if (it_S != bit_to_lut.end())
                                                lut_s = it_S->second.first;
@@ -271,7 +271,7 @@ lut_sigin_done:
                                if (has_r) {
                                        SigBit sig_R = sigmap(cell->getPort(ID::R));
                                        LutData lut_r = LutData(Const(2, 2), {sig_R});
-                                       bool inv_r = cell->hasParam(ID(IS_R_INVERTED)) && cell->getParam(ID(IS_R_INVERTED)).as_bool();
+                                       bool inv_r = cell->getParam(ID(IS_R_INVERTED)).as_bool();
                                        auto it_R = bit_to_lut.find(sig_R);
                                        if (it_R != bit_to_lut.end())
                                                lut_r = it_R->second.first;