* config/arc/arc.h (LOGICAL_OP_NON_SHORT_CIRCUIT): Define.

From-SVN: r204666

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index ea7d382357a66848c1c6cb4d03eaa46af0b390d6..6c55b69e6609f67e6e9e66ad21acdced5f517690 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,7 @@
+2013-11-11  Joern Rennecke  <joern.rennecke@embecosm.com>
+
+       * config/arc/arc.h (LOGICAL_OP_NON_SHORT_CIRCUIT): Define.
+
 2013-11-08  Jeff Law  <law@redhat.com>
 
        * tree-ssa-threadupdate.c (mark_threaded_blocks): Truncate jump

diff --git a/gcc/config/arc/arc.h b/gcc/config/arc/arc.h
index 87908d41afc6976c74c008da4dc1a340caf69050..cc49c553c55dc17f198c29bd671665fd6c9f2a45 100644 (file)
--- a/gcc/config/arc/arc.h
+++ b/gcc/config/arc/arc.h
@@ -1087,6 +1087,22 @@ arc_select_cc_mode (OP, X, Y)
    expensive than reg->reg moves.  */
 #define BRANCH_COST(speed_p, predictable_p) 2
 
+/* Scc sets the destination to 1 and then conditionally zeroes it.
+   Best case, ORed SCCs can be made into clear - condset - condset.
+   But it could also end up as five insns.  So say it costs four on
+   average.
+   These extra instructions - and the second comparison - will also be
+   an extra cost if the first comparison would have been decisive.
+   So get an average saving, with a probability of the first branch
+   beging decisive of p0, we want:
+   p0 * (branch_cost - 4) > (1 - p0) * 5
+   ??? We don't get to see that probability to evaluate, so we can
+   only wildly guess that it might be 50%.
+   ??? The compiler also lacks the notion of branch predictability.  */
+#define LOGICAL_OP_NON_SHORT_CIRCUIT \
+  (BRANCH_COST (optimize_function_for_speed_p (cfun), \
+               false) > 9)
+
 /* Nonzero if access to memory by bytes is slow and undesirable.
    For RISC chips, it means that access to memory by bytes is no
    better than access by words when possible, so grab a whole word