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rs6000.md (iorxor): New code_iterator.
authorSegher Boessenkool <segher@kernel.crashing.org>
Sun, 21 Sep 2014 18:01:01 +0000 (20:01 +0200)
committerSegher Boessenkool <segher@gcc.gnu.org>
Sun, 21 Sep 2014 18:01:01 +0000 (20:01 +0200)
2014-09-21  Segher Boessenkool  <segher@kernel.crashing.org>

* config/rs6000/rs6000.md (iorxor): New code_iterator.
(iorxor): New code_attr.
(IORXOR): New code_attr.
(*and<mode>3, *and<mode>3_dot, *and<mode>3_dot2): Delete.
(ior<mode>3, xor<mode>3): Delete.
(<iorxor><mode>3): New.
(splitter for "big" integer ior, xor): New.
(*bool<mode>3): Move.  Also handle AND.
(*bool<mode>3_dot, *bool<mode>3_dot2): Also handle AND.
(splitter for "big" integer ior, xor): Delete.

From-SVN: r215433

gcc/ChangeLog patch | blob | history
gcc/config/rs6000/rs6000.md patch | blob | history

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index b3aa885c7605df57fecc229d8a01c7d9c4382ef8..af1ebbc64a0d968b531f9a3166b84118d0fbef16 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,16 @@
+2014-09-21  Segher Boessenkool  <segher@kernel.crashing.org>
+
+       * config/rs6000/rs6000.md (iorxor): New code_iterator.
+       (iorxor): New code_attr.
+       (IORXOR): New code_attr.
+       (*and<mode>3, *and<mode>3_dot, *and<mode>3_dot2): Delete.
+       (ior<mode>3, xor<mode>3): Delete.
+       (<iorxor><mode>3): New.
+       (splitter for "big" integer ior, xor): New.
+       (*bool<mode>3): Move.  Also handle AND.
+       (*bool<mode>3_dot, *bool<mode>3_dot2): Also handle AND.
+       (splitter for "big" integer ior, xor): Delete.
+
 2014-09-21  Segher Boessenkool  <segher@kernel.crashing.org>
 
        * config/rs6000/rs6000.md (*neg<mode>2_internal): Delete.
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 48cc73deb9e830178cf2c915e0ff74b6fa4763af..b2f5c55534fa8b8d18ddd276876c8b055a8a419d 100644 (file)
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -438,6 +438,11 @@
                               (simple_return "1")])
 (define_code_attr return_str [(return "") (simple_return "simple_")])
 
+; Logical operators.
+(define_code_iterator iorxor [ior xor])
+(define_code_attr iorxor [(ior "ior") (xor "xor")])
+(define_code_attr IORXOR [(ior "IOR") (xor "XOR")])
+
 ; Signed/unsigned variants of ops.
 (define_code_iterator any_extend [sign_extend zero_extend])
 (define_code_attr u [(sign_extend "") (zero_extend "u")])
@@ -2640,61 +2645,6 @@
 })
 
 
-(define_insn "*and<mode>3"
-  [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
-       (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
-                (match_operand:GPR 2 "gpc_reg_operand" "r")))]
-  ""
-  "and %0,%1,%2"
-  [(set_attr "type" "logical")])
-
-(define_insn_and_split "*and<mode>3_dot"
-  [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
-       (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
-                            (match_operand:GPR 2 "gpc_reg_operand" "r,r"))
-                   (const_int 0)))
-   (clobber (match_scratch:GPR 0 "=r,r"))]
-  "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
-  "@
-   and. %0,%1,%2
-   #"
-  "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
-  [(set (match_dup 0)
-       (and:GPR (match_dup 1)
-                (match_dup 2)))
-   (set (match_dup 3)
-       (compare:CC (match_dup 0)
-                   (const_int 0)))]
-  ""
-  [(set_attr "type" "logical")
-   (set_attr "dot" "yes")
-   (set_attr "length" "4,8")])
-
-(define_insn_and_split "*and<mode>3_dot2"
-  [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
-       (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
-                            (match_operand:GPR 2 "gpc_reg_operand" "r,r"))
-                   (const_int 0)))
-   (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
-       (and:GPR (match_dup 1)
-                (match_dup 2)))]
-  "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
-  "@
-   and. %0,%1,%2
-   #"
-  "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
-  [(set (match_dup 0)
-       (and:GPR (match_dup 1)
-                (match_dup 2)))
-   (set (match_dup 3)
-       (compare:CC (match_dup 0)
-                   (const_int 0)))]
-  ""
-  [(set_attr "type" "logical")
-   (set_attr "dot" "yes")
-   (set_attr "length" "4,8")])
-
-
 (define_insn "and<mode>3_imm"
   [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
        (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r")
@@ -2913,15 +2863,15 @@
   [(set_attr "length" "8")])
 
 
-(define_expand "ior<mode>3"
+(define_expand "<iorxor><mode>3"
   [(set (match_operand:SDI 0 "gpc_reg_operand" "")
-       (ior:SDI (match_operand:SDI 1 "gpc_reg_operand" "")
-                (match_operand:SDI 2 "reg_or_cint_operand" "")))]
+       (iorxor:SDI (match_operand:SDI 1 "gpc_reg_operand" "")
+                   (match_operand:SDI 2 "reg_or_cint_operand" "")))]
   ""
 {
   if (<MODE>mode == DImode && !TARGET_POWERPC64)
     {
-      rs6000_split_logical (operands, IOR, false, false, false);
+      rs6000_split_logical (operands, <IORXOR>, false, false, false);
       DONE;
     }
 
@@ -2930,12 +2880,13 @@
       rtx tmp = ((!can_create_pseudo_p ()
                  || rtx_equal_p (operands[0], operands[1]))
                 ? operands[0] : gen_reg_rtx (<MODE>mode));
-      HOST_WIDE_INT value = INTVAL (operands[2]);
 
-      emit_insn (gen_ior<mode>3 (tmp, operands[1],
-                            GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
+      HOST_WIDE_INT value = INTVAL (operands[2]);
+      HOST_WIDE_INT lo = value & 0xffff;
+      HOST_WIDE_INT hi = value - lo;
 
-      emit_insn (gen_ior<mode>3 (operands[0], tmp, GEN_INT (value & 0xffff)));
+      emit_insn (gen_<iorxor><mode>3 (tmp, operands[1], GEN_INT (hi)));
+      emit_insn (gen_<iorxor><mode>3 (operands[0], tmp, GEN_INT (lo)));
       DONE;
     }
 
@@ -2943,45 +2894,30 @@
     operands[2] = force_reg (<MODE>mode, operands[2]);
 })
 
-(define_expand "xor<mode>3"
-  [(set (match_operand:SDI 0 "gpc_reg_operand" "")
-       (xor:SDI (match_operand:SDI 1 "gpc_reg_operand" "")
-                (match_operand:SDI 2 "reg_or_cint_operand" "")))]
+(define_split
+  [(set (match_operand:GPR 0 "gpc_reg_operand" "")
+       (iorxor:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
+                   (match_operand:GPR 2 "non_logical_cint_operand" "")))]
   ""
+  [(set (match_dup 3)
+       (iorxor:GPR (match_dup 1)
+                   (match_dup 4)))
+   (set (match_dup 0)
+       (iorxor:GPR (match_dup 3)
+                   (match_dup 5)))]
 {
-  if (<MODE>mode == DImode && !TARGET_POWERPC64)
-    {
-      rs6000_split_logical (operands, XOR, false, false, false);
-      DONE;
-    }
-
-  if (non_logical_cint_operand (operands[2], <MODE>mode))
-    {
-      rtx tmp = ((!can_create_pseudo_p ()
+  operands[3] = ((!can_create_pseudo_p ()
                  || rtx_equal_p (operands[0], operands[1]))
                 ? operands[0] : gen_reg_rtx (<MODE>mode));
-      HOST_WIDE_INT value = INTVAL (operands[2]);
-
-      emit_insn (gen_xor<mode>3 (tmp, operands[1],
-                            GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
 
-      emit_insn (gen_xor<mode>3 (operands[0], tmp, GEN_INT (value & 0xffff)));
-      DONE;
-    }
+  HOST_WIDE_INT value = INTVAL (operands[2]);
+  HOST_WIDE_INT lo = value & 0xffff;
+  HOST_WIDE_INT hi = value - lo;
 
-  if (!reg_or_logical_cint_operand (operands[2], <MODE>mode))
-    operands[2] = force_reg (<MODE>mode, operands[2]);
+  operands[4] = GEN_INT (hi);
+  operands[5] = GEN_INT (lo);
 })
 
-(define_insn "*bool<mode>3"
-  [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
-       (match_operator:GPR 3 "boolean_or_operator"
-        [(match_operand:GPR 1 "gpc_reg_operand" "r")
-         (match_operand:GPR 2 "gpc_reg_operand" "r")]))]
-  ""
-  "%q3 %0,%1,%2"
-  [(set_attr "type" "logical")])
-
 (define_insn "*bool<mode>3_imm"
   [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
        (match_operator:GPR 3 "boolean_or_operator"
@@ -2991,9 +2927,18 @@
   "%q3i%e2 %0,%1,%u2"
   [(set_attr "type" "logical")])
 
+(define_insn "*bool<mode>3"
+  [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
+       (match_operator:GPR 3 "boolean_operator"
+        [(match_operand:GPR 1 "gpc_reg_operand" "r")
+         (match_operand:GPR 2 "gpc_reg_operand" "r")]))]
+  ""
+  "%q3 %0,%1,%2"
+  [(set_attr "type" "logical")])
+
 (define_insn_and_split "*bool<mode>3_dot"
   [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
-       (compare:CC (match_operator:GPR 3 "boolean_or_operator"
+       (compare:CC (match_operator:GPR 3 "boolean_operator"
         [(match_operand:GPR 1 "gpc_reg_operand" "r,r")
          (match_operand:GPR 2 "gpc_reg_operand" "r,r")])
         (const_int 0)))
@@ -3015,7 +2960,7 @@
 
 (define_insn_and_split "*bool<mode>3_dot2"
   [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
-       (compare:CC (match_operator:GPR 3 "boolean_or_operator"
+       (compare:CC (match_operator:GPR 3 "boolean_operator"
         [(match_operand:GPR 1 "gpc_reg_operand" "r,r")
          (match_operand:GPR 2 "gpc_reg_operand" "r,r")])
         (const_int 0)))
@@ -3036,27 +2981,6 @@
    (set_attr "dot" "yes")
    (set_attr "length" "4,8")])
 
-;; Split a logical operation that we can't do in one insn into two insns,
-;; each of which does one 16-bit part.  This is used by combine.
-
-(define_split
-  [(set (match_operand:GPR 0 "gpc_reg_operand" "")
-       (match_operator:GPR 3 "boolean_or_operator"
-        [(match_operand:GPR 1 "gpc_reg_operand" "")
-         (match_operand:GPR 2 "non_logical_cint_operand" "")]))]
-  ""
-  [(set (match_dup 0) (match_dup 4))
-   (set (match_dup 0) (match_dup 5))]
-{
-  rtx i;
-  i = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff));
-  operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), <MODE>mode,
-                               operands[1], i);
-  i = GEN_INT (INTVAL (operands[2]) & 0xffff);
-  operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), <MODE>mode,
-                               operands[0], i);
-})
-
 
 (define_insn "*boolc<mode>3"
   [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")