arch, cpu: Add a takeOverFrom method for switching ISAs

This will be used by architectures to handle the m5.switchCpus at the
ISA level since some ISA specific fields might need to be aware of the
TC change.

Change-Id: If8d50c5c80bc3458d5f1d14cf93ae107314c98cf
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27712
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

diff --git a/src/arch/generic/isa.hh b/src/arch/generic/isa.hh
index 804462a365ede580bc54eadd8cefd1da0437d580..d4f6d9f8b890abef379df13a25e73986ed19d9cb 100644 (file)
--- a/src/arch/generic/isa.hh
+++ b/src/arch/generic/isa.hh
@@ -1,4 +1,16 @@
 /*
+ * Copyright (c) 2020 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
  * Copyright 2020 Google Inc.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -30,10 +42,17 @@
 
 #include "sim/sim_object.hh"
 
+class ThreadContext;
+
 class BaseISA : public SimObject
 {
   protected:
     using SimObject::SimObject;
+
+  public:
+    virtual void
+    takeOverFrom(ThreadContext *new_tc, ThreadContext *old_tc)
+    {}
 };
 
 #endif // __ARCH_GENERIC_ISA_HH__

diff --git a/src/cpu/o3/thread_context_impl.hh b/src/cpu/o3/thread_context_impl.hh
index 104e63cab93db5c0bfcebbd12a563d618381bf17..7a2c830707a8f496661ba4e8115a2c066ef018f0 100644 (file)
--- a/src/cpu/o3/thread_context_impl.hh
+++ b/src/cpu/o3/thread_context_impl.hh
@@ -69,6 +69,9 @@ void
 O3ThreadContext<Impl>::takeOverFrom(ThreadContext *old_context)
 {
     ::takeOverFrom(*this, *old_context);
+
+    this->getIsaPtr()->takeOverFrom(this, old_context);
+
     TheISA::Decoder *newDecoder = getDecoderPtr();
     TheISA::Decoder *oldDecoder = old_context->getDecoderPtr();
     newDecoder->takeOverFrom(oldDecoder);

diff --git a/src/cpu/simple_thread.cc b/src/cpu/simple_thread.cc
index 7574c4d7e6d43353894e71d7e4b94758fa761831..9e2e55e8e4bd91193be68ab87e33261bdc2c63af 100644 (file)
--- a/src/cpu/simple_thread.cc
+++ b/src/cpu/simple_thread.cc
@@ -121,6 +121,8 @@ SimpleThread::takeOverFrom(ThreadContext *oldContext)
     ::takeOverFrom(*this, *oldContext);
     decoder.takeOverFrom(oldContext->getDecoderPtr());
 
+    isa->takeOverFrom(this, oldContext);
+
     kernelStats = oldContext->getKernelStats();
     funcExeInst = oldContext->readFuncExeInst();
     storeCondFailures = 0;