(no commit message)

diff --git a/openpower/sv/bitmanip.mdwn b/openpower/sv/bitmanip.mdwn
index 3b652dae914317c5e51d9c722e21910d1f6e0c5f..d56cd788c7c802b80d95f8c574703836d86a6f29 100644 (file)
--- a/openpower/sv/bitmanip.mdwn
+++ b/openpower/sv/bitmanip.mdwn
@@ -118,9 +118,9 @@ similar to matrix permute in RV bitmanip, which has XOR and OR variants
          b = VSR[VRB+32].dword[i].byte[k].bit[j]
          VSR[VRT+32].dword[i].byte[j].bit[k] = b
 
-# vector bit deposit
+#  bit deposit
 
-vpdepd VRT,VRA,VRB, identical to RV bitmamip bdep
+vpdepd VRT,VRA,VRB, identical to RV bitmamip bdep, found already in v3.1 p106
 
     do while(m < 64)
        if VSR[VRB+32].dword[i].bit[63-m]=1 then do
@@ -145,9 +145,9 @@ uint_xlen_t bdep(uint_xlen_t RA, uint_xlen_t RB)
 
 ```
 
-# vector bit extract
+# bit extract
 
-other way round: identical to RV bext
+other way round: identical to RV bext, found in v3.1 p196
 
 ```
 uint_xlen_t bext(uint_xlen_t RA, uint_xlen_t RB)
@@ -163,6 +163,18 @@ uint_xlen_t bext(uint_xlen_t RA, uint_xlen_t RB)
 }
 ```
 
+# centrifuge
+
+found in v3.1 p106
+
+```
+ptr0 ← 0 ptr1 ← 0 do i = 0 to 63 if((RB)i=0) then do
+resultptr0 ← (RS)i end ptr0 ← ptr0 + 1
+if((RB)63-i==1) then do
+result63-ptr1 ← (RS)63-i end end ptr1 ← ptr1 + 1
+RA ← result
+```
+
 # int min/max
 
 signed and unsigned min/max for integer.  this is sort-of partly synthesiseable in [[sv/svp64]] with pred-result as long as the dest reg is one of the sources, but not both signed and unsigned.  when the dest is also one of the srces and the mv fails due to the CR bittest failing this will only overwrite the dest where the src is greater (or less).