---------- Begin Simulation Statistics ----------
-host_inst_rate 138841 # Simulator instruction rate (inst/s)
-host_mem_usage 198176 # Number of bytes of host memory used
-host_seconds 10123.96 # Real time elapsed on the host
-host_tick_rate 108192045 # Simulator tick rate (ticks/s)
+host_inst_rate 119996 # Simulator instruction rate (inst/s)
+host_mem_usage 230000 # Number of bytes of host memory used
+host_seconds 11713.80 # Real time elapsed on the host
+host_tick_rate 51345807 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 1405618374 # Number of instructions simulated
-sim_seconds 1.095331 # Number of seconds simulated
-sim_ticks 1095331467500 # Number of ticks simulated
+sim_insts 1405604152 # Number of instructions simulated
+sim_seconds 0.601455 # Number of seconds simulated
+sim_ticks 601454696500 # Number of ticks simulated
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.BTBHits 175591574 # Number of BTB hits
-system.cpu.BPredUnit.BTBLookups 198504175 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 98804348 # Number of BTB hits
+system.cpu.BPredUnit.BTBLookups 100538146 # Number of BTB lookups
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
-system.cpu.BPredUnit.condIncorrect 83489596 # Number of conditional branches incorrect
-system.cpu.BPredUnit.condPredicted 252577407 # Number of conditional branches predicted
-system.cpu.BPredUnit.lookups 252577407 # Number of BP lookups
+system.cpu.BPredUnit.condIncorrect 5348299 # Number of conditional branches incorrect
+system.cpu.BPredUnit.condPredicted 105812900 # Number of conditional branches predicted
+system.cpu.BPredUnit.lookups 105812900 # Number of BP lookups
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.commit.COM:branches 86248929 # Number of branches committed
-system.cpu.commit.COM:bw_lim_events 9068364 # number cycles where commit BW limit reached
+system.cpu.commit.COM:bw_lim_events 21328327 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle::samples 1951658061 # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::mean 0.763216 # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::stdev 1.203742 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::samples 1172134111 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::mean 1.270779 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::stdev 1.680126 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::0 1079992719 55.34% 55.34% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::1 573544089 29.39% 84.72% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::2 118996755 6.10% 90.82% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::3 118578034 6.08% 96.90% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::4 27958213 1.43% 98.33% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::5 7829070 0.40% 98.73% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::6 11095017 0.57% 99.30% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::7 4595800 0.24% 99.54% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::8 9068364 0.46% 100.00% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::0 418023744 35.66% 35.66% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::1 498322579 42.51% 78.18% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::2 52995965 4.52% 82.70% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::3 103673250 8.84% 91.54% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::4 32915504 2.81% 94.35% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::5 8294294 0.71% 95.06% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::6 25634202 2.19% 97.25% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::7 10946246 0.93% 98.18% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::8 21328327 1.82% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::total 1951658061 # Number of insts commited each cycle
-system.cpu.commit.COM:count 1489537517 # Number of instructions committed
-system.cpu.commit.COM:loads 402517252 # Number of loads committed
+system.cpu.commit.COM:committed_per_cycle::total 1172134111 # Number of insts commited each cycle
+system.cpu.commit.COM:count 1489523295 # Number of instructions committed
+system.cpu.commit.COM:loads 402512844 # Number of loads committed
system.cpu.commit.COM:membars 51356 # Number of memory barriers committed
-system.cpu.commit.COM:refs 569375208 # Number of memory references committed
+system.cpu.commit.COM:refs 569360986 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.branchMispredicts 83489596 # The number of times a branch was mispredicted
-system.cpu.commit.commitCommittedInsts 1489537517 # The number of committed instructions
+system.cpu.commit.branchMispredicts 5348299 # The number of times a branch was mispredicted
+system.cpu.commit.commitCommittedInsts 1489523295 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 2243671 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts 1344365389 # The number of squashed insts skipped by commit
-system.cpu.committedInsts 1405618374 # Number of Instructions Simulated
-system.cpu.committedInsts_total 1405618374 # Number of Instructions Simulated
-system.cpu.cpi 1.558505 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 1.558505 # CPI: Total CPI of All Threads
-system.cpu.dcache.ReadReq_accesses 428071377 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 13932.868577 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 6644.344451 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 427202678 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 12103469000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.002029 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 868699 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits 619015 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency 1658986500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.000583 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 249684 # number of ReadReq MSHR misses
+system.cpu.commit.commitSquashedInsts 219352878 # The number of squashed insts skipped by commit
+system.cpu.committedInsts 1405604152 # Number of Instructions Simulated
+system.cpu.committedInsts_total 1405604152 # Number of Instructions Simulated
+system.cpu.cpi 0.855795 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.855795 # CPI: Total CPI of All Threads
+system.cpu.dcache.ReadReq_accesses 295701747 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 14658.100936 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7465.537350 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 294883428 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 11995002500 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.002767 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 818319 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits 604827 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency 1593832500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.000722 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 213492 # number of ReadReq MSHR misses
system.cpu.dcache.SwapReq_accesses 1326 # number of SwapReq accesses(hits+misses)
-system.cpu.dcache.SwapReq_avg_miss_latency 38071.428571 # average SwapReq miss latency
-system.cpu.dcache.SwapReq_avg_mshr_miss_latency 35071.428571 # average SwapReq mshr miss latency
+system.cpu.dcache.SwapReq_avg_miss_latency 38214.285714 # average SwapReq miss latency
+system.cpu.dcache.SwapReq_avg_mshr_miss_latency 35214.285714 # average SwapReq mshr miss latency
system.cpu.dcache.SwapReq_hits 1319 # number of SwapReq hits
-system.cpu.dcache.SwapReq_miss_latency 266500 # number of SwapReq miss cycles
+system.cpu.dcache.SwapReq_miss_latency 267500 # number of SwapReq miss cycles
system.cpu.dcache.SwapReq_miss_rate 0.005279 # miss rate for SwapReq accesses
system.cpu.dcache.SwapReq_misses 7 # number of SwapReq misses
-system.cpu.dcache.SwapReq_mshr_miss_latency 245500 # number of SwapReq MSHR miss cycles
+system.cpu.dcache.SwapReq_mshr_miss_latency 246500 # number of SwapReq MSHR miss cycles
system.cpu.dcache.SwapReq_mshr_miss_rate 0.005279 # mshr miss rate for SwapReq accesses
system.cpu.dcache.SwapReq_mshr_misses 7 # number of SwapReq MSHR misses
-system.cpu.dcache.WriteReq_accesses 166856630 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 14486.830110 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 11574.912497 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 165064790 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 25958081664 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.010739 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 1791840 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits 1512123 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency 3237699799 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.001676 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 279717 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_accesses 166846816 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency 15552.165643 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 12826.834160 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 165080576 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 27468857045 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.010586 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 1766240 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_hits 1498175 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_miss_latency 3438425299 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.001607 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 268065 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 1118.737886 # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs 955.148896 # Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 594928007 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 14305.954795 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 9249.484415 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 592267468 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 38061550664 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.004472 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 2660539 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 2131138 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 4896686299 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.000890 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 529401 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_accesses 462548563 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 15269.088284 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 10449.973314 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 459964004 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 39463859545 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.005588 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 2584559 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 2103002 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 5032257799 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.001041 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 481557 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0 0.999897 # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0 4095.577700 # Average occupied blocks per context
-system.cpu.dcache.overall_accesses 594928007 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 14305.954795 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 9249.484415 # average overall mshr miss latency
+system.cpu.dcache.occ_%::0 0.999860 # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0 4095.424781 # Average occupied blocks per context
+system.cpu.dcache.overall_accesses 462548563 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 15269.088284 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 10449.973314 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 592267468 # number of overall hits
-system.cpu.dcache.overall_miss_latency 38061550664 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.004472 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 2660539 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 2131138 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 4896686299 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.000890 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 529401 # number of overall MSHR misses
+system.cpu.dcache.overall_hits 459964004 # number of overall hits
+system.cpu.dcache.overall_miss_latency 39463859545 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.005588 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 2584559 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 2103002 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 5032257799 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.001041 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 481557 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.replacements 525312 # number of replacements
-system.cpu.dcache.sampled_refs 529408 # Sample count of references to valid blocks.
+system.cpu.dcache.replacements 477468 # number of replacements
+system.cpu.dcache.sampled_refs 481564 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 4095.577700 # Cycle average of tags in use
-system.cpu.dcache.total_refs 592268787 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 165936000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 467492 # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles 419165001 # Number of cycles decode is blocked
-system.cpu.decode.DECODE:DecodedInsts 3408944329 # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles 761736999 # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles 767859019 # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles 238675861 # Number of cycles decode is squashing
-system.cpu.decode.DECODE:UnblockCycles 2897042 # Number of cycles decode is unblocking
-system.cpu.fetch.Branches 252577407 # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines 355041427 # Number of cache lines fetched
-system.cpu.fetch.Cycles 1184621367 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes 11557522 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts 3696750718 # Number of instructions fetch has processed
-system.cpu.fetch.SquashCycles 90055290 # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate 0.115297 # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles 355041427 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches 175591574 # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate 1.687503 # Number of inst fetches per cycle
-system.cpu.fetch.rateDist::samples 2190333922 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 1.687757 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.837142 # Number of instructions fetched each cycle (Total)
+system.cpu.dcache.tagsinuse 4095.424781 # Cycle average of tags in use
+system.cpu.dcache.total_refs 459965323 # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 132220000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 428419 # number of writebacks
+system.cpu.decode.DECODE:BlockedCycles 393630434 # Number of cycles decode is blocked
+system.cpu.decode.DECODE:DecodedInsts 1750728609 # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles 405694605 # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles 351105685 # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles 30409425 # Number of cycles decode is squashing
+system.cpu.decode.DECODE:UnblockCycles 21703387 # Number of cycles decode is unblocking
+system.cpu.fetch.Branches 105812900 # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines 173095521 # Number of cache lines fetched
+system.cpu.fetch.Cycles 548231197 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes 1429406 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Insts 1760522570 # Number of instructions fetch has processed
+system.cpu.fetch.SquashCycles 6170035 # Number of cycles fetch has spent squashing
+system.cpu.fetch.branchRate 0.087964 # Number of branch fetches per cycle
+system.cpu.fetch.icacheStallCycles 173095521 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches 98804348 # Number of branches that fetch has predicted taken
+system.cpu.fetch.rate 1.463554 # Number of inst fetches per cycle
+system.cpu.fetch.rateDist::samples 1202543536 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 1.463999 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.699989 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 1360754025 62.13% 62.13% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 248782776 11.36% 73.48% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 79015111 3.61% 77.09% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 36736924 1.68% 78.77% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 85275355 3.89% 82.66% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 39319900 1.80% 84.46% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 30979848 1.41% 85.87% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 19612924 0.90% 86.77% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 289857059 13.23% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 827407907 68.80% 68.80% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 82886631 6.89% 75.70% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 45822474 3.81% 79.51% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 22740031 1.89% 81.40% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 33832186 2.81% 84.21% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 32824396 2.73% 86.94% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 14991772 1.25% 88.19% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 7935570 0.66% 88.85% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 134102569 11.15% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 2190333922 # Number of instructions fetched each cycle (Total)
-system.cpu.icache.ReadReq_accesses 355041427 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 33183.081998 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 34797.601744 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 355039305 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 70414500 # number of ReadReq miss cycles
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-system.cpu.icache.ReadReq_mshr_hits 746 # number of ReadReq MSHR hits
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-system.cpu.icache.ReadReq_mshr_misses 1376 # number of ReadReq MSHR misses
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+system.cpu.icache.ReadReq_avg_miss_latency 35040.947075 # average ReadReq miss latency
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system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 258210.403636 # Average number of references to valid blocks.
+system.cpu.icache.avg_refs 133766.403400 # Average number of references to valid blocks.
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 355041427 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 33183.081998 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 34797.601744 # average overall mshr miss latency
-system.cpu.icache.demand_hits 355039305 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 70414500 # number of demand (read+write) miss cycles
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-system.cpu.icache.demand_mshr_miss_latency 47881500 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 355039305 # number of overall hits
-system.cpu.icache.overall_miss_latency 70414500 # number of overall miss cycles
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-system.cpu.icache.overall_mshr_hits 746 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 47881500 # number of overall MSHR miss cycles
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-system.cpu.icache.overall_mshr_misses 1376 # number of overall MSHR misses
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system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.replacements 218 # number of replacements
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+system.cpu.icache.replacements 158 # number of replacements
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system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
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-system.cpu.iew.EXEC:branches 129329311 # Number of branches executed
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system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
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-system.cpu.iew.WB:sent 1859595547 # cumulative count of insts sent to commit
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-system.cpu.iew.iewBlockCycles 2291655 # Number of cycles IEW is blocking
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system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
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-system.cpu.iew.iewUnblockCycles 70086 # Number of cycles IEW is unblocking
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system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread.0.cacheBlocked 28836 # Number of times an access to memory failed due to the cache being blocked
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system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
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-system.cpu.iew.predictedNotTakenIncorrect 2781524 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect 89047121 # Number of branches that were predicted taken incorrectly
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-system.cpu.ipc_total 0.641641 # IPC: Total IPC of All Threads
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-system.cpu.iq.iqSquashedInstsIssued 637277 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedNonSpecRemoved 19401032 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined 1242826340 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.l2cache.ReadExReq_accesses 279724 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34530.938042 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31386.377770 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_hits 218618 # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_miss_latency 2110047500 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate 0.218451 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses 61106 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 1917896000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.218451 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses 61106 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses 251060 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 34076.007326 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31002.126905 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 217208 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 1153541000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.134836 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 33852 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 1049484000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.134836 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 33852 # number of ReadReq MSHR misses
-system.cpu.l2cache.Writeback_accesses 467492 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits 467492 # number of Writeback hits
+system.cpu.iq.ISSUE:issued_per_cycle::total 1202543536 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:rate 1.231951 # Inst issue rate
+system.cpu.iq.iqInstsAdded 1603622713 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsIssued 1481925155 # Number of instructions issued
+system.cpu.iq.iqNonSpecInstsAdded 3075375 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqSquashedInstsExamined 200589396 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsIssued 67249 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedNonSpecRemoved 831704 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.iqSquashedOperandsExamined 279090439 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.l2cache.ReadExReq_accesses 268080 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34407.656689 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31319.323632 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_hits 207610 # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_miss_latency 2080631000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate 0.225567 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses 60470 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 1893879500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.225567 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses 60470 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_accesses 214779 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 34036.266738 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31004.958285 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits 181098 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency 1146375500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.156817 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 33681 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 1044278000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.156817 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 33681 # number of ReadReq MSHR misses
+system.cpu.l2cache.Writeback_accesses 428419 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits 428419 # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 5.866131 # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs 5.114556 # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 530784 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 34368.757767 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31249.394469 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 435826 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 3263588500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.178901 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 94958 # number of demand (read+write) misses
+system.cpu.l2cache.demand_accesses 482859 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 34274.797931 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31206.864505 # average overall mshr miss latency
+system.cpu.l2cache.demand_hits 388708 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 3227006500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.194987 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 94151 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 2967380000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.178901 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 94958 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_miss_latency 2938157500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.194987 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 94151 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0 0.061469 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_%::1 0.477467 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_blocks::0 2014.215255 # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1 15645.646003 # Average occupied blocks per context
-system.cpu.l2cache.overall_accesses 530784 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 34368.757767 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31249.394469 # average overall mshr miss latency
+system.cpu.l2cache.occ_%::0 0.060603 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::1 0.478382 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0 1985.832482 # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1 15675.625212 # Average occupied blocks per context
+system.cpu.l2cache.overall_accesses 482859 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 34274.797931 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31206.864505 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 435826 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 3263588500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.178901 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 94958 # number of overall misses
+system.cpu.l2cache.overall_hits 388708 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 3227006500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.194987 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 94151 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 2967380000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.178901 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 94958 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency 2938157500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.194987 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 94151 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements 76745 # number of replacements
-system.cpu.l2cache.sampled_refs 92262 # Sample count of references to valid blocks.
+system.cpu.l2cache.replacements 75917 # number of replacements
+system.cpu.l2cache.sampled_refs 91431 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 17659.861257 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 541221 # Total number of references to valid blocks.
+system.cpu.l2cache.tagsinuse 17661.457694 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 467629 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 59365 # number of writebacks
-system.cpu.memDep0.conflictingLoads 443698156 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 136383139 # Number of conflicting stores.
-system.cpu.memDep0.insertedLoads 731683017 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 299730608 # Number of stores inserted to the mem dependence unit.
-system.cpu.numCycles 2190662936 # number of cpu cycles simulated
-system.cpu.rename.RENAME:BlockCycles 17189054 # Number of cycles rename is blocking
-system.cpu.rename.RENAME:CommittedMaps 1244779268 # Number of HB maps that are committed
-system.cpu.rename.RENAME:FullRegisterEvents 463 # Number of times there has been no free registers
-system.cpu.rename.RENAME:IQFullEvents 34257 # Number of times rename has blocked due to IQ full
-system.cpu.rename.RENAME:IdleCycles 824291881 # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents 24214806 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:ROBFullEvents 8 # Number of times rename has blocked due to ROB full
-system.cpu.rename.RENAME:RenameLookups 4869886562 # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts 3060544953 # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands 2396042530 # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles 704670101 # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles 238675861 # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles 33809858 # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps 1151263262 # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:serializeStallCycles 371697167 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RENAME:serializingInsts 21697179 # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts 175779479 # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts 21533408 # count of temporary serializing insts renamed
-system.cpu.timesIdled 8581 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.l2cache.writebacks 59275 # number of writebacks
+system.cpu.memDep0.conflictingLoads 406523725 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 165664801 # Number of conflicting stores.
+system.cpu.memDep0.insertedLoads 468103706 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 188277007 # Number of stores inserted to the mem dependence unit.
+system.cpu.numCycles 1202909394 # number of cpu cycles simulated
+system.cpu.rename.RENAME:BlockCycles 123850376 # Number of cycles rename is blocking
+system.cpu.rename.RENAME:CommittedMaps 1244770452 # Number of HB maps that are committed
+system.cpu.rename.RENAME:FullRegisterEvents 28358883 # Number of times there has been no free registers
+system.cpu.rename.RENAME:IQFullEvents 134234500 # Number of times rename has blocked due to IQ full
+system.cpu.rename.RENAME:IdleCycles 443697356 # Number of cycles rename is idle
+system.cpu.rename.RENAME:LSQFullEvents 41034725 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RENAME:ROBFullEvents 3 # Number of times rename has blocked due to ROB full
+system.cpu.rename.RENAME:RenameLookups 2926103966 # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts 1732026812 # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands 1445187078 # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles 329587648 # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles 30409425 # Number of cycles rename is squashing
+system.cpu.rename.RENAME:UnblockCycles 217220624 # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps 200416626 # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:serializeStallCycles 57778107 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RENAME:serializingInsts 3036469 # count of serializing insts renamed
+system.cpu.rename.RENAME:skidInsts 385260528 # count of insts added to the skid buffer
+system.cpu.rename.RENAME:tempSerializingInsts 3035800 # count of temporary serializing insts renamed
+system.cpu.timesIdled 11398 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 49 # Number of system calls
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-host_inst_rate 60755 # Simulator instruction rate (inst/s)
-host_mem_usage 205968 # Number of bytes of host memory used
-host_seconds 0.09 # Real time elapsed on the host
-host_tick_rate 164238154 # Simulator tick rate (ticks/s)
+host_inst_rate 25375 # Simulator instruction rate (inst/s)
+host_mem_usage 223596 # Number of bytes of host memory used
+host_seconds 0.20 # Real time elapsed on the host
+host_tick_rate 62666353 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 5169 # Number of instructions simulated
-sim_seconds 0.000014 # Number of seconds simulated
-sim_ticks 14010500 # Number of ticks simulated
+sim_seconds 0.000013 # Number of seconds simulated
+sim_ticks 12784500 # Number of ticks simulated
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.BTBHits 546 # Number of BTB hits
-system.cpu.BPredUnit.BTBLookups 1895 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 538 # Number of BTB hits
+system.cpu.BPredUnit.BTBLookups 1522 # Number of BTB lookups
system.cpu.BPredUnit.RASInCorrect 66 # Number of incorrect RAS predictions.
-system.cpu.BPredUnit.condIncorrect 747 # Number of conditional branches incorrect
-system.cpu.BPredUnit.condPredicted 1584 # Number of conditional branches predicted
-system.cpu.BPredUnit.lookups 2400 # Number of BP lookups
-system.cpu.BPredUnit.usedRAS 400 # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.condIncorrect 378 # Number of conditional branches incorrect
+system.cpu.BPredUnit.condPredicted 1192 # Number of conditional branches predicted
+system.cpu.BPredUnit.lookups 1744 # Number of BP lookups
+system.cpu.BPredUnit.usedRAS 215 # Number of times the RAS was used to get a target.
system.cpu.commit.COM:branches 916 # Number of branches committed
-system.cpu.commit.COM:bw_lim_events 67 # number cycles where commit BW limit reached
+system.cpu.commit.COM:bw_lim_events 76 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle::samples 14458 # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::mean 0.402960 # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::stdev 1.127371 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::samples 12273 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::mean 0.474701 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::stdev 1.213395 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::0 11898 82.29% 82.29% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::1 1218 8.42% 90.72% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::2 521 3.60% 94.32% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::3 292 2.02% 96.34% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::4 296 2.05% 98.39% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::5 65 0.45% 98.84% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::6 62 0.43% 99.27% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::7 39 0.27% 99.54% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::8 67 0.46% 100.00% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::0 9782 79.70% 79.70% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::1 1006 8.20% 87.90% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::2 705 5.74% 93.64% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::3 340 2.77% 96.41% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::4 169 1.38% 97.79% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::5 96 0.78% 98.57% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::6 67 0.55% 99.12% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::7 32 0.26% 99.38% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::8 76 0.62% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::total 14458 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::total 12273 # Number of insts commited each cycle
system.cpu.commit.COM:count 5826 # Number of instructions committed
system.cpu.commit.COM:loads 1164 # Number of loads committed
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
system.cpu.commit.COM:refs 2089 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.branchMispredicts 616 # The number of times a branch was mispredicted
+system.cpu.commit.branchMispredicts 337 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 5826 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 10 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts 5944 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 3481 # The number of squashed insts skipped by commit
system.cpu.committedInsts 5169 # Number of Instructions Simulated
system.cpu.committedInsts_total 5169 # Number of Instructions Simulated
-system.cpu.cpi 5.421165 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 5.421165 # CPI: Total CPI of All Threads
-system.cpu.dcache.ReadReq_accesses 2307 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 34750 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 36021.978022 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 2179 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 4448000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.055483 # miss rate for ReadReq accesses
+system.cpu.cpi 4.946798 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 4.946798 # CPI: Total CPI of All Threads
+system.cpu.dcache.ReadReq_accesses 1824 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 36046.875000 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35938.888889 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 1696 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 4614000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.070175 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 128 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits 37 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency 3278000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.039445 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 91 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_hits 38 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency 3234500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.049342 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 90 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 925 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 27330.827068 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36160 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 659 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 7270000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.287568 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 266 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits 216 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency 1808000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.054054 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 50 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_avg_miss_latency 34184.971098 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36196.078431 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 579 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 11828000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.374054 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 346 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_hits 295 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_miss_latency 1846000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.055135 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 51 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 20.127660 # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs 16.134752 # Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 3232 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 29741.116751 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 36070.921986 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 2838 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 11718000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.121906 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 394 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 253 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 5086000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.043626 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_accesses 2749 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 34687.763713 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 36031.914894 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 2275 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 16442000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.172426 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 474 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 333 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 5080500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.051291 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 141 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0 0.022299 # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0 91.337822 # Average occupied blocks per context
-system.cpu.dcache.overall_accesses 3232 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 29741.116751 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 36070.921986 # average overall mshr miss latency
+system.cpu.dcache.occ_%::0 0.022390 # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0 91.708831 # Average occupied blocks per context
+system.cpu.dcache.overall_accesses 2749 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 34687.763713 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 36031.914894 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 2838 # number of overall hits
-system.cpu.dcache.overall_miss_latency 11718000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.121906 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 394 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 253 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 5086000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.043626 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_hits 2275 # number of overall hits
+system.cpu.dcache.overall_miss_latency 16442000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.172426 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 474 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 333 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 5080500 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.051291 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 141 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.sampled_refs 141 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 91.337822 # Cycle average of tags in use
-system.cpu.dcache.total_refs 2838 # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse 91.708831 # Cycle average of tags in use
+system.cpu.dcache.total_refs 2275 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 0 # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles 514 # Number of cycles decode is blocked
-system.cpu.decode.DECODE:BranchMispred 138 # Number of times decode detected a branch misprediction
-system.cpu.decode.DECODE:BranchResolved 138 # Number of times decode resolved a branch
-system.cpu.decode.DECODE:DecodedInsts 14307 # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles 10045 # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles 3899 # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles 1070 # Number of cycles decode is squashing
-system.cpu.decode.DECODE:SquashedInsts 267 # Number of squashed instructions handled by decode
+system.cpu.decode.DECODE:BlockedCycles 736 # Number of cycles decode is blocked
+system.cpu.decode.DECODE:BranchMispred 42 # Number of times decode detected a branch misprediction
+system.cpu.decode.DECODE:BranchResolved 88 # Number of times decode resolved a branch
+system.cpu.decode.DECODE:DecodedInsts 10461 # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles 8771 # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles 2729 # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles 649 # Number of cycles decode is squashing
+system.cpu.decode.DECODE:SquashedInsts 153 # Number of squashed instructions handled by decode
+system.cpu.decode.DECODE:UnblockCycles 37 # Number of cycles decode is unblocking
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
-system.cpu.fetch.Branches 2400 # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines 2213 # Number of cache lines fetched
-system.cpu.fetch.Cycles 6297 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes 357 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts 15518 # Number of instructions fetch has processed
-system.cpu.fetch.SquashCycles 762 # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate 0.085647 # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles 2213 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches 946 # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate 0.553779 # Number of inst fetches per cycle
-system.cpu.fetch.rateDist::samples 15528 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 0.999356 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.261429 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.Branches 1744 # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines 1555 # Number of cache lines fetched
+system.cpu.fetch.Cycles 4407 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes 219 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Insts 11052 # Number of instructions fetch has processed
+system.cpu.fetch.SquashCycles 393 # Number of cycles fetch has spent squashing
+system.cpu.fetch.branchRate 0.068205 # Number of branch fetches per cycle
+system.cpu.fetch.icacheStallCycles 1555 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches 753 # Number of branches that fetch has predicted taken
+system.cpu.fetch.rate 0.432225 # Number of inst fetches per cycle
+system.cpu.fetch.rateDist::samples 12922 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 0.855286 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.122030 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 11461 73.81% 73.81% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 1813 11.68% 85.48% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 195 1.26% 86.74% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 140 0.90% 87.64% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 320 2.06% 89.70% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 114 0.73% 90.44% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 288 1.85% 92.29% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 259 1.67% 93.96% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 938 6.04% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 10085 78.05% 78.05% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 1182 9.15% 87.19% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 138 1.07% 88.26% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 127 0.98% 89.24% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 278 2.15% 91.39% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 124 0.96% 92.35% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 162 1.25% 93.61% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 99 0.77% 94.37% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 727 5.63% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 15528 # Number of instructions fetched each cycle (Total)
-system.cpu.icache.ReadReq_accesses 2213 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 35692.399050 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 34907.294833 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 1792 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 15026500 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.190239 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 421 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits 92 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency 11484500 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.148667 # mshr miss rate for ReadReq accesses
+system.cpu.fetch.rateDist::total 12922 # Number of instructions fetched each cycle (Total)
+system.cpu.icache.ReadReq_accesses 1555 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 36274.074074 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 35024.316109 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 1150 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 14691000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.260450 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 405 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_hits 76 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_miss_latency 11523000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.211576 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 329 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 5.446809 # Average number of references to valid blocks.
+system.cpu.icache.avg_refs 3.495441 # Average number of references to valid blocks.
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 2213 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 35692.399050 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 34907.294833 # average overall mshr miss latency
-system.cpu.icache.demand_hits 1792 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 15026500 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.190239 # miss rate for demand accesses
-system.cpu.icache.demand_misses 421 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 92 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 11484500 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.148667 # mshr miss rate for demand accesses
+system.cpu.icache.demand_accesses 1555 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 36274.074074 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 35024.316109 # average overall mshr miss latency
+system.cpu.icache.demand_hits 1150 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 14691000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.260450 # miss rate for demand accesses
+system.cpu.icache.demand_misses 405 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 76 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 11523000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.211576 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 329 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0 0.076220 # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0 156.098402 # Average occupied blocks per context
-system.cpu.icache.overall_accesses 2213 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 35692.399050 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 34907.294833 # average overall mshr miss latency
+system.cpu.icache.occ_%::0 0.077565 # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0 158.853467 # Average occupied blocks per context
+system.cpu.icache.overall_accesses 1555 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 36274.074074 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 35024.316109 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 1792 # number of overall hits
-system.cpu.icache.overall_miss_latency 15026500 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.190239 # miss rate for overall accesses
-system.cpu.icache.overall_misses 421 # number of overall misses
-system.cpu.icache.overall_mshr_hits 92 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 11484500 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.148667 # mshr miss rate for overall accesses
+system.cpu.icache.overall_hits 1150 # number of overall hits
+system.cpu.icache.overall_miss_latency 14691000 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.260450 # miss rate for overall accesses
+system.cpu.icache.overall_misses 405 # number of overall misses
+system.cpu.icache.overall_mshr_hits 76 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency 11523000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0.211576 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 329 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.replacements 16 # number of replacements
+system.cpu.icache.replacements 15 # number of replacements
system.cpu.icache.sampled_refs 329 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 156.098402 # Cycle average of tags in use
-system.cpu.icache.total_refs 1792 # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 158.853467 # Cycle average of tags in use
+system.cpu.icache.total_refs 1150 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idleCycles 12494 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.EXEC:branches 1265 # Number of branches executed
-system.cpu.iew.EXEC:nop 1823 # number of nop insts executed
-system.cpu.iew.EXEC:rate 0.295232 # Inst execution rate
-system.cpu.iew.EXEC:refs 3434 # number of memory reference insts executed
+system.cpu.idleCycles 12648 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.iew.EXEC:branches 1183 # Number of branches executed
+system.cpu.iew.EXEC:nop 1244 # number of nop insts executed
+system.cpu.iew.EXEC:rate 0.279625 # Inst execution rate
+system.cpu.iew.EXEC:refs 2950 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 1042 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
-system.cpu.iew.WB:consumers 4130 # num instructions consuming a value
-system.cpu.iew.WB:count 7520 # cumulative count of insts written-back
-system.cpu.iew.WB:fanout 0.704843 # average fanout of values written-back
+system.cpu.iew.WB:consumers 3586 # num instructions consuming a value
+system.cpu.iew.WB:count 6793 # cumulative count of insts written-back
+system.cpu.iew.WB:fanout 0.717513 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers 2911 # num instructions producing a value
-system.cpu.iew.WB:rate 0.268361 # insts written-back per cycle
-system.cpu.iew.WB:sent 7608 # cumulative count of insts sent to commit
-system.cpu.iew.branchMispredicts 678 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewBlockCycles 0 # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts 2792 # Number of dispatched load instructions
-system.cpu.iew.iewDispNonSpecInsts 12 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts 953 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts 1150 # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts 11774 # Number of instructions dispatched to IQ
-system.cpu.iew.iewExecLoadInsts 2392 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 540 # Number of squashed instructions skipped in execute
-system.cpu.iew.iewExecutedInsts 8273 # Number of executed instructions
-system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.WB:producers 2573 # num instructions producing a value
+system.cpu.iew.WB:rate 0.265663 # insts written-back per cycle
+system.cpu.iew.WB:sent 6861 # cumulative count of insts sent to commit
+system.cpu.iew.branchMispredicts 377 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewBlockCycles 165 # Number of cycles IEW is blocking
+system.cpu.iew.iewDispLoadInsts 2139 # Number of dispatched load instructions
+system.cpu.iew.iewDispNonSpecInsts 11 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewDispSquashedInsts 207 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispStoreInsts 1135 # Number of dispatched store instructions
+system.cpu.iew.iewDispatchedInsts 9313 # Number of instructions dispatched to IQ
+system.cpu.iew.iewExecLoadInsts 1908 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 223 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts 7150 # Number of executed instructions
+system.cpu.iew.iewIQFullEvents 6 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles 1070 # Number of cycles IEW is squashing
-system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking
+system.cpu.iew.iewLSQFullEvents 1 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles 649 # Number of cycles IEW is squashing
+system.cpu.iew.iewUnblockCycles 14 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread.0.forwLoads 67 # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread.0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread.0.forwLoads 66 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread.0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.memOrderViolation 19 # Number of memory ordering violations
+system.cpu.iew.lsq.thread.0.memOrderViolation 16 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.0.squashedLoads 1628 # Number of loads squashed
-system.cpu.iew.lsq.thread.0.squashedStores 225 # Number of stores squashed
-system.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect 283 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect 395 # Number of branches that were predicted taken incorrectly
-system.cpu.ipc 0.184462 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.184462 # IPC: Total IPC of All Threads
+system.cpu.iew.lsq.thread.0.squashedLoads 975 # Number of loads squashed
+system.cpu.iew.lsq.thread.0.squashedStores 210 # Number of stores squashed
+system.cpu.iew.memOrderViolationEvents 16 # Number of memory order violations
+system.cpu.iew.predictedNotTakenIncorrect 259 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.predictedTakenIncorrect 118 # Number of branches that were predicted taken incorrectly
+system.cpu.ipc 0.202151 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.202151 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntAlu 5164 58.60% 58.60% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntMult 5 0.06% 58.65% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntDiv 2 0.02% 58.67% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2 0.02% 58.70% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 58.70% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 58.70% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 58.70% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 58.70% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 58.70% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemRead 2584 29.32% 88.02% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemWrite 1056 11.98% 100.00% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntAlu 4328 58.70% 58.70% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntMult 4 0.05% 58.75% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntDiv 2 0.03% 58.78% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2 0.03% 58.81% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 58.81% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 58.81% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 58.81% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 58.81% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 58.81% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::MemRead 1984 26.91% 85.72% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::MemWrite 1053 14.28% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::total 8813 # Type of FU issued
-system.cpu.iq.ISSUE:fu_busy_cnt 160 # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate 0.018155 # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:FU_type_0::total 7373 # Type of FU issued
+system.cpu.iq.ISSUE:fu_busy_cnt 142 # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_rate 0.019259 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntAlu 8 5.00% 5.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 5.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 5.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 5.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 5.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 5.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 5.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 5.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 5.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemRead 100 62.50% 67.50% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemWrite 52 32.50% 100.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntAlu 7 4.93% 4.93% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 4.93% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 4.93% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 4.93% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 4.93% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 4.93% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 4.93% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 4.93% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 4.93% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::MemRead 83 58.45% 63.38% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::MemWrite 52 36.62% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:issued_per_cycle::samples 15528 # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::mean 0.567555 # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.215524 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::samples 12922 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::mean 0.570577 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.213210 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::0 11574 74.54% 74.54% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::1 1747 11.25% 85.79% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::2 792 5.10% 90.89% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::3 724 4.66% 95.55% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::4 342 2.20% 97.75% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::5 211 1.36% 99.11% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::6 94 0.61% 99.72% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::7 29 0.19% 99.90% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::8 15 0.10% 100.00% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::0 9579 74.13% 74.13% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::1 1454 11.25% 85.38% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::2 793 6.14% 91.52% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::3 511 3.95% 95.47% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::4 304 2.35% 97.83% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::5 160 1.24% 99.06% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::6 76 0.59% 99.65% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::7 32 0.25% 99.90% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::8 13 0.10% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::total 15528 # Number of insts issued each cycle
-system.cpu.iq.ISSUE:rate 0.314503 # Inst issue rate
-system.cpu.iq.iqInstsAdded 9939 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued 8813 # Number of instructions issued
-system.cpu.iq.iqNonSpecInstsAdded 12 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined 4094 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedInstsIssued 38 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined 2672 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.ISSUE:issued_per_cycle::total 12922 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:rate 0.288346 # Inst issue rate
+system.cpu.iq.iqInstsAdded 8058 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsIssued 7373 # Number of instructions issued
+system.cpu.iq.iqNonSpecInstsAdded 11 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqSquashedInstsExamined 2456 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsIssued 31 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedNonSpecRemoved 1 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.iqSquashedOperandsExamined 1522 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.l2cache.ReadExReq_accesses 50 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34680 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31360 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency 1734000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_accesses 51 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34696.078431 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31490.196078 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_miss_latency 1769500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses 50 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 1568000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_misses 51 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 1606000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses 50 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses 420 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 34319.711538 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31133.413462 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 4 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 14277000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.990476 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses 51 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_accesses 419 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 34325.721154 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31134.615385 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits 3 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency 14279500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.992840 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 416 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 12951500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.990476 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 12952000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.992840 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 416 # number of ReadReq MSHR misses
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 0.009615 # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs 0.007212 # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 470 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 34358.369099 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31157.725322 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 4 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 16011000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.991489 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 466 # number of demand (read+write) misses
+system.cpu.l2cache.demand_avg_miss_latency 34366.167024 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31173.447537 # average overall mshr miss latency
+system.cpu.l2cache.demand_hits 3 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 16049000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.993617 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 467 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 14519500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.991489 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 466 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_miss_latency 14558000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.993617 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 467 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0 0.006586 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_blocks::0 215.818258 # Average occupied blocks per context
+system.cpu.l2cache.occ_%::0 0.006661 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0 218.261856 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 470 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 34358.369099 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31157.725322 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_miss_latency 34366.167024 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31173.447537 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 4 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 16011000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.991489 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 466 # number of overall misses
+system.cpu.l2cache.overall_hits 3 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 16049000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.993617 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 467 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 14519500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.991489 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 466 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency 14558000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.993617 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 467 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.sampled_refs 416 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 215.818258 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 4 # Total number of references to valid blocks.
+system.cpu.l2cache.tagsinuse 218.261856 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.memDep0.conflictingLoads 5 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 2 # Number of conflicting stores.
-system.cpu.memDep0.insertedLoads 2792 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 1150 # Number of stores inserted to the mem dependence unit.
-system.cpu.numCycles 28022 # number of cpu cycles simulated
-system.cpu.rename.RENAME:BlockCycles 4 # Number of cycles rename is blocking
+system.cpu.memDep0.conflictingStores 1 # Number of conflicting stores.
+system.cpu.memDep0.insertedLoads 2139 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 1135 # Number of stores inserted to the mem dependence unit.
+system.cpu.numCycles 25570 # number of cpu cycles simulated
+system.cpu.rename.RENAME:BlockCycles 238 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 3410 # Number of HB maps that are committed
-system.cpu.rename.RENAME:IdleCycles 10436 # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents 5 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:RenameLookups 15725 # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts 13557 # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands 8322 # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles 3509 # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles 1070 # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles 15 # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps 4912 # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:serializeStallCycles 494 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RENAME:serializingInsts 17 # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts 104 # count of insts added to the skid buffer
+system.cpu.rename.RENAME:IdleCycles 8931 # Number of cycles rename is idle
+system.cpu.rename.RENAME:LSQFullEvents 71 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RENAME:RenameLookups 12088 # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts 10031 # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands 6119 # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles 2609 # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles 649 # Number of cycles rename is squashing
+system.cpu.rename.RENAME:UnblockCycles 81 # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps 2709 # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:serializeStallCycles 414 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RENAME:serializingInsts 16 # count of serializing insts renamed
+system.cpu.rename.RENAME:skidInsts 196 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 11 # count of temporary serializing insts renamed
-system.cpu.timesIdled 247 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.timesIdled 259 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 8 # Number of system calls
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-host_inst_rate 45017 # Simulator instruction rate (inst/s)
-host_mem_usage 207928 # Number of bytes of host memory used
-host_seconds 0.32 # Real time elapsed on the host
-host_tick_rate 85360538 # Simulator tick rate (ticks/s)
+host_inst_rate 29064 # Simulator instruction rate (inst/s)
+host_mem_usage 225548 # Number of bytes of host memory used
+host_seconds 0.50 # Real time elapsed on the host
+host_tick_rate 37472433 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 14449 # Number of instructions simulated
-sim_seconds 0.000027 # Number of seconds simulated
-sim_ticks 27419000 # Number of ticks simulated
+sim_seconds 0.000019 # Number of seconds simulated
+sim_ticks 18639500 # Number of ticks simulated
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.BTBHits 4205 # Number of BTB hits
-system.cpu.BPredUnit.BTBLookups 9180 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 2677 # Number of BTB hits
+system.cpu.BPredUnit.BTBLookups 5066 # Number of BTB lookups
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
-system.cpu.BPredUnit.condIncorrect 2913 # Number of conditional branches incorrect
-system.cpu.BPredUnit.condPredicted 11474 # Number of conditional branches predicted
-system.cpu.BPredUnit.lookups 11474 # Number of BP lookups
+system.cpu.BPredUnit.condIncorrect 725 # Number of conditional branches incorrect
+system.cpu.BPredUnit.condPredicted 5166 # Number of conditional branches predicted
+system.cpu.BPredUnit.lookups 5166 # Number of BP lookups
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.commit.COM:branches 3359 # Number of branches committed
-system.cpu.commit.COM:bw_lim_events 114 # number cycles where commit BW limit reached
+system.cpu.commit.COM:bw_lim_events 84 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle::samples 41984 # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::mean 0.361447 # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::stdev 0.969782 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::samples 27536 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::mean 0.551097 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::stdev 1.189203 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::0 33831 80.58% 80.58% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::1 4806 11.45% 92.03% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::2 1719 4.09% 96.12% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::3 713 1.70% 97.82% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::4 414 0.99% 98.81% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::5 146 0.35% 99.15% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::6 193 0.46% 99.61% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::7 48 0.11% 99.73% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::8 114 0.27% 100.00% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::0 19764 71.78% 71.78% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::1 4506 16.36% 88.14% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::2 1459 5.30% 93.44% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::3 767 2.79% 96.22% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::4 365 1.33% 97.55% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::5 265 0.96% 98.51% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::6 289 1.05% 99.56% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::7 37 0.13% 99.69% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::8 84 0.31% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::total 41984 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::total 27536 # Number of insts commited each cycle
system.cpu.commit.COM:count 15175 # Number of instructions committed
system.cpu.commit.COM:loads 2226 # Number of loads committed
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
system.cpu.commit.COM:refs 3674 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.branchMispredicts 2913 # The number of times a branch was mispredicted
+system.cpu.commit.branchMispredicts 725 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 15175 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts 19909 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 4917 # The number of squashed insts skipped by commit
system.cpu.committedInsts 14449 # Number of Instructions Simulated
system.cpu.committedInsts_total 14449 # Number of Instructions Simulated
-system.cpu.cpi 3.795349 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 3.795349 # CPI: Total CPI of All Threads
-system.cpu.dcache.ReadReq_accesses 3842 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 35221.238938 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35546.153846 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 3729 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 3980000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.029412 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 113 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits 48 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency 2310500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.016918 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 65 # number of ReadReq MSHR misses
+system.cpu.cpi 2.580109 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 2.580109 # CPI: Total CPI of All Threads
+system.cpu.dcache.ReadReq_accesses 2725 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 33508.064516 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35587.301587 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 2601 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 4155000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.045505 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 124 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits 61 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency 2242000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.023119 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 63 # number of ReadReq MSHR misses
system.cpu.dcache.SwapReq_accesses 6 # number of SwapReq accesses(hits+misses)
system.cpu.dcache.SwapReq_hits 6 # number of SwapReq hits
system.cpu.dcache.WriteReq_accesses 1442 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 31011.029412 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35620.481928 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 35792.892157 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35765.060241 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 1034 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 12652500 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency 14603500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.282940 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 408 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits 325 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency 2956500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency 2968500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.057559 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 83 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 32.222973 # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs 24.938356 # Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 5284 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 31924.184261 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 35587.837838 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 4763 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 16632500 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.098600 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 521 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 373 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 5267000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.028009 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 148 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_accesses 4167 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 35260.338346 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 35688.356164 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 3635 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 18758500 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.127670 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 532 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 386 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 5210500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.035037 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 146 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0 0.026492 # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0 108.511216 # Average occupied blocks per context
-system.cpu.dcache.overall_accesses 5284 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 31924.184261 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 35587.837838 # average overall mshr miss latency
+system.cpu.dcache.occ_%::0 0.024989 # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0 102.354840 # Average occupied blocks per context
+system.cpu.dcache.overall_accesses 4167 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 35260.338346 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 35688.356164 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 4763 # number of overall hits
-system.cpu.dcache.overall_miss_latency 16632500 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.098600 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 521 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 373 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 5267000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.028009 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 148 # number of overall MSHR misses
+system.cpu.dcache.overall_hits 3635 # number of overall hits
+system.cpu.dcache.overall_miss_latency 18758500 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.127670 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 532 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 386 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 5210500 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.035037 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 146 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 0 # number of replacements
-system.cpu.dcache.sampled_refs 148 # Sample count of references to valid blocks.
+system.cpu.dcache.sampled_refs 146 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 108.511216 # Cycle average of tags in use
-system.cpu.dcache.total_refs 4769 # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse 102.354840 # Cycle average of tags in use
+system.cpu.dcache.total_refs 3641 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 0 # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles 6598 # Number of cycles decode is blocked
-system.cpu.decode.DECODE:DecodedInsts 51837 # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles 20462 # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles 14791 # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles 4324 # Number of cycles decode is squashing
-system.cpu.decode.DECODE:UnblockCycles 133 # Number of cycles decode is unblocking
-system.cpu.fetch.Branches 11474 # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines 7329 # Number of cache lines fetched
-system.cpu.fetch.Cycles 23792 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes 833 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts 58386 # Number of instructions fetch has processed
-system.cpu.fetch.SquashCycles 3008 # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate 0.209231 # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles 7329 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches 4205 # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate 1.064680 # Number of inst fetches per cycle
-system.cpu.fetch.rateDist::samples 46308 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 1.260819 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.406261 # Number of instructions fetched each cycle (Total)
+system.cpu.decode.DECODE:BlockedCycles 7103 # Number of cycles decode is blocked
+system.cpu.decode.DECODE:DecodedInsts 23378 # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles 13089 # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles 7237 # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles 1142 # Number of cycles decode is squashing
+system.cpu.decode.DECODE:UnblockCycles 107 # Number of cycles decode is unblocking
+system.cpu.fetch.Branches 5166 # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines 4063 # Number of cache lines fetched
+system.cpu.fetch.Cycles 11559 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes 384 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Insts 23733 # Number of instructions fetch has processed
+system.cpu.fetch.SquashCycles 820 # Number of cycles fetch has spent squashing
+system.cpu.fetch.branchRate 0.138573 # Number of branch fetches per cycle
+system.cpu.fetch.icacheStallCycles 4063 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches 2677 # Number of branches that fetch has predicted taken
+system.cpu.fetch.rate 0.636615 # Number of inst fetches per cycle
+system.cpu.fetch.rateDist::samples 28678 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 0.827568 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 1.939691 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 29867 64.50% 64.50% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 7441 16.07% 80.56% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 1110 2.40% 82.96% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 985 2.13% 85.09% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 1044 2.25% 87.34% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 1211 2.62% 89.96% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 663 1.43% 91.39% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 335 0.72% 92.11% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 3652 7.89% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 21209 73.96% 73.96% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 3590 12.52% 86.47% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 580 2.02% 88.50% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 498 1.74% 90.23% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 667 2.33% 92.56% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 529 1.84% 94.40% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 243 0.85% 95.25% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 178 0.62% 95.87% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 1184 4.13% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 46308 # Number of instructions fetched each cycle (Total)
-system.cpu.icache.ReadReq_accesses 7329 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 33501.855288 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 34869.080780 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 6790 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 18057500 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.073543 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 539 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits 180 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency 12518000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.048983 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 359 # number of ReadReq MSHR misses
+system.cpu.fetch.rateDist::total 28678 # Number of instructions fetched each cycle (Total)
+system.cpu.icache.ReadReq_accesses 4063 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 34748.459959 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 34876.056338 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 3576 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 16922500 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.119862 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 487 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_hits 132 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_miss_latency 12381000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.087374 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses 355 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 18.966480 # Average number of references to valid blocks.
+system.cpu.icache.avg_refs 10.101695 # Average number of references to valid blocks.
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 7329 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 33501.855288 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 34869.080780 # average overall mshr miss latency
-system.cpu.icache.demand_hits 6790 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 18057500 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.073543 # miss rate for demand accesses
-system.cpu.icache.demand_misses 539 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 180 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 12518000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.048983 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 359 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_accesses 4063 # number of demand (read+write) accesses
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+system.cpu.icache.demand_hits 3576 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 16922500 # number of demand (read+write) miss cycles
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+system.cpu.icache.demand_mshr_hits 132 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 12381000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.087374 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses 355 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0 0.110645 # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0 226.601923 # Average occupied blocks per context
-system.cpu.icache.overall_accesses 7329 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 33501.855288 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 34869.080780 # average overall mshr miss latency
+system.cpu.icache.occ_%::0 0.100082 # Average percentage of cache occupancy
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system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 6790 # number of overall hits
-system.cpu.icache.overall_miss_latency 18057500 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.073543 # miss rate for overall accesses
-system.cpu.icache.overall_misses 539 # number of overall misses
-system.cpu.icache.overall_mshr_hits 180 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 12518000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.048983 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 359 # number of overall MSHR misses
+system.cpu.icache.overall_hits 3576 # number of overall hits
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system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.replacements 1 # number of replacements
-system.cpu.icache.sampled_refs 358 # Sample count of references to valid blocks.
+system.cpu.icache.sampled_refs 354 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 226.601923 # Cycle average of tags in use
-system.cpu.icache.total_refs 6790 # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 204.967174 # Cycle average of tags in use
+system.cpu.icache.total_refs 3576 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idleCycles 8531 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.EXEC:branches 4839 # Number of branches executed
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system.cpu.iew.EXEC:swp 0 # number of swp insts executed
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-system.cpu.iew.WB:count 23892 # cumulative count of insts written-back
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+system.cpu.iew.WB:count 17034 # cumulative count of insts written-back
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system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers 10801 # num instructions producing a value
-system.cpu.iew.WB:rate 0.435675 # insts written-back per cycle
-system.cpu.iew.WB:sent 24096 # cumulative count of insts sent to commit
-system.cpu.iew.branchMispredicts 3200 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewBlockCycles 24 # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts 4967 # Number of dispatched load instructions
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-system.cpu.iew.iewExecLoadInsts 3960 # Number of load instructions executed
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-system.cpu.iew.iewExecutedInsts 24849 # Number of executed instructions
-system.cpu.iew.iewIQFullEvents 4 # Number of times the IQ has become full, causing a stall
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+system.cpu.iew.WB:sent 17187 # cumulative count of insts sent to commit
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system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles 4324 # Number of cycles IEW is squashing
-system.cpu.iew.iewUnblockCycles 4 # Number of cycles IEW is unblocking
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system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread.0.forwLoads 36 # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread.0.ignoredResponses 6 # Number of memory responses ignored because the instruction is squashed
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system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.memOrderViolation 53 # Number of memory ordering violations
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system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.0.squashedLoads 2741 # Number of loads squashed
-system.cpu.iew.lsq.thread.0.squashedStores 1958 # Number of stores squashed
-system.cpu.iew.memOrderViolationEvents 53 # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect 815 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect 2385 # Number of branches that were predicted taken incorrectly
-system.cpu.ipc 0.263480 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.263480 # IPC: Total IPC of All Threads
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+system.cpu.ipc_total 0.387580 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
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-system.cpu.iq.ISSUE:FU_type_0::MemWrite 3111 10.65% 100.00% # Type of FU issued
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system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
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-system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 24.86% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemRead 20 11.30% 36.16% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemWrite 113 63.84% 100.00% # attempts to use FU when none available
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system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
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-system.cpu.iq.ISSUE:issued_per_cycle::6 336 0.73% 99.45% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::7 214 0.46% 99.91% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::8 43 0.09% 100.00% # Number of insts issued each cycle
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system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
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-system.cpu.iq.ISSUE:rate 0.532559 # Inst issue rate
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-system.cpu.iq.iqInstsIssued 29205 # Number of instructions issued
-system.cpu.iq.iqNonSpecInstsAdded 773 # Number of non-speculative instructions added to the IQ
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-system.cpu.iq.iqSquashedInstsIssued 124 # Number of squashed instructions issued
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system.cpu.l2cache.ReadExReq_accesses 83 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34391.566265 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31313.253012 # average ReadExReq mshr miss latency
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+system.cpu.l2cache.ReadExReq_avg_miss_latency 34536.144578 # average ReadExReq miss latency
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system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 83 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 2599000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 2607000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 83 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses 424 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 34219.047619 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31002.380952 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_accesses 418 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 34231.884058 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31006.038647 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 4 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 14372000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.990566 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 420 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 13021000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.990566 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 420 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_miss_latency 14172000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.990431 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 414 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 12836500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.990431 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 414 # number of ReadReq MSHR misses
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 0.009547 # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs 0.009685 # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 507 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 34247.514911 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31053.677932 # average overall mshr miss latency
+system.cpu.l2cache.demand_accesses 501 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 34282.696177 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31073.440644 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 4 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 17226500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.992110 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 503 # number of demand (read+write) misses
+system.cpu.l2cache.demand_miss_latency 17038500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.992016 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 497 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 15620000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.992110 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 503 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_miss_latency 15443500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.992016 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 497 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0 0.008034 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_blocks::0 263.251984 # Average occupied blocks per context
-system.cpu.l2cache.overall_accesses 507 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 34247.514911 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31053.677932 # average overall mshr miss latency
+system.cpu.l2cache.occ_%::0 0.007304 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0 239.321987 # Average occupied blocks per context
+system.cpu.l2cache.overall_accesses 501 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 34282.696177 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31073.440644 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 4 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 17226500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.992110 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 503 # number of overall misses
+system.cpu.l2cache.overall_miss_latency 17038500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.992016 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 497 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 15620000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.992110 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 503 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency 15443500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.992016 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 497 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.sampled_refs 419 # Sample count of references to valid blocks.
+system.cpu.l2cache.sampled_refs 413 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 263.251984 # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 239.321987 # Cycle average of tags in use
system.cpu.l2cache.total_refs 4 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
-system.cpu.memDep0.conflictingLoads 26 # Number of conflicting loads.
+system.cpu.memDep0.conflictingLoads 13 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores.
-system.cpu.memDep0.insertedLoads 4967 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 3406 # Number of stores inserted to the mem dependence unit.
-system.cpu.numCycles 54839 # number of cpu cycles simulated
-system.cpu.rename.RENAME:BlockCycles 31 # Number of cycles rename is blocking
+system.cpu.memDep0.insertedLoads 2960 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 1800 # Number of stores inserted to the mem dependence unit.
+system.cpu.numCycles 37280 # number of cpu cycles simulated
+system.cpu.rename.RENAME:BlockCycles 254 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 13832 # Number of HB maps that are committed
-system.cpu.rename.RENAME:IQFullEvents 2 # Number of times rename has blocked due to IQ full
-system.cpu.rename.RENAME:IdleCycles 22249 # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents 3 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:RenameLookups 74810 # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts 42608 # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands 35749 # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles 13159 # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles 4324 # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles 313 # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps 21917 # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:serializeStallCycles 6232 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RENAME:serializingInsts 888 # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts 5138 # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts 822 # count of temporary serializing insts renamed
-system.cpu.timesIdled 180 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.rename.RENAME:IdleCycles 13548 # Number of cycles rename is idle
+system.cpu.rename.RENAME:LSQFullEvents 112 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RENAME:RenameLookups 39844 # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts 21594 # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands 19316 # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles 7011 # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles 1142 # Number of cycles rename is squashing
+system.cpu.rename.RENAME:UnblockCycles 422 # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps 5484 # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:serializeStallCycles 6301 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RENAME:serializingInsts 607 # count of serializing insts renamed
+system.cpu.rename.RENAME:skidInsts 2701 # count of insts added to the skid buffer
+system.cpu.rename.RENAME:tempSerializingInsts 587 # count of temporary serializing insts renamed
+system.cpu.timesIdled 184 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 18 # Number of system calls
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-host_inst_rate 29197 # Simulator instruction rate (inst/s)
-host_mem_usage 217900 # Number of bytes of host memory used
-host_seconds 14.87 # Real time elapsed on the host
-host_tick_rate 14552660 # Simulator tick rate (ticks/s)
+host_inst_rate 45662 # Simulator instruction rate (inst/s)
+host_mem_usage 235748 # Number of bytes of host memory used
+host_seconds 25.27 # Real time elapsed on the host
+host_tick_rate 4652764 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 434213 # Number of instructions simulated
-sim_seconds 0.000216 # Number of seconds simulated
-sim_ticks 216428500 # Number of ticks simulated
+sim_insts 1153797 # Number of instructions simulated
+sim_seconds 0.000118 # Number of seconds simulated
+sim_ticks 117567000 # Number of ticks simulated
system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.BPredUnit.BTBHits 44089 # Number of BTB hits
-system.cpu0.BPredUnit.BTBLookups 68668 # Number of BTB lookups
+system.cpu0.BPredUnit.BTBHits 89355 # Number of BTB hits
+system.cpu0.BPredUnit.BTBLookups 91985 # Number of BTB lookups
system.cpu0.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
-system.cpu0.BPredUnit.condIncorrect 42322 # Number of conditional branches incorrect
-system.cpu0.BPredUnit.condPredicted 70848 # Number of conditional branches predicted
-system.cpu0.BPredUnit.lookups 70848 # Number of BP lookups
+system.cpu0.BPredUnit.condIncorrect 1075 # Number of conditional branches incorrect
+system.cpu0.BPredUnit.condPredicted 92438 # Number of conditional branches predicted
+system.cpu0.BPredUnit.lookups 92438 # Number of BP lookups
system.cpu0.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
-system.cpu0.commit.COM:branches 23275 # Number of branches committed
-system.cpu0.commit.COM:bw_lim_events 180 # number cycles where commit BW limit reached
+system.cpu0.commit.COM:branches 89649 # Number of branches committed
+system.cpu0.commit.COM:bw_lim_events 218 # number cycles where commit BW limit reached
system.cpu0.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
-system.cpu0.commit.COM:committed_per_cycle::samples 370366 # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::mean 0.369578 # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::stdev 0.675268 # Number of insts commited each cycle
+system.cpu0.commit.COM:committed_per_cycle::samples 214956 # Number of insts commited each cycle
+system.cpu0.commit.COM:committed_per_cycle::mean 2.489454 # Number of insts commited each cycle
+system.cpu0.commit.COM:committed_per_cycle::stdev 2.121443 # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::0 262900 70.98% 70.98% # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::1 83158 22.45% 93.44% # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::2 22390 6.05% 99.48% # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::3 687 0.19% 99.67% # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::4 335 0.09% 99.76% # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::5 230 0.06% 99.82% # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::6 452 0.12% 99.94% # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::7 34 0.01% 99.95% # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::8 180 0.05% 100.00% # Number of insts commited each cycle
+system.cpu0.commit.COM:committed_per_cycle::0 33666 15.66% 15.66% # Number of insts commited each cycle
+system.cpu0.commit.COM:committed_per_cycle::1 90734 42.21% 57.87% # Number of insts commited each cycle
+system.cpu0.commit.COM:committed_per_cycle::2 2490 1.16% 59.03% # Number of insts commited each cycle
+system.cpu0.commit.COM:committed_per_cycle::3 739 0.34% 59.37% # Number of insts commited each cycle
+system.cpu0.commit.COM:committed_per_cycle::4 734 0.34% 59.72% # Number of insts commited each cycle
+system.cpu0.commit.COM:committed_per_cycle::5 85813 39.92% 99.64% # Number of insts commited each cycle
+system.cpu0.commit.COM:committed_per_cycle::6 487 0.23% 99.86% # Number of insts commited each cycle
+system.cpu0.commit.COM:committed_per_cycle::7 75 0.03% 99.90% # Number of insts commited each cycle
+system.cpu0.commit.COM:committed_per_cycle::8 218 0.10% 100.00% # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::total 370366 # Number of insts commited each cycle
-system.cpu0.commit.COM:count 136879 # Number of instructions committed
-system.cpu0.commit.COM:loads 41762 # Number of loads committed
+system.cpu0.commit.COM:committed_per_cycle::total 214956 # Number of insts commited each cycle
+system.cpu0.commit.COM:count 535123 # Number of instructions committed
+system.cpu0.commit.COM:loads 174510 # Number of loads committed
system.cpu0.commit.COM:membars 84 # Number of memory barriers committed
-system.cpu0.commit.COM:refs 63149 # Number of memory references committed
+system.cpu0.commit.COM:refs 262271 # Number of memory references committed
system.cpu0.commit.COM:swp_count 0 # Number of s/w prefetches committed
-system.cpu0.commit.branchMispredicts 42322 # The number of times a branch was mispredicted
-system.cpu0.commit.commitCommittedInsts 136879 # The number of committed instructions
+system.cpu0.commit.branchMispredicts 1075 # The number of times a branch was mispredicted
+system.cpu0.commit.commitCommittedInsts 535123 # The number of committed instructions
system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.commitSquashedInsts 179861 # The number of squashed insts skipped by commit
-system.cpu0.committedInsts 116789 # Number of Instructions Simulated
-system.cpu0.committedInsts_total 116789 # Number of Instructions Simulated
-system.cpu0.cpi 3.706325 # CPI: Cycles Per Instruction
-system.cpu0.cpi_total 3.706325 # CPI: Total CPI of All Threads
-system.cpu0.dcache.ReadReq_accesses 24665 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_avg_miss_latency 30381.703470 # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 24070.175439 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_hits 24348 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_miss_latency 9631000 # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_rate 0.012852 # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_misses 317 # number of ReadReq misses
-system.cpu0.dcache.ReadReq_mshr_hits 89 # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_miss_latency 5488000 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate 0.009244 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_misses 228 # number of ReadReq MSHR misses
+system.cpu0.commit.commitSquashedInsts 9238 # The number of squashed insts skipped by commit
+system.cpu0.committedInsts 448659 # Number of Instructions Simulated
+system.cpu0.committedInsts_total 448659 # Number of Instructions Simulated
+system.cpu0.cpi 0.524084 # CPI: Cycles Per Instruction
+system.cpu0.cpi_total 0.524084 # CPI: Total CPI of All Threads
+system.cpu0.dcache.ReadReq_accesses 89545 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_avg_miss_latency 27580.808081 # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 27913.043478 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_hits 89050 # number of ReadReq hits
+system.cpu0.dcache.ReadReq_miss_latency 13652500 # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_rate 0.005528 # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_misses 495 # number of ReadReq misses
+system.cpu0.dcache.ReadReq_mshr_hits 311 # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_miss_latency 5136000 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate 0.002055 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_misses 184 # number of ReadReq MSHR misses
system.cpu0.dcache.SwapReq_accesses 42 # number of SwapReq accesses(hits+misses)
-system.cpu0.dcache.SwapReq_avg_miss_latency 15653.846154 # average SwapReq miss latency
-system.cpu0.dcache.SwapReq_avg_mshr_miss_latency 12653.846154 # average SwapReq mshr miss latency
+system.cpu0.dcache.SwapReq_avg_miss_latency 16596.153846 # average SwapReq miss latency
+system.cpu0.dcache.SwapReq_avg_mshr_miss_latency 13596.153846 # average SwapReq mshr miss latency
system.cpu0.dcache.SwapReq_hits 16 # number of SwapReq hits
-system.cpu0.dcache.SwapReq_miss_latency 407000 # number of SwapReq miss cycles
+system.cpu0.dcache.SwapReq_miss_latency 431500 # number of SwapReq miss cycles
system.cpu0.dcache.SwapReq_miss_rate 0.619048 # miss rate for SwapReq accesses
system.cpu0.dcache.SwapReq_misses 26 # number of SwapReq misses
-system.cpu0.dcache.SwapReq_mshr_miss_latency 329000 # number of SwapReq MSHR miss cycles
+system.cpu0.dcache.SwapReq_mshr_miss_latency 353500 # number of SwapReq MSHR miss cycles
system.cpu0.dcache.SwapReq_mshr_miss_rate 0.619048 # mshr miss rate for SwapReq accesses
system.cpu0.dcache.SwapReq_mshr_misses 26 # number of SwapReq MSHR misses
-system.cpu0.dcache.WriteReq_accesses 21345 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_avg_miss_latency 44931.354360 # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 36030.726257 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_hits 20806 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_miss_latency 24218000 # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_rate 0.025252 # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_accesses 87719 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_avg_miss_latency 46114.070501 # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 37094.827586 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_hits 87180 # number of WriteReq hits
+system.cpu0.dcache.WriteReq_miss_latency 24855484 # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_rate 0.006145 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_misses 539 # number of WriteReq misses
-system.cpu0.dcache.WriteReq_mshr_hits 360 # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_miss_latency 6449500 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_rate 0.008386 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_misses 179 # number of WriteReq MSHR misses
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs 25250 # average number of cycles each access was blocked
+system.cpu0.dcache.WriteReq_mshr_hits 365 # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_miss_latency 6454500 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_rate 0.001984 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_misses 174 # number of WriteReq MSHR misses
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs 8595.238095 # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu0.dcache.avg_refs 162.926136 # Average number of references to valid blocks.
-system.cpu0.dcache.blocked::no_mshrs 2 # number of cycles access was blocked
+system.cpu0.dcache.avg_refs 639.867816 # Average number of references to valid blocks.
+system.cpu0.dcache.blocked::no_mshrs 21 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_mshrs 50500 # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_mshrs 180500 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
-system.cpu0.dcache.demand_accesses 46010 # number of demand (read+write) accesses
-system.cpu0.dcache.demand_avg_miss_latency 39543.224299 # average overall miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency 29330.466830 # average overall mshr miss latency
-system.cpu0.dcache.demand_hits 45154 # number of demand (read+write) hits
-system.cpu0.dcache.demand_miss_latency 33849000 # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_rate 0.018605 # miss rate for demand accesses
-system.cpu0.dcache.demand_misses 856 # number of demand (read+write) misses
-system.cpu0.dcache.demand_mshr_hits 449 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_miss_latency 11937500 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_rate 0.008846 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_misses 407 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_accesses 177264 # number of demand (read+write) accesses
+system.cpu0.dcache.demand_avg_miss_latency 37241.764023 # average overall miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency 32375.698324 # average overall mshr miss latency
+system.cpu0.dcache.demand_hits 176230 # number of demand (read+write) hits
+system.cpu0.dcache.demand_miss_latency 38507984 # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_rate 0.005833 # miss rate for demand accesses
+system.cpu0.dcache.demand_misses 1034 # number of demand (read+write) misses
+system.cpu0.dcache.demand_mshr_hits 676 # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_miss_latency 11590500 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_rate 0.002020 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_misses 358 # number of demand (read+write) MSHR misses
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.dcache.occ_%::0 0.285120 # Average percentage of cache occupancy
-system.cpu0.dcache.occ_%::1 -0.014413 # Average percentage of cache occupancy
-system.cpu0.dcache.occ_blocks::0 145.981294 # Average occupied blocks per context
-system.cpu0.dcache.occ_blocks::1 -7.379294 # Average occupied blocks per context
-system.cpu0.dcache.overall_accesses 46010 # number of overall (read+write) accesses
-system.cpu0.dcache.overall_avg_miss_latency 39543.224299 # average overall miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency 29330.466830 # average overall mshr miss latency
+system.cpu0.dcache.occ_%::0 0.276057 # Average percentage of cache occupancy
+system.cpu0.dcache.occ_%::1 -0.002702 # Average percentage of cache occupancy
+system.cpu0.dcache.occ_blocks::0 141.341435 # Average occupied blocks per context
+system.cpu0.dcache.occ_blocks::1 -1.383203 # Average occupied blocks per context
+system.cpu0.dcache.overall_accesses 177264 # number of overall (read+write) accesses
+system.cpu0.dcache.overall_avg_miss_latency 37241.764023 # average overall miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency 32375.698324 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_hits 45154 # number of overall hits
-system.cpu0.dcache.overall_miss_latency 33849000 # number of overall miss cycles
-system.cpu0.dcache.overall_miss_rate 0.018605 # miss rate for overall accesses
-system.cpu0.dcache.overall_misses 856 # number of overall misses
-system.cpu0.dcache.overall_mshr_hits 449 # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_miss_latency 11937500 # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_rate 0.008846 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_misses 407 # number of overall MSHR misses
+system.cpu0.dcache.overall_hits 176230 # number of overall hits
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+system.cpu0.dcache.overall_miss_rate 0.005833 # miss rate for overall accesses
+system.cpu0.dcache.overall_misses 1034 # number of overall misses
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+system.cpu0.dcache.overall_mshr_miss_latency 11590500 # number of overall MSHR miss cycles
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+system.cpu0.dcache.overall_mshr_misses 358 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu0.dcache.replacements 10 # number of replacements
-system.cpu0.dcache.sampled_refs 176 # Sample count of references to valid blocks.
+system.cpu0.dcache.replacements 9 # number of replacements
+system.cpu0.dcache.sampled_refs 174 # Sample count of references to valid blocks.
system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu0.dcache.tagsinuse 138.602000 # Cycle average of tags in use
-system.cpu0.dcache.total_refs 28675 # Total number of references to valid blocks.
+system.cpu0.dcache.tagsinuse 139.958233 # Cycle average of tags in use
+system.cpu0.dcache.total_refs 111337 # Total number of references to valid blocks.
system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu0.dcache.writebacks 6 # number of writebacks
-system.cpu0.decode.DECODE:BlockedCycles 52020 # Number of cycles decode is blocked
-system.cpu0.decode.DECODE:DecodedInsts 451824 # Number of instructions handled by decode
-system.cpu0.decode.DECODE:IdleCycles 163842 # Number of cycles decode is idle
-system.cpu0.decode.DECODE:RunCycles 154430 # Number of cycles decode is running
-system.cpu0.decode.DECODE:SquashCycles 44292 # Number of cycles decode is squashing
-system.cpu0.decode.DECODE:UnblockCycles 74 # Number of cycles decode is unblocking
-system.cpu0.fetch.Branches 70848 # Number of branches that fetch encountered
-system.cpu0.fetch.CacheLines 87024 # Number of cache lines fetched
-system.cpu0.fetch.Cycles 242789 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.IcacheSquashes 20667 # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.Insts 457866 # Number of instructions fetch has processed
-system.cpu0.fetch.SquashCycles 42477 # Number of cycles fetch has spent squashing
-system.cpu0.fetch.branchRate 0.163675 # Number of branch fetches per cycle
-system.cpu0.fetch.icacheStallCycles 87024 # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.predictedBranches 44089 # Number of branches that fetch has predicted taken
-system.cpu0.fetch.rate 1.057774 # Number of inst fetches per cycle
-system.cpu0.fetch.rateDist::samples 414658 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean 1.104202 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev 2.128179 # Number of instructions fetched each cycle (Total)
+system.cpu0.decode.DECODE:BlockedCycles 13605 # Number of cycles decode is blocked
+system.cpu0.decode.DECODE:DecodedInsts 549348 # Number of instructions handled by decode
+system.cpu0.decode.DECODE:IdleCycles 19922 # Number of cycles decode is idle
+system.cpu0.decode.DECODE:RunCycles 181227 # Number of cycles decode is running
+system.cpu0.decode.DECODE:SquashCycles 2012 # Number of cycles decode is squashing
+system.cpu0.decode.DECODE:UnblockCycles 202 # Number of cycles decode is unblocking
+system.cpu0.fetch.Branches 92438 # Number of branches that fetch encountered
+system.cpu0.fetch.CacheLines 5211 # Number of cache lines fetched
+system.cpu0.fetch.Cycles 186910 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.IcacheSquashes 478 # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.Insts 550298 # Number of instructions fetch has processed
+system.cpu0.fetch.SquashCycles 1215 # Number of cycles fetch has spent squashing
+system.cpu0.fetch.branchRate 0.393127 # Number of branch fetches per cycle
+system.cpu0.fetch.icacheStallCycles 5211 # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.predictedBranches 89355 # Number of branches that fetch has predicted taken
+system.cpu0.fetch.rate 2.340349 # Number of inst fetches per cycle
+system.cpu0.fetch.rateDist::samples 216968 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean 2.536310 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev 2.185886 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0 258930 62.44% 62.44% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1 86799 20.93% 83.38% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2 1004 0.24% 83.62% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3 21052 5.08% 88.70% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::4 1074 0.26% 88.95% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::5 20905 5.04% 94.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::6 680 0.16% 94.16% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::7 710 0.17% 94.33% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::8 23504 5.67% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0 35310 16.27% 16.27% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1 90281 41.61% 57.88% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2 487 0.22% 58.11% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3 792 0.37% 58.47% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::4 586 0.27% 58.74% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::5 86643 39.93% 98.68% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::6 826 0.38% 99.06% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::7 192 0.09% 99.15% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::8 1851 0.85% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total 414658 # Number of instructions fetched each cycle (Total)
-system.cpu0.icache.ReadReq_accesses 87024 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_avg_miss_latency 37020.114943 # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency 35068.011958 # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_hits 86154 # number of ReadReq hits
-system.cpu0.icache.ReadReq_miss_latency 32207500 # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_rate 0.009997 # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_misses 870 # number of ReadReq misses
-system.cpu0.icache.ReadReq_mshr_hits 201 # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_miss_latency 23460500 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate 0.007688 # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_misses 669 # number of ReadReq MSHR misses
-system.cpu0.icache.avg_blocked_cycles::no_mshrs 10250 # average number of cycles each access was blocked
+system.cpu0.fetch.rateDist::total 216968 # Number of instructions fetched each cycle (Total)
+system.cpu0.icache.ReadReq_accesses 5211 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_avg_miss_latency 39190.412783 # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency 37010.673235 # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_hits 4460 # number of ReadReq hits
+system.cpu0.icache.ReadReq_miss_latency 29432000 # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_rate 0.144118 # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_misses 751 # number of ReadReq misses
+system.cpu0.icache.ReadReq_mshr_hits 142 # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_miss_latency 22539500 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate 0.116868 # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_misses 609 # number of ReadReq MSHR misses
+system.cpu0.icache.avg_blocked_cycles::no_mshrs 11000 # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu0.icache.avg_refs 128.973054 # Average number of references to valid blocks.
+system.cpu0.icache.avg_refs 7.335526 # Average number of references to valid blocks.
system.cpu0.icache.blocked::no_mshrs 2 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu0.icache.blocked_cycles::no_mshrs 20500 # number of cycles access was blocked
+system.cpu0.icache.blocked_cycles::no_mshrs 22000 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.cache_copies 0 # number of cache copies performed
-system.cpu0.icache.demand_accesses 87024 # number of demand (read+write) accesses
-system.cpu0.icache.demand_avg_miss_latency 37020.114943 # average overall miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency 35068.011958 # average overall mshr miss latency
-system.cpu0.icache.demand_hits 86154 # number of demand (read+write) hits
-system.cpu0.icache.demand_miss_latency 32207500 # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_rate 0.009997 # miss rate for demand accesses
-system.cpu0.icache.demand_misses 870 # number of demand (read+write) misses
-system.cpu0.icache.demand_mshr_hits 201 # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_miss_latency 23460500 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_rate 0.007688 # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_misses 669 # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_accesses 5211 # number of demand (read+write) accesses
+system.cpu0.icache.demand_avg_miss_latency 39190.412783 # average overall miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency 37010.673235 # average overall mshr miss latency
+system.cpu0.icache.demand_hits 4460 # number of demand (read+write) hits
+system.cpu0.icache.demand_miss_latency 29432000 # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_rate 0.144118 # miss rate for demand accesses
+system.cpu0.icache.demand_misses 751 # number of demand (read+write) misses
+system.cpu0.icache.demand_mshr_hits 142 # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_miss_latency 22539500 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_rate 0.116868 # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_misses 609 # number of demand (read+write) MSHR misses
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.icache.occ_%::0 0.526858 # Average percentage of cache occupancy
-system.cpu0.icache.occ_blocks::0 269.751047 # Average occupied blocks per context
-system.cpu0.icache.overall_accesses 87024 # number of overall (read+write) accesses
-system.cpu0.icache.overall_avg_miss_latency 37020.114943 # average overall miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency 35068.011958 # average overall mshr miss latency
+system.cpu0.icache.occ_%::0 0.503078 # Average percentage of cache occupancy
+system.cpu0.icache.occ_blocks::0 257.575944 # Average occupied blocks per context
+system.cpu0.icache.overall_accesses 5211 # number of overall (read+write) accesses
+system.cpu0.icache.overall_avg_miss_latency 39190.412783 # average overall miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency 37010.673235 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu0.icache.overall_hits 86154 # number of overall hits
-system.cpu0.icache.overall_miss_latency 32207500 # number of overall miss cycles
-system.cpu0.icache.overall_miss_rate 0.009997 # miss rate for overall accesses
-system.cpu0.icache.overall_misses 870 # number of overall misses
-system.cpu0.icache.overall_mshr_hits 201 # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_miss_latency 23460500 # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_rate 0.007688 # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_misses 669 # number of overall MSHR misses
+system.cpu0.icache.overall_hits 4460 # number of overall hits
+system.cpu0.icache.overall_miss_latency 29432000 # number of overall miss cycles
+system.cpu0.icache.overall_miss_rate 0.144118 # miss rate for overall accesses
+system.cpu0.icache.overall_misses 751 # number of overall misses
+system.cpu0.icache.overall_mshr_hits 142 # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_miss_latency 22539500 # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_rate 0.116868 # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_misses 609 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu0.icache.replacements 363 # number of replacements
-system.cpu0.icache.sampled_refs 668 # Sample count of references to valid blocks.
+system.cpu0.icache.replacements 307 # number of replacements
+system.cpu0.icache.sampled_refs 608 # Sample count of references to valid blocks.
system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu0.icache.tagsinuse 269.751047 # Cycle average of tags in use
-system.cpu0.icache.total_refs 86154 # Total number of references to valid blocks.
+system.cpu0.icache.tagsinuse 257.575944 # Cycle average of tags in use
+system.cpu0.icache.total_refs 4460 # Total number of references to valid blocks.
system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu0.icache.writebacks 0 # number of writebacks
-system.cpu0.idleCycles 18200 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.iew.EXEC:branches 44503 # Number of branches executed
-system.cpu0.iew.EXEC:nop 59775 # number of nop insts executed
-system.cpu0.iew.EXEC:rate 0.436141 # Inst execution rate
-system.cpu0.iew.EXEC:refs 66647 # number of memory reference insts executed
-system.cpu0.iew.EXEC:stores 22312 # Number of stores executed
+system.cpu0.idleCycles 18167 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu0.iew.EXEC:branches 90443 # Number of branches executed
+system.cpu0.iew.EXEC:nop 86837 # number of nop insts executed
+system.cpu0.iew.EXEC:rate 1.932175 # Inst execution rate
+system.cpu0.iew.EXEC:refs 263768 # number of memory reference insts executed
+system.cpu0.iew.EXEC:stores 88187 # Number of stores executed
system.cpu0.iew.EXEC:swp 0 # number of swp insts executed
-system.cpu0.iew.WB:consumers 95172 # num instructions consuming a value
-system.cpu0.iew.WB:count 187212 # cumulative count of insts written-back
-system.cpu0.iew.WB:fanout 0.972912 # average fanout of values written-back
+system.cpu0.iew.WB:consumers 271302 # num instructions consuming a value
+system.cpu0.iew.WB:count 453750 # cumulative count of insts written-back
+system.cpu0.iew.WB:fanout 0.992930 # average fanout of values written-back
system.cpu0.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu0.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu0.iew.WB:producers 92594 # num instructions producing a value
-system.cpu0.iew.WB:rate 0.432502 # insts written-back per cycle
-system.cpu0.iew.WB:sent 187507 # cumulative count of insts sent to commit
-system.cpu0.iew.branchMispredicts 42628 # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewBlockCycles 24 # Number of cycles IEW is blocking
-system.cpu0.iew.iewDispLoadInsts 45739 # Number of dispatched load instructions
-system.cpu0.iew.iewDispNonSpecInsts 20652 # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewDispSquashedInsts 2935 # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispStoreInsts 43021 # Number of dispatched store instructions
-system.cpu0.iew.iewDispatchedInsts 316777 # Number of instructions dispatched to IQ
-system.cpu0.iew.iewExecLoadInsts 44335 # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts 42979 # Number of squashed instructions skipped in execute
-system.cpu0.iew.iewExecutedInsts 188787 # Number of executed instructions
-system.cpu0.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.WB:producers 269384 # num instructions producing a value
+system.cpu0.iew.WB:rate 1.929742 # insts written-back per cycle
+system.cpu0.iew.WB:sent 453963 # cumulative count of insts sent to commit
+system.cpu0.iew.branchMispredicts 1256 # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewBlockCycles 901 # Number of cycles IEW is blocking
+system.cpu0.iew.iewDispLoadInsts 176074 # Number of dispatched load instructions
+system.cpu0.iew.iewDispNonSpecInsts 725 # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewDispSquashedInsts 482 # Number of squashed instructions skipped by dispatch
+system.cpu0.iew.iewDispStoreInsts 88705 # Number of dispatched store instructions
+system.cpu0.iew.iewDispatchedInsts 544396 # Number of instructions dispatched to IQ
+system.cpu0.iew.iewExecLoadInsts 175581 # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts 893 # Number of squashed instructions skipped in execute
+system.cpu0.iew.iewExecutedInsts 454322 # Number of executed instructions
+system.cpu0.iew.iewIQFullEvents 25 # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu0.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.iewSquashCycles 44292 # Number of cycles IEW is squashing
-system.cpu0.iew.iewUnblockCycles 4 # Number of cycles IEW is unblocking
+system.cpu0.iew.iewSquashCycles 2012 # Number of cycles IEW is squashing
+system.cpu0.iew.iewUnblockCycles 26 # Number of cycles IEW is unblocking
system.cpu0.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu0.iew.lsq.thread.0.cacheBlocked 15 # Number of times an access to memory failed due to the cache being blocked
-system.cpu0.iew.lsq.thread.0.forwLoads 19578 # Number of loads that had data forwarded from stores
-system.cpu0.iew.lsq.thread.0.ignoredResponses 11 # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread.0.cacheBlocked 18 # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread.0.forwLoads 85985 # Number of loads that had data forwarded from stores
+system.cpu0.iew.lsq.thread.0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu0.iew.lsq.thread.0.memOrderViolation 197 # Number of memory ordering violations
+system.cpu0.iew.lsq.thread.0.memOrderViolation 74 # Number of memory ordering violations
system.cpu0.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread.0.squashedLoads 3977 # Number of loads squashed
-system.cpu0.iew.lsq.thread.0.squashedStores 21634 # Number of stores squashed
-system.cpu0.iew.memOrderViolationEvents 197 # Number of memory order violations
-system.cpu0.iew.predictedNotTakenIncorrect 962 # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.predictedTakenIncorrect 41666 # Number of branches that were predicted taken incorrectly
-system.cpu0.ipc 0.269809 # IPC: Instructions Per Cycle
-system.cpu0.ipc_total 0.269809 # IPC: Total IPC of All Threads
+system.cpu0.iew.lsq.thread.0.squashedLoads 1564 # Number of loads squashed
+system.cpu0.iew.lsq.thread.0.squashedStores 944 # Number of stores squashed
+system.cpu0.iew.memOrderViolationEvents 74 # Number of memory order violations
+system.cpu0.iew.predictedNotTakenIncorrect 831 # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.predictedTakenIncorrect 425 # Number of branches that were predicted taken incorrectly
+system.cpu0.ipc 1.908091 # IPC: Instructions Per Cycle
+system.cpu0.ipc_total 1.908091 # IPC: Total IPC of All Threads
system.cpu0.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0::IntAlu 164239 70.86% 70.86% # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0::IntMult 0 0.00% 70.86% # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 70.86% # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 70.86% # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 70.86% # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 70.86% # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 70.86% # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 70.86% # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 70.86% # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0::MemRead 44972 19.40% 90.27% # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0::MemWrite 22555 9.73% 100.00% # Type of FU issued
+system.cpu0.iq.ISSUE:FU_type_0::IntAlu 191075 41.97% 41.97% # Type of FU issued
+system.cpu0.iq.ISSUE:FU_type_0::IntMult 0 0.00% 41.97% # Type of FU issued
+system.cpu0.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 41.97% # Type of FU issued
+system.cpu0.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 41.97% # Type of FU issued
+system.cpu0.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 41.97% # Type of FU issued
+system.cpu0.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 41.97% # Type of FU issued
+system.cpu0.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 41.97% # Type of FU issued
+system.cpu0.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 41.97% # Type of FU issued
+system.cpu0.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 41.97% # Type of FU issued
+system.cpu0.iq.ISSUE:FU_type_0::MemRead 175866 38.63% 80.61% # Type of FU issued
+system.cpu0.iq.ISSUE:FU_type_0::MemWrite 88274 19.39% 100.00% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0::total 231766 # Type of FU issued
-system.cpu0.iq.ISSUE:fu_busy_cnt 133 # FU busy when requested
-system.cpu0.iq.ISSUE:fu_busy_rate 0.000574 # FU busy rate (busy events/executed inst)
+system.cpu0.iq.ISSUE:FU_type_0::total 455215 # Type of FU issued
+system.cpu0.iq.ISSUE:fu_busy_cnt 184 # FU busy when requested
+system.cpu0.iq.ISSUE:fu_busy_rate 0.000404 # FU busy rate (busy events/executed inst)
system.cpu0.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::IntAlu 38 28.57% 28.57% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::IntMult 0 0.00% 28.57% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::IntDiv 0 0.00% 28.57% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::FloatAdd 0 0.00% 28.57% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::FloatCmp 0 0.00% 28.57% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::FloatCvt 0 0.00% 28.57% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::FloatMult 0 0.00% 28.57% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::FloatDiv 0 0.00% 28.57% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 28.57% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::MemRead 27 20.30% 48.87% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::MemWrite 68 51.13% 100.00% # attempts to use FU when none available
+system.cpu0.iq.ISSUE:fu_full::IntAlu 29 15.76% 15.76% # attempts to use FU when none available
+system.cpu0.iq.ISSUE:fu_full::IntMult 0 0.00% 15.76% # attempts to use FU when none available
+system.cpu0.iq.ISSUE:fu_full::IntDiv 0 0.00% 15.76% # attempts to use FU when none available
+system.cpu0.iq.ISSUE:fu_full::FloatAdd 0 0.00% 15.76% # attempts to use FU when none available
+system.cpu0.iq.ISSUE:fu_full::FloatCmp 0 0.00% 15.76% # attempts to use FU when none available
+system.cpu0.iq.ISSUE:fu_full::FloatCvt 0 0.00% 15.76% # attempts to use FU when none available
+system.cpu0.iq.ISSUE:fu_full::FloatMult 0 0.00% 15.76% # attempts to use FU when none available
+system.cpu0.iq.ISSUE:fu_full::FloatDiv 0 0.00% 15.76% # attempts to use FU when none available
+system.cpu0.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 15.76% # attempts to use FU when none available
+system.cpu0.iq.ISSUE:fu_full::MemRead 75 40.76% 56.52% # attempts to use FU when none available
+system.cpu0.iq.ISSUE:fu_full::MemWrite 80 43.48% 100.00% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:issued_per_cycle::samples 414658 # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:issued_per_cycle::mean 0.558933 # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:issued_per_cycle::stdev 0.948995 # Number of insts issued each cycle
+system.cpu0.iq.ISSUE:issued_per_cycle::samples 216968 # Number of insts issued each cycle
+system.cpu0.iq.ISSUE:issued_per_cycle::mean 2.098074 # Number of insts issued each cycle
+system.cpu0.iq.ISSUE:issued_per_cycle::stdev 1.056367 # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:issued_per_cycle::0 280664 67.69% 67.69% # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:issued_per_cycle::1 66211 15.97% 83.65% # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:issued_per_cycle::2 42876 10.34% 93.99% # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:issued_per_cycle::3 21783 5.25% 99.25% # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:issued_per_cycle::4 1770 0.43% 99.67% # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:issued_per_cycle::5 925 0.22% 99.90% # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:issued_per_cycle::6 280 0.07% 99.96% # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:issued_per_cycle::7 123 0.03% 99.99% # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:issued_per_cycle::8 26 0.01% 100.00% # Number of insts issued each cycle
+system.cpu0.iq.ISSUE:issued_per_cycle::0 33344 15.37% 15.37% # Number of insts issued each cycle
+system.cpu0.iq.ISSUE:issued_per_cycle::1 5639 2.60% 17.97% # Number of insts issued each cycle
+system.cpu0.iq.ISSUE:issued_per_cycle::2 88266 40.68% 58.65% # Number of insts issued each cycle
+system.cpu0.iq.ISSUE:issued_per_cycle::3 87233 40.21% 98.85% # Number of insts issued each cycle
+system.cpu0.iq.ISSUE:issued_per_cycle::4 1475 0.68% 99.53% # Number of insts issued each cycle
+system.cpu0.iq.ISSUE:issued_per_cycle::5 727 0.34% 99.87% # Number of insts issued each cycle
+system.cpu0.iq.ISSUE:issued_per_cycle::6 185 0.09% 99.95% # Number of insts issued each cycle
+system.cpu0.iq.ISSUE:issued_per_cycle::7 92 0.04% 100.00% # Number of insts issued each cycle
+system.cpu0.iq.ISSUE:issued_per_cycle::8 7 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:issued_per_cycle::total 414658 # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:rate 0.535432 # Inst issue rate
-system.cpu0.iq.iqInstsAdded 236227 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqInstsIssued 231766 # Number of instructions issued
-system.cpu0.iq.iqNonSpecInstsAdded 20775 # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqSquashedInstsExamined 98222 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedInstsIssued 56 # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedNonSpecRemoved 20216 # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.iqSquashedOperandsExamined 15756 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.memDep0.conflictingLoads 19721 # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores 107 # Number of conflicting stores.
-system.cpu0.memDep0.insertedLoads 45739 # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores 43021 # Number of stores inserted to the mem dependence unit.
-system.cpu0.numCycles 432858 # number of cpu cycles simulated
-system.cpu0.rename.RENAME:BlockCycles 32 # Number of cycles rename is blocking
-system.cpu0.rename.RENAME:CommittedMaps 96356 # Number of HB maps that are committed
-system.cpu0.rename.RENAME:IdleCycles 185237 # Number of cycles rename is idle
-system.cpu0.rename.RENAME:LSQFullEvents 5 # Number of times rename has blocked due to LSQ full
-system.cpu0.rename.RENAME:RenameLookups 505980 # Number of register rename lookups that rename has made
-system.cpu0.rename.RENAME:RenamedInsts 324358 # Number of instructions processed by rename
-system.cpu0.rename.RENAME:RenamedOperands 242034 # Number of destination operands rename has renamed
-system.cpu0.rename.RENAME:RunCycles 133140 # Number of cycles rename is running
-system.cpu0.rename.RENAME:SquashCycles 44292 # Number of cycles rename is squashing
-system.cpu0.rename.RENAME:UnblockCycles 353 # Number of cycles rename is unblocking
-system.cpu0.rename.RENAME:UndoneMaps 145678 # Number of HB maps that are undone due to squashing
-system.cpu0.rename.RENAME:serializeStallCycles 51604 # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RENAME:serializingInsts 20781 # count of serializing insts renamed
-system.cpu0.rename.RENAME:skidInsts 83212 # count of insts added to the skid buffer
-system.cpu0.rename.RENAME:tempSerializingInsts 20768 # count of temporary serializing insts renamed
-system.cpu0.timesIdled 340 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu0.iq.ISSUE:issued_per_cycle::total 216968 # Number of insts issued each cycle
+system.cpu0.iq.ISSUE:rate 1.935973 # Inst issue rate
+system.cpu0.iq.iqInstsAdded 456737 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqInstsIssued 455215 # Number of instructions issued
+system.cpu0.iq.iqNonSpecInstsAdded 822 # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqSquashedInstsExamined 7989 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedInstsIssued 42 # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedNonSpecRemoved 263 # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.iqSquashedOperandsExamined 6440 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.memDep0.conflictingLoads 86348 # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores 86194 # Number of conflicting stores.
+system.cpu0.memDep0.insertedLoads 176074 # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores 88705 # Number of stores inserted to the mem dependence unit.
+system.cpu0.numCycles 235135 # number of cpu cycles simulated
+system.cpu0.rename.RENAME:BlockCycles 1287 # Number of cycles rename is blocking
+system.cpu0.rename.RENAME:CommittedMaps 361852 # Number of HB maps that are committed
+system.cpu0.rename.RENAME:IQFullEvents 6 # Number of times rename has blocked due to IQ full
+system.cpu0.rename.RENAME:IdleCycles 20610 # Number of cycles rename is idle
+system.cpu0.rename.RENAME:LSQFullEvents 290 # Number of times rename has blocked due to LSQ full
+system.cpu0.rename.RENAME:RenameLookups 1089678 # Number of register rename lookups that rename has made
+system.cpu0.rename.RENAME:RenamedInsts 546179 # Number of instructions processed by rename
+system.cpu0.rename.RENAME:RenamedOperands 371907 # Number of destination operands rename has renamed
+system.cpu0.rename.RENAME:RunCycles 180783 # Number of cycles rename is running
+system.cpu0.rename.RENAME:SquashCycles 2012 # Number of cycles rename is squashing
+system.cpu0.rename.RENAME:UnblockCycles 696 # Number of cycles rename is unblocking
+system.cpu0.rename.RENAME:UndoneMaps 10055 # Number of HB maps that are undone due to squashing
+system.cpu0.rename.RENAME:serializeStallCycles 11580 # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RENAME:serializingInsts 797 # count of serializing insts renamed
+system.cpu0.rename.RENAME:skidInsts 4205 # count of insts added to the skid buffer
+system.cpu0.rename.RENAME:tempSerializingInsts 813 # count of temporary serializing insts renamed
+system.cpu0.timesIdled 339 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.workload.PROG:num_syscalls 89 # Number of system calls
system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.BPredUnit.BTBHits 53713 # Number of BTB hits
-system.cpu1.BPredUnit.BTBLookups 65870 # Number of BTB lookups
+system.cpu1.BPredUnit.BTBHits 54161 # Number of BTB hits
+system.cpu1.BPredUnit.BTBLookups 56395 # Number of BTB lookups
system.cpu1.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
-system.cpu1.BPredUnit.condIncorrect 29792 # Number of conditional branches incorrect
-system.cpu1.BPredUnit.condPredicted 83669 # Number of conditional branches predicted
-system.cpu1.BPredUnit.lookups 83669 # Number of BP lookups
+system.cpu1.BPredUnit.condIncorrect 1087 # Number of conditional branches incorrect
+system.cpu1.BPredUnit.condPredicted 56507 # Number of conditional branches predicted
+system.cpu1.BPredUnit.lookups 56507 # Number of BP lookups
system.cpu1.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
-system.cpu1.commit.COM:branches 25470 # Number of branches committed
-system.cpu1.commit.COM:bw_lim_events 577 # number cycles where commit BW limit reached
+system.cpu1.commit.COM:branches 53696 # Number of branches committed
+system.cpu1.commit.COM:bw_lim_events 485 # number cycles where commit BW limit reached
system.cpu1.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
-system.cpu1.commit.COM:committed_per_cycle::samples 350132 # Number of insts commited each cycle
-system.cpu1.commit.COM:committed_per_cycle::mean 0.363609 # Number of insts commited each cycle
-system.cpu1.commit.COM:committed_per_cycle::stdev 0.831936 # Number of insts commited each cycle
+system.cpu1.commit.COM:committed_per_cycle::samples 188473 # Number of insts commited each cycle
+system.cpu1.commit.COM:committed_per_cycle::mean 1.608787 # Number of insts commited each cycle
+system.cpu1.commit.COM:committed_per_cycle::stdev 1.965463 # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu1.commit.COM:committed_per_cycle::0 266836 76.21% 76.21% # Number of insts commited each cycle
-system.cpu1.commit.COM:committed_per_cycle::1 54270 15.50% 91.71% # Number of insts commited each cycle
-system.cpu1.commit.COM:committed_per_cycle::2 24066 6.87% 98.58% # Number of insts commited each cycle
-system.cpu1.commit.COM:committed_per_cycle::3 1288 0.37% 98.95% # Number of insts commited each cycle
-system.cpu1.commit.COM:committed_per_cycle::4 810 0.23% 99.18% # Number of insts commited each cycle
-system.cpu1.commit.COM:committed_per_cycle::5 561 0.16% 99.34% # Number of insts commited each cycle
-system.cpu1.commit.COM:committed_per_cycle::6 1684 0.48% 99.82% # Number of insts commited each cycle
-system.cpu1.commit.COM:committed_per_cycle::7 40 0.01% 99.84% # Number of insts commited each cycle
-system.cpu1.commit.COM:committed_per_cycle::8 577 0.16% 100.00% # Number of insts commited each cycle
+system.cpu1.commit.COM:committed_per_cycle::0 76772 40.73% 40.73% # Number of insts commited each cycle
+system.cpu1.commit.COM:committed_per_cycle::1 54519 28.93% 69.66% # Number of insts commited each cycle
+system.cpu1.commit.COM:committed_per_cycle::2 7469 3.96% 73.62% # Number of insts commited each cycle
+system.cpu1.commit.COM:committed_per_cycle::3 7244 3.84% 77.47% # Number of insts commited each cycle
+system.cpu1.commit.COM:committed_per_cycle::4 2460 1.31% 78.77% # Number of insts commited each cycle
+system.cpu1.commit.COM:committed_per_cycle::5 38973 20.68% 99.45% # Number of insts commited each cycle
+system.cpu1.commit.COM:committed_per_cycle::6 418 0.22% 99.67% # Number of insts commited each cycle
+system.cpu1.commit.COM:committed_per_cycle::7 133 0.07% 99.74% # Number of insts commited each cycle
+system.cpu1.commit.COM:committed_per_cycle::8 485 0.26% 100.00% # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu1.commit.COM:committed_per_cycle::total 350132 # Number of insts commited each cycle
-system.cpu1.commit.COM:count 127311 # Number of instructions committed
-system.cpu1.commit.COM:loads 29520 # Number of loads committed
-system.cpu1.commit.COM:membars 8970 # Number of memory barriers committed
-system.cpu1.commit.COM:refs 40059 # Number of memory references committed
+system.cpu1.commit.COM:committed_per_cycle::total 188473 # Number of insts commited each cycle
+system.cpu1.commit.COM:count 303213 # Number of instructions committed
+system.cpu1.commit.COM:loads 89248 # Number of loads committed
+system.cpu1.commit.COM:membars 5702 # Number of memory barriers committed
+system.cpu1.commit.COM:refs 131277 # Number of memory references committed
system.cpu1.commit.COM:swp_count 0 # Number of s/w prefetches committed
-system.cpu1.commit.branchMispredicts 29792 # The number of times a branch was mispredicted
-system.cpu1.commit.commitCommittedInsts 127311 # The number of committed instructions
-system.cpu1.commit.commitNonSpecStalls 9688 # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.commitSquashedInsts 134332 # The number of squashed insts skipped by commit
-system.cpu1.committedInsts 102085 # Number of Instructions Simulated
-system.cpu1.committedInsts_total 102085 # Number of Instructions Simulated
-system.cpu1.cpi 3.872714 # CPI: Cycles Per Instruction
-system.cpu1.cpi_total 3.872714 # CPI: Total CPI of All Threads
-system.cpu1.dcache.ReadReq_accesses 28866 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_avg_miss_latency 18882.352941 # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 16694.285714 # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_hits 28662 # number of ReadReq hits
-system.cpu1.dcache.ReadReq_miss_latency 3852000 # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_rate 0.007067 # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_misses 204 # number of ReadReq misses
-system.cpu1.dcache.ReadReq_mshr_hits 29 # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_miss_latency 2921500 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate 0.006062 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_misses 175 # number of ReadReq MSHR misses
-system.cpu1.dcache.SwapReq_accesses 72 # number of SwapReq accesses(hits+misses)
-system.cpu1.dcache.SwapReq_avg_miss_latency 22155.172414 # average SwapReq miss latency
-system.cpu1.dcache.SwapReq_avg_mshr_miss_latency 24152.173913 # average SwapReq mshr miss latency
-system.cpu1.dcache.SwapReq_hits 14 # number of SwapReq hits
-system.cpu1.dcache.SwapReq_miss_latency 1285000 # number of SwapReq miss cycles
-system.cpu1.dcache.SwapReq_miss_rate 0.805556 # miss rate for SwapReq accesses
-system.cpu1.dcache.SwapReq_misses 58 # number of SwapReq misses
-system.cpu1.dcache.SwapReq_mshr_hits 12 # number of SwapReq MSHR hits
-system.cpu1.dcache.SwapReq_mshr_miss_latency 1111000 # number of SwapReq MSHR miss cycles
-system.cpu1.dcache.SwapReq_mshr_miss_rate 0.638889 # mshr miss rate for SwapReq accesses
-system.cpu1.dcache.SwapReq_mshr_misses 46 # number of SwapReq MSHR misses
-system.cpu1.dcache.WriteReq_accesses 10467 # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_avg_miss_latency 23593.023256 # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 15414.414414 # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_hits 10338 # number of WriteReq hits
-system.cpu1.dcache.WriteReq_miss_latency 3043500 # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_rate 0.012324 # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_misses 129 # number of WriteReq misses
+system.cpu1.commit.branchMispredicts 1087 # The number of times a branch was mispredicted
+system.cpu1.commit.commitCommittedInsts 303213 # The number of committed instructions
+system.cpu1.commit.commitNonSpecStalls 6416 # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.commitSquashedInsts 8260 # The number of squashed insts skipped by commit
+system.cpu1.committedInsts 253025 # Number of Instructions Simulated
+system.cpu1.committedInsts_total 253025 # Number of Instructions Simulated
+system.cpu1.cpi 0.791222 # CPI: Cycles Per Instruction
+system.cpu1.cpi_total 0.791222 # CPI: Total CPI of All Threads
+system.cpu1.dcache.ReadReq_accesses 51822 # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_avg_miss_latency 22047.619048 # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 13770.186335 # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_hits 51360 # number of ReadReq hits
+system.cpu1.dcache.ReadReq_miss_latency 10186000 # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_rate 0.008915 # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_misses 462 # number of ReadReq misses
+system.cpu1.dcache.ReadReq_mshr_hits 301 # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_miss_latency 2217000 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate 0.003107 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_misses 161 # number of ReadReq MSHR misses
+system.cpu1.dcache.SwapReq_accesses 68 # number of SwapReq accesses(hits+misses)
+system.cpu1.dcache.SwapReq_avg_miss_latency 25285.714286 # average SwapReq miss latency
+system.cpu1.dcache.SwapReq_avg_mshr_miss_latency 22285.714286 # average SwapReq mshr miss latency
+system.cpu1.dcache.SwapReq_hits 12 # number of SwapReq hits
+system.cpu1.dcache.SwapReq_miss_latency 1416000 # number of SwapReq miss cycles
+system.cpu1.dcache.SwapReq_miss_rate 0.823529 # miss rate for SwapReq accesses
+system.cpu1.dcache.SwapReq_misses 56 # number of SwapReq misses
+system.cpu1.dcache.SwapReq_mshr_miss_latency 1248000 # number of SwapReq MSHR miss cycles
+system.cpu1.dcache.SwapReq_mshr_miss_rate 0.823529 # mshr miss rate for SwapReq accesses
+system.cpu1.dcache.SwapReq_mshr_misses 56 # number of SwapReq MSHR misses
+system.cpu1.dcache.WriteReq_accesses 41961 # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_avg_miss_latency 22916 # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 14406.542056 # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_hits 41836 # number of WriteReq hits
+system.cpu1.dcache.WriteReq_miss_latency 2864500 # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_rate 0.002979 # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_misses 125 # number of WriteReq misses
system.cpu1.dcache.WriteReq_mshr_hits 18 # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_miss_latency 1711000 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_rate 0.010605 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_misses 111 # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_miss_latency 1541500 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_rate 0.002550 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_misses 107 # number of WriteReq MSHR misses
system.cpu1.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu1.dcache.avg_refs 701.333333 # Average number of references to valid blocks.
+system.cpu1.dcache.avg_refs 1593.333333 # Average number of references to valid blocks.
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
-system.cpu1.dcache.demand_accesses 39333 # number of demand (read+write) accesses
-system.cpu1.dcache.demand_avg_miss_latency 20707.207207 # average overall miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency 16197.552448 # average overall mshr miss latency
-system.cpu1.dcache.demand_hits 39000 # number of demand (read+write) hits
-system.cpu1.dcache.demand_miss_latency 6895500 # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_rate 0.008466 # miss rate for demand accesses
-system.cpu1.dcache.demand_misses 333 # number of demand (read+write) misses
-system.cpu1.dcache.demand_mshr_hits 47 # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_miss_latency 4632500 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_rate 0.007271 # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_misses 286 # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_accesses 93783 # number of demand (read+write) accesses
+system.cpu1.dcache.demand_avg_miss_latency 22232.538330 # average overall miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency 14024.253731 # average overall mshr miss latency
+system.cpu1.dcache.demand_hits 93196 # number of demand (read+write) hits
+system.cpu1.dcache.demand_miss_latency 13050500 # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_rate 0.006259 # miss rate for demand accesses
+system.cpu1.dcache.demand_misses 587 # number of demand (read+write) misses
+system.cpu1.dcache.demand_mshr_hits 319 # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_miss_latency 3758500 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_rate 0.002858 # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_misses 268 # number of demand (read+write) MSHR misses
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.dcache.occ_%::0 0.053273 # Average percentage of cache occupancy
-system.cpu1.dcache.occ_%::1 -0.013192 # Average percentage of cache occupancy
-system.cpu1.dcache.occ_blocks::0 27.275525 # Average occupied blocks per context
-system.cpu1.dcache.occ_blocks::1 -6.754298 # Average occupied blocks per context
-system.cpu1.dcache.overall_accesses 39333 # number of overall (read+write) accesses
-system.cpu1.dcache.overall_avg_miss_latency 20707.207207 # average overall miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency 16197.552448 # average overall mshr miss latency
+system.cpu1.dcache.occ_%::0 0.047229 # Average percentage of cache occupancy
+system.cpu1.dcache.occ_%::1 -0.018864 # Average percentage of cache occupancy
+system.cpu1.dcache.occ_blocks::0 24.181003 # Average occupied blocks per context
+system.cpu1.dcache.occ_blocks::1 -9.658476 # Average occupied blocks per context
+system.cpu1.dcache.overall_accesses 93783 # number of overall (read+write) accesses
+system.cpu1.dcache.overall_avg_miss_latency 22232.538330 # average overall miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency 14024.253731 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu1.dcache.overall_hits 39000 # number of overall hits
-system.cpu1.dcache.overall_miss_latency 6895500 # number of overall miss cycles
-system.cpu1.dcache.overall_miss_rate 0.008466 # miss rate for overall accesses
-system.cpu1.dcache.overall_misses 333 # number of overall misses
-system.cpu1.dcache.overall_mshr_hits 47 # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_miss_latency 4632500 # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_rate 0.007271 # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_misses 286 # number of overall MSHR misses
+system.cpu1.dcache.overall_hits 93196 # number of overall hits
+system.cpu1.dcache.overall_miss_latency 13050500 # number of overall miss cycles
+system.cpu1.dcache.overall_miss_rate 0.006259 # miss rate for overall accesses
+system.cpu1.dcache.overall_misses 587 # number of overall misses
+system.cpu1.dcache.overall_mshr_hits 319 # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_miss_latency 3758500 # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_rate 0.002858 # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_misses 268 # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu1.dcache.replacements 2 # number of replacements
system.cpu1.dcache.sampled_refs 30 # Sample count of references to valid blocks.
system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu1.dcache.tagsinuse 20.521228 # Cycle average of tags in use
-system.cpu1.dcache.total_refs 21040 # Total number of references to valid blocks.
+system.cpu1.dcache.tagsinuse 14.522528 # Cycle average of tags in use
+system.cpu1.dcache.total_refs 47800 # Total number of references to valid blocks.
system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu1.dcache.writebacks 1 # number of writebacks
-system.cpu1.decode.DECODE:BlockedCycles 30059 # Number of cycles decode is blocked
-system.cpu1.decode.DECODE:DecodedInsts 353088 # Number of instructions handled by decode
-system.cpu1.decode.DECODE:IdleCycles 174967 # Number of cycles decode is idle
-system.cpu1.decode.DECODE:RunCycles 144955 # Number of cycles decode is running
-system.cpu1.decode.DECODE:SquashCycles 33628 # Number of cycles decode is squashing
-system.cpu1.decode.DECODE:UnblockCycles 151 # Number of cycles decode is unblocking
-system.cpu1.fetch.Branches 83669 # Number of branches that fetch encountered
-system.cpu1.fetch.CacheLines 82467 # Number of cache lines fetched
-system.cpu1.fetch.Cycles 239936 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.IcacheSquashes 9132 # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.Insts 410532 # Number of instructions fetch has processed
-system.cpu1.fetch.SquashCycles 29946 # Number of cycles fetch has spent squashing
-system.cpu1.fetch.branchRate 0.211635 # Number of branch fetches per cycle
-system.cpu1.fetch.icacheStallCycles 82467 # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.predictedBranches 53713 # Number of branches that fetch has predicted taken
-system.cpu1.fetch.rate 1.038412 # Number of inst fetches per cycle
-system.cpu1.fetch.rateDist::samples 392437 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean 1.046109 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev 1.946317 # Number of instructions fetched each cycle (Total)
+system.cpu1.decode.DECODE:BlockedCycles 20776 # Number of cycles decode is blocked
+system.cpu1.decode.DECODE:DecodedInsts 315521 # Number of instructions handled by decode
+system.cpu1.decode.DECODE:IdleCycles 53573 # Number of cycles decode is idle
+system.cpu1.decode.DECODE:RunCycles 108896 # Number of cycles decode is running
+system.cpu1.decode.DECODE:SquashCycles 1776 # Number of cycles decode is squashing
+system.cpu1.decode.DECODE:UnblockCycles 5228 # Number of cycles decode is unblocking
+system.cpu1.fetch.Branches 56507 # Number of branches that fetch encountered
+system.cpu1.fetch.CacheLines 20124 # Number of cache lines fetched
+system.cpu1.fetch.Cycles 134645 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.IcacheSquashes 219 # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.Insts 316659 # Number of instructions fetch has processed
+system.cpu1.fetch.SquashCycles 1165 # Number of cycles fetch has spent squashing
+system.cpu1.fetch.branchRate 0.282254 # Number of branch fetches per cycle
+system.cpu1.fetch.icacheStallCycles 20124 # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.predictedBranches 54161 # Number of branches that fetch has predicted taken
+system.cpu1.fetch.rate 1.581721 # Number of inst fetches per cycle
+system.cpu1.fetch.rateDist::samples 196865 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean 1.608508 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev 2.050886 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0 234991 59.88% 59.88% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1 84908 21.64% 81.52% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2 20175 5.14% 86.66% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3 13313 3.39% 90.05% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::4 2697 0.69% 90.74% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::5 17066 4.35% 95.09% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::6 1329 0.34% 95.42% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::7 2421 0.62% 96.04% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::8 15537 3.96% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0 82366 41.84% 41.84% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1 58899 29.92% 71.76% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2 6765 3.44% 75.19% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3 2772 1.41% 76.60% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::4 1900 0.97% 77.57% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::5 39920 20.28% 97.84% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::6 2488 1.26% 99.11% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::7 254 0.13% 99.24% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::8 1501 0.76% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total 392437 # Number of instructions fetched each cycle (Total)
-system.cpu1.icache.ReadReq_accesses 82467 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_avg_miss_latency 14489.768076 # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11935.534591 # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_hits 81734 # number of ReadReq hits
-system.cpu1.icache.ReadReq_miss_latency 10621000 # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_rate 0.008888 # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_misses 733 # number of ReadReq misses
-system.cpu1.icache.ReadReq_mshr_hits 97 # number of ReadReq MSHR hits
-system.cpu1.icache.ReadReq_mshr_miss_latency 7591000 # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate 0.007712 # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_misses 636 # number of ReadReq MSHR misses
+system.cpu1.fetch.rateDist::total 196865 # Number of instructions fetched each cycle (Total)
+system.cpu1.icache.ReadReq_accesses 20124 # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_avg_miss_latency 15227.650728 # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency 12284.753363 # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_hits 19643 # number of ReadReq hits
+system.cpu1.icache.ReadReq_miss_latency 7324500 # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_rate 0.023902 # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_misses 481 # number of ReadReq misses
+system.cpu1.icache.ReadReq_mshr_hits 35 # number of ReadReq MSHR hits
+system.cpu1.icache.ReadReq_mshr_miss_latency 5479000 # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate 0.022163 # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_misses 446 # number of ReadReq MSHR misses
system.cpu1.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu1.icache.avg_refs 128.512579 # Average number of references to valid blocks.
+system.cpu1.icache.avg_refs 44.042601 # Average number of references to valid blocks.
system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.cache_copies 0 # number of cache copies performed
-system.cpu1.icache.demand_accesses 82467 # number of demand (read+write) accesses
-system.cpu1.icache.demand_avg_miss_latency 14489.768076 # average overall miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency 11935.534591 # average overall mshr miss latency
-system.cpu1.icache.demand_hits 81734 # number of demand (read+write) hits
-system.cpu1.icache.demand_miss_latency 10621000 # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_rate 0.008888 # miss rate for demand accesses
-system.cpu1.icache.demand_misses 733 # number of demand (read+write) misses
-system.cpu1.icache.demand_mshr_hits 97 # number of demand (read+write) MSHR hits
-system.cpu1.icache.demand_mshr_miss_latency 7591000 # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_rate 0.007712 # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_misses 636 # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_accesses 20124 # number of demand (read+write) accesses
+system.cpu1.icache.demand_avg_miss_latency 15227.650728 # average overall miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency 12284.753363 # average overall mshr miss latency
+system.cpu1.icache.demand_hits 19643 # number of demand (read+write) hits
+system.cpu1.icache.demand_miss_latency 7324500 # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_rate 0.023902 # miss rate for demand accesses
+system.cpu1.icache.demand_misses 481 # number of demand (read+write) misses
+system.cpu1.icache.demand_mshr_hits 35 # number of demand (read+write) MSHR hits
+system.cpu1.icache.demand_mshr_miss_latency 5479000 # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_rate 0.022163 # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_misses 446 # number of demand (read+write) MSHR misses
system.cpu1.icache.fast_writes 0 # number of fast writes performed
system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.icache.occ_%::0 0.183206 # Average percentage of cache occupancy
-system.cpu1.icache.occ_blocks::0 93.801528 # Average occupied blocks per context
-system.cpu1.icache.overall_accesses 82467 # number of overall (read+write) accesses
-system.cpu1.icache.overall_avg_miss_latency 14489.768076 # average overall miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency 11935.534591 # average overall mshr miss latency
+system.cpu1.icache.occ_%::0 0.166563 # Average percentage of cache occupancy
+system.cpu1.icache.occ_blocks::0 85.280274 # Average occupied blocks per context
+system.cpu1.icache.overall_accesses 20124 # number of overall (read+write) accesses
+system.cpu1.icache.overall_avg_miss_latency 15227.650728 # average overall miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency 12284.753363 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu1.icache.overall_hits 81734 # number of overall hits
-system.cpu1.icache.overall_miss_latency 10621000 # number of overall miss cycles
-system.cpu1.icache.overall_miss_rate 0.008888 # miss rate for overall accesses
-system.cpu1.icache.overall_misses 733 # number of overall misses
-system.cpu1.icache.overall_mshr_hits 97 # number of overall MSHR hits
-system.cpu1.icache.overall_mshr_miss_latency 7591000 # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_rate 0.007712 # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_misses 636 # number of overall MSHR misses
+system.cpu1.icache.overall_hits 19643 # number of overall hits
+system.cpu1.icache.overall_miss_latency 7324500 # number of overall miss cycles
+system.cpu1.icache.overall_miss_rate 0.023902 # miss rate for overall accesses
+system.cpu1.icache.overall_misses 481 # number of overall misses
+system.cpu1.icache.overall_mshr_hits 35 # number of overall MSHR hits
+system.cpu1.icache.overall_mshr_miss_latency 5479000 # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_rate 0.022163 # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_misses 446 # number of overall MSHR misses
system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu1.icache.replacements 524 # number of replacements
-system.cpu1.icache.sampled_refs 636 # Sample count of references to valid blocks.
+system.cpu1.icache.replacements 334 # number of replacements
+system.cpu1.icache.sampled_refs 446 # Sample count of references to valid blocks.
system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu1.icache.tagsinuse 93.801528 # Cycle average of tags in use
-system.cpu1.icache.total_refs 81734 # Total number of references to valid blocks.
+system.cpu1.icache.tagsinuse 85.280274 # Cycle average of tags in use
+system.cpu1.icache.total_refs 19643 # Total number of references to valid blocks.
system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu1.icache.writebacks 0 # number of writebacks
-system.cpu1.idleCycles 2909 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.iew.EXEC:branches 36547 # Number of branches executed
-system.cpu1.iew.EXEC:nop 47873 # number of nop insts executed
-system.cpu1.iew.EXEC:rate 0.410671 # Inst execution rate
-system.cpu1.iew.EXEC:refs 47615 # number of memory reference insts executed
-system.cpu1.iew.EXEC:stores 12164 # Number of stores executed
+system.cpu1.idleCycles 3334 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu1.iew.EXEC:branches 54256 # Number of branches executed
+system.cpu1.iew.EXEC:nop 45272 # number of nop insts executed
+system.cpu1.iew.EXEC:rate 1.311145 # Inst execution rate
+system.cpu1.iew.EXEC:refs 132363 # number of memory reference insts executed
+system.cpu1.iew.EXEC:stores 42366 # Number of stores executed
system.cpu1.iew.EXEC:swp 0 # number of swp insts executed
-system.cpu1.iew.WB:consumers 78764 # num instructions consuming a value
-system.cpu1.iew.WB:count 158732 # cumulative count of insts written-back
-system.cpu1.iew.WB:fanout 0.929676 # average fanout of values written-back
+system.cpu1.iew.WB:consumers 152450 # num instructions consuming a value
+system.cpu1.iew.WB:count 262125 # cumulative count of insts written-back
+system.cpu1.iew.WB:fanout 0.975992 # average fanout of values written-back
system.cpu1.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu1.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu1.iew.WB:producers 73225 # num instructions producing a value
-system.cpu1.iew.WB:rate 0.401501 # insts written-back per cycle
-system.cpu1.iew.WB:sent 158983 # cumulative count of insts sent to commit
-system.cpu1.iew.branchMispredicts 30400 # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewBlockCycles 0 # Number of cycles IEW is blocking
-system.cpu1.iew.iewDispLoadInsts 39543 # Number of dispatched load instructions
-system.cpu1.iew.iewDispNonSpecInsts 8501 # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewDispSquashedInsts 3508 # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispStoreInsts 20654 # Number of dispatched store instructions
-system.cpu1.iew.iewDispatchedInsts 261662 # Number of instructions dispatched to IQ
-system.cpu1.iew.iewExecLoadInsts 35451 # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts 33572 # Number of squashed instructions skipped in execute
-system.cpu1.iew.iewExecutedInsts 162357 # Number of executed instructions
-system.cpu1.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.WB:producers 148790 # num instructions producing a value
+system.cpu1.iew.WB:rate 1.309322 # insts written-back per cycle
+system.cpu1.iew.WB:sent 262257 # cumulative count of insts sent to commit
+system.cpu1.iew.branchMispredicts 1189 # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewBlockCycles 1724 # Number of cycles IEW is blocking
+system.cpu1.iew.iewDispLoadInsts 90756 # Number of dispatched load instructions
+system.cpu1.iew.iewDispNonSpecInsts 936 # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewDispSquashedInsts 579 # Number of squashed instructions skipped by dispatch
+system.cpu1.iew.iewDispStoreInsts 42793 # Number of dispatched store instructions
+system.cpu1.iew.iewDispatchedInsts 311506 # Number of instructions dispatched to IQ
+system.cpu1.iew.iewExecLoadInsts 89997 # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts 940 # Number of squashed instructions skipped in execute
+system.cpu1.iew.iewExecutedInsts 262490 # Number of executed instructions
+system.cpu1.iew.iewIQFullEvents 48 # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.iewSquashCycles 33628 # Number of cycles IEW is squashing
-system.cpu1.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking
+system.cpu1.iew.iewSquashCycles 1776 # Number of cycles IEW is squashing
+system.cpu1.iew.iewUnblockCycles 55 # Number of cycles IEW is unblocking
system.cpu1.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
-system.cpu1.iew.lsq.thread.0.forwLoads 6568 # Number of loads that had data forwarded from stores
-system.cpu1.iew.lsq.thread.0.ignoredResponses 11 # Number of memory responses ignored because the instruction is squashed
+system.cpu1.iew.lsq.thread.0.forwLoads 38160 # Number of loads that had data forwarded from stores
+system.cpu1.iew.lsq.thread.0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu1.iew.lsq.thread.0.memOrderViolation 694 # Number of memory ordering violations
+system.cpu1.iew.lsq.thread.0.memOrderViolation 37 # Number of memory ordering violations
system.cpu1.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled
-system.cpu1.iew.lsq.thread.0.squashedLoads 10023 # Number of loads squashed
-system.cpu1.iew.lsq.thread.0.squashedStores 10115 # Number of stores squashed
-system.cpu1.iew.memOrderViolationEvents 694 # Number of memory order violations
-system.cpu1.iew.predictedNotTakenIncorrect 1033 # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.predictedTakenIncorrect 29367 # Number of branches that were predicted taken incorrectly
-system.cpu1.ipc 0.258217 # IPC: Instructions Per Cycle
-system.cpu1.ipc_total 0.258217 # IPC: Total IPC of All Threads
+system.cpu1.iew.lsq.thread.0.squashedLoads 1508 # Number of loads squashed
+system.cpu1.iew.lsq.thread.0.squashedStores 764 # Number of stores squashed
+system.cpu1.iew.memOrderViolationEvents 37 # Number of memory order violations
+system.cpu1.iew.predictedNotTakenIncorrect 207 # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.predictedTakenIncorrect 982 # Number of branches that were predicted taken incorrectly
+system.cpu1.ipc 1.263867 # IPC: Instructions Per Cycle
+system.cpu1.ipc_total 1.263867 # IPC: Total IPC of All Threads
system.cpu1.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::IntAlu 137441 70.15% 70.15% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::IntMult 0 0.00% 70.15% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 70.15% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 70.15% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 70.15% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 70.15% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 70.15% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 70.15% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 70.15% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::MemRead 45623 23.29% 93.43% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::MemWrite 12865 6.57% 100.00% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::IntAlu 125150 47.51% 47.51% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::IntMult 0 0.00% 47.51% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 47.51% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 47.51% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 47.51% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 47.51% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 47.51% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 47.51% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 47.51% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::MemRead 95884 36.40% 83.91% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::MemWrite 42396 16.09% 100.00% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::total 195929 # Type of FU issued
-system.cpu1.iq.ISSUE:fu_busy_cnt 186 # FU busy when requested
-system.cpu1.iq.ISSUE:fu_busy_rate 0.000949 # FU busy rate (busy events/executed inst)
+system.cpu1.iq.ISSUE:FU_type_0::total 263430 # Type of FU issued
+system.cpu1.iq.ISSUE:fu_busy_cnt 193 # FU busy when requested
+system.cpu1.iq.ISSUE:fu_busy_rate 0.000733 # FU busy rate (busy events/executed inst)
system.cpu1.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::IntAlu 24 12.90% 12.90% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::IntMult 0 0.00% 12.90% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::IntDiv 0 0.00% 12.90% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::FloatAdd 0 0.00% 12.90% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::FloatCmp 0 0.00% 12.90% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::FloatCvt 0 0.00% 12.90% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::FloatMult 0 0.00% 12.90% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::FloatDiv 0 0.00% 12.90% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 12.90% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::MemRead 17 9.14% 22.04% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::MemWrite 145 77.96% 100.00% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::IntAlu 10 5.18% 5.18% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::IntMult 0 0.00% 5.18% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::IntDiv 0 0.00% 5.18% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::FloatAdd 0 0.00% 5.18% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::FloatCmp 0 0.00% 5.18% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::FloatCvt 0 0.00% 5.18% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::FloatMult 0 0.00% 5.18% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::FloatDiv 0 0.00% 5.18% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 5.18% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::MemRead 55 28.50% 33.68% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::MemWrite 128 66.32% 100.00% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:issued_per_cycle::samples 392437 # Number of insts issued each cycle
-system.cpu1.iq.ISSUE:issued_per_cycle::mean 0.499262 # Number of insts issued each cycle
-system.cpu1.iq.ISSUE:issued_per_cycle::stdev 0.956261 # Number of insts issued each cycle
+system.cpu1.iq.ISSUE:issued_per_cycle::samples 196865 # Number of insts issued each cycle
+system.cpu1.iq.ISSUE:issued_per_cycle::mean 1.338125 # Number of insts issued each cycle
+system.cpu1.iq.ISSUE:issued_per_cycle::stdev 1.287182 # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu1.iq.ISSUE:issued_per_cycle::0 275791 70.28% 70.28% # Number of insts issued each cycle
-system.cpu1.iq.ISSUE:issued_per_cycle::1 71375 18.19% 88.46% # Number of insts issued each cycle
-system.cpu1.iq.ISSUE:issued_per_cycle::2 23368 5.95% 94.42% # Number of insts issued each cycle
-system.cpu1.iq.ISSUE:issued_per_cycle::3 13587 3.46% 97.88% # Number of insts issued each cycle
-system.cpu1.iq.ISSUE:issued_per_cycle::4 5437 1.39% 99.27% # Number of insts issued each cycle
-system.cpu1.iq.ISSUE:issued_per_cycle::5 2194 0.56% 99.83% # Number of insts issued each cycle
-system.cpu1.iq.ISSUE:issued_per_cycle::6 490 0.12% 99.95% # Number of insts issued each cycle
-system.cpu1.iq.ISSUE:issued_per_cycle::7 161 0.04% 99.99% # Number of insts issued each cycle
-system.cpu1.iq.ISSUE:issued_per_cycle::8 34 0.01% 100.00% # Number of insts issued each cycle
+system.cpu1.iq.ISSUE:issued_per_cycle::0 78477 39.86% 39.86% # Number of insts issued each cycle
+system.cpu1.iq.ISSUE:issued_per_cycle::1 26779 13.60% 53.47% # Number of insts issued each cycle
+system.cpu1.iq.ISSUE:issued_per_cycle::2 44704 22.71% 76.17% # Number of insts issued each cycle
+system.cpu1.iq.ISSUE:issued_per_cycle::3 42537 21.61% 97.78% # Number of insts issued each cycle
+system.cpu1.iq.ISSUE:issued_per_cycle::4 2555 1.30% 99.08% # Number of insts issued each cycle
+system.cpu1.iq.ISSUE:issued_per_cycle::5 1568 0.80% 99.88% # Number of insts issued each cycle
+system.cpu1.iq.ISSUE:issued_per_cycle::6 153 0.08% 99.95% # Number of insts issued each cycle
+system.cpu1.iq.ISSUE:issued_per_cycle::7 82 0.04% 99.99% # Number of insts issued each cycle
+system.cpu1.iq.ISSUE:issued_per_cycle::8 10 0.01% 100.00% # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu1.iq.ISSUE:issued_per_cycle::total 392437 # Number of insts issued each cycle
-system.cpu1.iq.ISSUE:rate 0.495589 # Inst issue rate
-system.cpu1.iq.iqInstsAdded 196258 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqInstsIssued 195929 # Number of instructions issued
-system.cpu1.iq.iqNonSpecInstsAdded 17531 # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqSquashedInstsExamined 74909 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedInstsIssued 4 # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedNonSpecRemoved 7843 # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.iqSquashedOperandsExamined 33478 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.memDep0.conflictingLoads 6760 # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores 87 # Number of conflicting stores.
-system.cpu1.memDep0.insertedLoads 39543 # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores 20654 # Number of stores inserted to the mem dependence unit.
-system.cpu1.numCycles 395346 # number of cpu cycles simulated
-system.cpu1.rename.RENAME:CommittedMaps 85194 # Number of HB maps that are committed
-system.cpu1.rename.RENAME:IdleCycles 186916 # Number of cycles rename is idle
-system.cpu1.rename.RENAME:LSQFullEvents 1 # Number of times rename has blocked due to LSQ full
-system.cpu1.rename.RENAME:RenameLookups 447878 # Number of register rename lookups that rename has made
-system.cpu1.rename.RENAME:RenamedInsts 290237 # Number of instructions processed by rename
-system.cpu1.rename.RENAME:RenamedOperands 204758 # Number of destination operands rename has renamed
-system.cpu1.rename.RENAME:RunCycles 133245 # Number of cycles rename is running
-system.cpu1.rename.RENAME:SquashCycles 33628 # Number of cycles rename is squashing
-system.cpu1.rename.RENAME:UnblockCycles 630 # Number of cycles rename is unblocking
-system.cpu1.rename.RENAME:UndoneMaps 119564 # Number of HB maps that are undone due to squashing
-system.cpu1.rename.RENAME:serializeStallCycles 29341 # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RENAME:serializingInsts 8772 # count of serializing insts renamed
-system.cpu1.rename.RENAME:skidInsts 33179 # count of insts added to the skid buffer
-system.cpu1.rename.RENAME:tempSerializingInsts 8900 # count of temporary serializing insts renamed
-system.cpu1.timesIdled 285 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu1.iq.ISSUE:issued_per_cycle::total 196865 # Number of insts issued each cycle
+system.cpu1.iq.ISSUE:rate 1.315841 # Inst issue rate
+system.cpu1.iq.iqInstsAdded 259216 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqInstsIssued 263430 # Number of instructions issued
+system.cpu1.iq.iqNonSpecInstsAdded 7018 # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqSquashedInstsExamined 6568 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedInstsIssued 1 # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedNonSpecRemoved 602 # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.iqSquashedOperandsExamined 6183 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.memDep0.conflictingLoads 44382 # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores 38318 # Number of conflicting stores.
+system.cpu1.memDep0.insertedLoads 90756 # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores 42793 # Number of stores inserted to the mem dependence unit.
+system.cpu1.numCycles 200199 # number of cpu cycles simulated
+system.cpu1.rename.RENAME:BlockCycles 7060 # Number of cycles rename is blocking
+system.cpu1.rename.RENAME:CommittedMaps 207910 # Number of HB maps that are committed
+system.cpu1.rename.RENAME:IQFullEvents 85 # Number of times rename has blocked due to IQ full
+system.cpu1.rename.RENAME:IdleCycles 54204 # Number of cycles rename is idle
+system.cpu1.rename.RENAME:LSQFullEvents 50 # Number of times rename has blocked due to LSQ full
+system.cpu1.rename.RENAME:RenameLookups 600624 # Number of register rename lookups that rename has made
+system.cpu1.rename.RENAME:RenamedInsts 313715 # Number of instructions processed by rename
+system.cpu1.rename.RENAME:RenamedOperands 216199 # Number of destination operands rename has renamed
+system.cpu1.rename.RENAME:RunCycles 113621 # Number of cycles rename is running
+system.cpu1.rename.RENAME:SquashCycles 1776 # Number of cycles rename is squashing
+system.cpu1.rename.RENAME:UnblockCycles 643 # Number of cycles rename is unblocking
+system.cpu1.rename.RENAME:UndoneMaps 8289 # Number of HB maps that are undone due to squashing
+system.cpu1.rename.RENAME:serializeStallCycles 12945 # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RENAME:serializingInsts 960 # count of serializing insts renamed
+system.cpu1.rename.RENAME:skidInsts 2963 # count of insts added to the skid buffer
+system.cpu1.rename.RENAME:tempSerializingInsts 1012 # count of temporary serializing insts renamed
+system.cpu1.timesIdled 296 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu2.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu2.BPredUnit.BTBHits 52073 # Number of BTB hits
-system.cpu2.BPredUnit.BTBLookups 66680 # Number of BTB lookups
+system.cpu2.BPredUnit.BTBHits 47889 # Number of BTB hits
+system.cpu2.BPredUnit.BTBLookups 50081 # Number of BTB lookups
system.cpu2.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
-system.cpu2.BPredUnit.condIncorrect 30422 # Number of conditional branches incorrect
-system.cpu2.BPredUnit.condPredicted 81408 # Number of conditional branches predicted
-system.cpu2.BPredUnit.lookups 81408 # Number of BP lookups
+system.cpu2.BPredUnit.condIncorrect 1085 # Number of conditional branches incorrect
+system.cpu2.BPredUnit.condPredicted 50180 # Number of conditional branches predicted
+system.cpu2.BPredUnit.lookups 50180 # Number of BP lookups
system.cpu2.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
-system.cpu2.commit.COM:branches 25190 # Number of branches committed
-system.cpu2.commit.COM:bw_lim_events 578 # number cycles where commit BW limit reached
+system.cpu2.commit.COM:branches 47494 # Number of branches committed
+system.cpu2.commit.COM:bw_lim_events 498 # number cycles where commit BW limit reached
system.cpu2.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
-system.cpu2.commit.COM:committed_per_cycle::samples 347008 # Number of insts commited each cycle
-system.cpu2.commit.COM:committed_per_cycle::mean 0.368821 # Number of insts commited each cycle
-system.cpu2.commit.COM:committed_per_cycle::stdev 0.833965 # Number of insts commited each cycle
+system.cpu2.commit.COM:committed_per_cycle::samples 185767 # Number of insts commited each cycle
+system.cpu2.commit.COM:committed_per_cycle::mean 1.418212 # Number of insts commited each cycle
+system.cpu2.commit.COM:committed_per_cycle::stdev 1.887646 # Number of insts commited each cycle
system.cpu2.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu2.commit.COM:committed_per_cycle::0 262750 75.72% 75.72% # Number of insts commited each cycle
-system.cpu2.commit.COM:committed_per_cycle::1 55494 15.99% 91.71% # Number of insts commited each cycle
-system.cpu2.commit.COM:committed_per_cycle::2 23803 6.86% 98.57% # Number of insts commited each cycle
-system.cpu2.commit.COM:committed_per_cycle::3 1293 0.37% 98.94% # Number of insts commited each cycle
-system.cpu2.commit.COM:committed_per_cycle::4 820 0.24% 99.18% # Number of insts commited each cycle
-system.cpu2.commit.COM:committed_per_cycle::5 559 0.16% 99.34% # Number of insts commited each cycle
-system.cpu2.commit.COM:committed_per_cycle::6 1671 0.48% 99.82% # Number of insts commited each cycle
-system.cpu2.commit.COM:committed_per_cycle::7 40 0.01% 99.83% # Number of insts commited each cycle
-system.cpu2.commit.COM:committed_per_cycle::8 578 0.17% 100.00% # Number of insts commited each cycle
+system.cpu2.commit.COM:committed_per_cycle::0 86596 46.62% 46.62% # Number of insts commited each cycle
+system.cpu2.commit.COM:committed_per_cycle::1 48193 25.94% 72.56% # Number of insts commited each cycle
+system.cpu2.commit.COM:committed_per_cycle::2 7461 4.02% 76.57% # Number of insts commited each cycle
+system.cpu2.commit.COM:committed_per_cycle::3 8520 4.59% 81.16% # Number of insts commited each cycle
+system.cpu2.commit.COM:committed_per_cycle::4 2452 1.32% 82.48% # Number of insts commited each cycle
+system.cpu2.commit.COM:committed_per_cycle::5 31422 16.91% 99.40% # Number of insts commited each cycle
+system.cpu2.commit.COM:committed_per_cycle::6 495 0.27% 99.66% # Number of insts commited each cycle
+system.cpu2.commit.COM:committed_per_cycle::7 130 0.07% 99.73% # Number of insts commited each cycle
+system.cpu2.commit.COM:committed_per_cycle::8 498 0.27% 100.00% # Number of insts commited each cycle
system.cpu2.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu2.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu2.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu2.commit.COM:committed_per_cycle::total 347008 # Number of insts commited each cycle
-system.cpu2.commit.COM:count 127984 # Number of instructions committed
-system.cpu2.commit.COM:loads 30137 # Number of loads committed
-system.cpu2.commit.COM:membars 7796 # Number of memory barriers committed
-system.cpu2.commit.COM:refs 41570 # Number of memory references committed
+system.cpu2.commit.COM:committed_per_cycle::total 185767 # Number of insts commited each cycle
+system.cpu2.commit.COM:count 263457 # Number of instructions committed
+system.cpu2.commit.COM:loads 75571 # Number of loads committed
+system.cpu2.commit.COM:membars 6984 # Number of memory barriers committed
+system.cpu2.commit.COM:refs 110122 # Number of memory references committed
system.cpu2.commit.COM:swp_count 0 # Number of s/w prefetches committed
-system.cpu2.commit.branchMispredicts 30422 # The number of times a branch was mispredicted
-system.cpu2.commit.commitCommittedInsts 127984 # The number of committed instructions
-system.cpu2.commit.commitNonSpecStalls 8513 # The number of times commit has been forced to stall to communicate backwards
-system.cpu2.commit.commitSquashedInsts 138030 # The number of squashed insts skipped by commit
-system.cpu2.committedInsts 104211 # Number of Instructions Simulated
-system.cpu2.committedInsts_total 104211 # Number of Instructions Simulated
-system.cpu2.cpi 3.790608 # CPI: Cycles Per Instruction
-system.cpu2.cpi_total 3.790608 # CPI: Total CPI of All Threads
-system.cpu2.dcache.ReadReq_accesses 28582 # number of ReadReq accesses(hits+misses)
-system.cpu2.dcache.ReadReq_avg_miss_latency 19289.473684 # average ReadReq miss latency
-system.cpu2.dcache.ReadReq_avg_mshr_miss_latency 17373.563218 # average ReadReq mshr miss latency
-system.cpu2.dcache.ReadReq_hits 28373 # number of ReadReq hits
-system.cpu2.dcache.ReadReq_miss_latency 4031500 # number of ReadReq miss cycles
-system.cpu2.dcache.ReadReq_miss_rate 0.007312 # miss rate for ReadReq accesses
-system.cpu2.dcache.ReadReq_misses 209 # number of ReadReq misses
-system.cpu2.dcache.ReadReq_mshr_hits 35 # number of ReadReq MSHR hits
-system.cpu2.dcache.ReadReq_mshr_miss_latency 3023000 # number of ReadReq MSHR miss cycles
-system.cpu2.dcache.ReadReq_mshr_miss_rate 0.006088 # mshr miss rate for ReadReq accesses
-system.cpu2.dcache.ReadReq_mshr_misses 174 # number of ReadReq MSHR misses
-system.cpu2.dcache.SwapReq_accesses 71 # number of SwapReq accesses(hits+misses)
-system.cpu2.dcache.SwapReq_avg_miss_latency 21973.684211 # average SwapReq miss latency
-system.cpu2.dcache.SwapReq_avg_mshr_miss_latency 23510.869565 # average SwapReq mshr miss latency
-system.cpu2.dcache.SwapReq_hits 14 # number of SwapReq hits
-system.cpu2.dcache.SwapReq_miss_latency 1252500 # number of SwapReq miss cycles
-system.cpu2.dcache.SwapReq_miss_rate 0.802817 # miss rate for SwapReq accesses
-system.cpu2.dcache.SwapReq_misses 57 # number of SwapReq misses
-system.cpu2.dcache.SwapReq_mshr_hits 11 # number of SwapReq MSHR hits
-system.cpu2.dcache.SwapReq_mshr_miss_latency 1081500 # number of SwapReq MSHR miss cycles
-system.cpu2.dcache.SwapReq_mshr_miss_rate 0.647887 # mshr miss rate for SwapReq accesses
-system.cpu2.dcache.SwapReq_mshr_misses 46 # number of SwapReq MSHR misses
-system.cpu2.dcache.WriteReq_accesses 11362 # number of WriteReq accesses(hits+misses)
-system.cpu2.dcache.WriteReq_avg_miss_latency 24003.906250 # average WriteReq miss latency
-system.cpu2.dcache.WriteReq_avg_mshr_miss_latency 15831.818182 # average WriteReq mshr miss latency
-system.cpu2.dcache.WriteReq_hits 11234 # number of WriteReq hits
-system.cpu2.dcache.WriteReq_miss_latency 3072500 # number of WriteReq miss cycles
-system.cpu2.dcache.WriteReq_miss_rate 0.011266 # miss rate for WriteReq accesses
-system.cpu2.dcache.WriteReq_misses 128 # number of WriteReq misses
-system.cpu2.dcache.WriteReq_mshr_hits 18 # number of WriteReq MSHR hits
-system.cpu2.dcache.WriteReq_mshr_miss_latency 1741500 # number of WriteReq MSHR miss cycles
-system.cpu2.dcache.WriteReq_mshr_miss_rate 0.009681 # mshr miss rate for WriteReq accesses
-system.cpu2.dcache.WriteReq_mshr_misses 110 # number of WriteReq MSHR misses
+system.cpu2.commit.branchMispredicts 1085 # The number of times a branch was mispredicted
+system.cpu2.commit.commitCommittedInsts 263457 # The number of committed instructions
+system.cpu2.commit.commitNonSpecStalls 7697 # The number of times commit has been forced to stall to communicate backwards
+system.cpu2.commit.commitSquashedInsts 7870 # The number of squashed insts skipped by commit
+system.cpu2.committedInsts 218188 # Number of Instructions Simulated
+system.cpu2.committedInsts_total 218188 # Number of Instructions Simulated
+system.cpu2.cpi 0.916214 # CPI: Cycles Per Instruction
+system.cpu2.cpi_total 0.916214 # CPI: Total CPI of All Threads
+system.cpu2.dcache.ReadReq_accesses 45603 # number of ReadReq accesses(hits+misses)
+system.cpu2.dcache.ReadReq_avg_miss_latency 22462.882096 # average ReadReq miss latency
+system.cpu2.dcache.ReadReq_avg_mshr_miss_latency 15906.060606 # average ReadReq mshr miss latency
+system.cpu2.dcache.ReadReq_hits 45145 # number of ReadReq hits
+system.cpu2.dcache.ReadReq_miss_latency 10288000 # number of ReadReq miss cycles
+system.cpu2.dcache.ReadReq_miss_rate 0.010043 # miss rate for ReadReq accesses
+system.cpu2.dcache.ReadReq_misses 458 # number of ReadReq misses
+system.cpu2.dcache.ReadReq_mshr_hits 293 # number of ReadReq MSHR hits
+system.cpu2.dcache.ReadReq_mshr_miss_latency 2624500 # number of ReadReq MSHR miss cycles
+system.cpu2.dcache.ReadReq_mshr_miss_rate 0.003618 # mshr miss rate for ReadReq accesses
+system.cpu2.dcache.ReadReq_mshr_misses 165 # number of ReadReq MSHR misses
+system.cpu2.dcache.SwapReq_accesses 67 # number of SwapReq accesses(hits+misses)
+system.cpu2.dcache.SwapReq_avg_miss_latency 27057.692308 # average SwapReq miss latency
+system.cpu2.dcache.SwapReq_avg_mshr_miss_latency 24057.692308 # average SwapReq mshr miss latency
+system.cpu2.dcache.SwapReq_hits 15 # number of SwapReq hits
+system.cpu2.dcache.SwapReq_miss_latency 1407000 # number of SwapReq miss cycles
+system.cpu2.dcache.SwapReq_miss_rate 0.776119 # miss rate for SwapReq accesses
+system.cpu2.dcache.SwapReq_misses 52 # number of SwapReq misses
+system.cpu2.dcache.SwapReq_mshr_miss_latency 1251000 # number of SwapReq MSHR miss cycles
+system.cpu2.dcache.SwapReq_mshr_miss_rate 0.776119 # mshr miss rate for SwapReq accesses
+system.cpu2.dcache.SwapReq_mshr_misses 52 # number of SwapReq MSHR misses
+system.cpu2.dcache.WriteReq_accesses 34484 # number of WriteReq accesses(hits+misses)
+system.cpu2.dcache.WriteReq_avg_miss_latency 24804.878049 # average WriteReq miss latency
+system.cpu2.dcache.WriteReq_avg_mshr_miss_latency 16634.615385 # average WriteReq mshr miss latency
+system.cpu2.dcache.WriteReq_hits 34361 # number of WriteReq hits
+system.cpu2.dcache.WriteReq_miss_latency 3051000 # number of WriteReq miss cycles
+system.cpu2.dcache.WriteReq_miss_rate 0.003567 # miss rate for WriteReq accesses
+system.cpu2.dcache.WriteReq_misses 123 # number of WriteReq misses
+system.cpu2.dcache.WriteReq_mshr_hits 19 # number of WriteReq MSHR hits
+system.cpu2.dcache.WriteReq_mshr_miss_latency 1730000 # number of WriteReq MSHR miss cycles
+system.cpu2.dcache.WriteReq_mshr_miss_rate 0.003016 # mshr miss rate for WriteReq accesses
+system.cpu2.dcache.WriteReq_mshr_misses 104 # number of WriteReq MSHR misses
system.cpu2.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu2.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu2.dcache.avg_refs 708.483871 # Average number of references to valid blocks.
+system.cpu2.dcache.avg_refs 1342.733333 # Average number of references to valid blocks.
system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu2.dcache.cache_copies 0 # number of cache copies performed
-system.cpu2.dcache.demand_accesses 39944 # number of demand (read+write) accesses
-system.cpu2.dcache.demand_avg_miss_latency 21080.118694 # average overall miss latency
-system.cpu2.dcache.demand_avg_mshr_miss_latency 16776.408451 # average overall mshr miss latency
-system.cpu2.dcache.demand_hits 39607 # number of demand (read+write) hits
-system.cpu2.dcache.demand_miss_latency 7104000 # number of demand (read+write) miss cycles
-system.cpu2.dcache.demand_miss_rate 0.008437 # miss rate for demand accesses
-system.cpu2.dcache.demand_misses 337 # number of demand (read+write) misses
-system.cpu2.dcache.demand_mshr_hits 53 # number of demand (read+write) MSHR hits
-system.cpu2.dcache.demand_mshr_miss_latency 4764500 # number of demand (read+write) MSHR miss cycles
-system.cpu2.dcache.demand_mshr_miss_rate 0.007110 # mshr miss rate for demand accesses
-system.cpu2.dcache.demand_mshr_misses 284 # number of demand (read+write) MSHR misses
+system.cpu2.dcache.demand_accesses 80087 # number of demand (read+write) accesses
+system.cpu2.dcache.demand_avg_miss_latency 22958.691910 # average overall miss latency
+system.cpu2.dcache.demand_avg_mshr_miss_latency 16187.732342 # average overall mshr miss latency
+system.cpu2.dcache.demand_hits 79506 # number of demand (read+write) hits
+system.cpu2.dcache.demand_miss_latency 13339000 # number of demand (read+write) miss cycles
+system.cpu2.dcache.demand_miss_rate 0.007255 # miss rate for demand accesses
+system.cpu2.dcache.demand_misses 581 # number of demand (read+write) misses
+system.cpu2.dcache.demand_mshr_hits 312 # number of demand (read+write) MSHR hits
+system.cpu2.dcache.demand_mshr_miss_latency 4354500 # number of demand (read+write) MSHR miss cycles
+system.cpu2.dcache.demand_mshr_miss_rate 0.003359 # mshr miss rate for demand accesses
+system.cpu2.dcache.demand_mshr_misses 269 # number of demand (read+write) MSHR misses
system.cpu2.dcache.fast_writes 0 # number of fast writes performed
system.cpu2.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu2.dcache.occ_%::0 0.057032 # Average percentage of cache occupancy
-system.cpu2.dcache.occ_%::1 -0.010468 # Average percentage of cache occupancy
-system.cpu2.dcache.occ_blocks::0 29.200191 # Average occupied blocks per context
-system.cpu2.dcache.occ_blocks::1 -5.359479 # Average occupied blocks per context
-system.cpu2.dcache.overall_accesses 39944 # number of overall (read+write) accesses
-system.cpu2.dcache.overall_avg_miss_latency 21080.118694 # average overall miss latency
-system.cpu2.dcache.overall_avg_mshr_miss_latency 16776.408451 # average overall mshr miss latency
+system.cpu2.dcache.occ_%::0 0.052876 # Average percentage of cache occupancy
+system.cpu2.dcache.occ_%::1 -0.017040 # Average percentage of cache occupancy
+system.cpu2.dcache.occ_blocks::0 27.072320 # Average occupied blocks per context
+system.cpu2.dcache.occ_blocks::1 -8.724259 # Average occupied blocks per context
+system.cpu2.dcache.overall_accesses 80087 # number of overall (read+write) accesses
+system.cpu2.dcache.overall_avg_miss_latency 22958.691910 # average overall miss latency
+system.cpu2.dcache.overall_avg_mshr_miss_latency 16187.732342 # average overall mshr miss latency
system.cpu2.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu2.dcache.overall_hits 39607 # number of overall hits
-system.cpu2.dcache.overall_miss_latency 7104000 # number of overall miss cycles
-system.cpu2.dcache.overall_miss_rate 0.008437 # miss rate for overall accesses
-system.cpu2.dcache.overall_misses 337 # number of overall misses
-system.cpu2.dcache.overall_mshr_hits 53 # number of overall MSHR hits
-system.cpu2.dcache.overall_mshr_miss_latency 4764500 # number of overall MSHR miss cycles
-system.cpu2.dcache.overall_mshr_miss_rate 0.007110 # mshr miss rate for overall accesses
-system.cpu2.dcache.overall_mshr_misses 284 # number of overall MSHR misses
+system.cpu2.dcache.overall_hits 79506 # number of overall hits
+system.cpu2.dcache.overall_miss_latency 13339000 # number of overall miss cycles
+system.cpu2.dcache.overall_miss_rate 0.007255 # miss rate for overall accesses
+system.cpu2.dcache.overall_misses 581 # number of overall misses
+system.cpu2.dcache.overall_mshr_hits 312 # number of overall MSHR hits
+system.cpu2.dcache.overall_mshr_miss_latency 4354500 # number of overall MSHR miss cycles
+system.cpu2.dcache.overall_mshr_miss_rate 0.003359 # mshr miss rate for overall accesses
+system.cpu2.dcache.overall_mshr_misses 269 # number of overall MSHR misses
system.cpu2.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu2.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu2.dcache.replacements 2 # number of replacements
-system.cpu2.dcache.sampled_refs 31 # Sample count of references to valid blocks.
+system.cpu2.dcache.sampled_refs 30 # Sample count of references to valid blocks.
system.cpu2.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu2.dcache.tagsinuse 23.840712 # Cycle average of tags in use
-system.cpu2.dcache.total_refs 21963 # Total number of references to valid blocks.
+system.cpu2.dcache.tagsinuse 18.348061 # Cycle average of tags in use
+system.cpu2.dcache.total_refs 40282 # Total number of references to valid blocks.
system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu2.dcache.writebacks 1 # number of writebacks
-system.cpu2.decode.DECODE:BlockedCycles 31861 # Number of cycles decode is blocked
-system.cpu2.decode.DECODE:DecodedInsts 361505 # Number of instructions handled by decode
-system.cpu2.decode.DECODE:IdleCycles 170760 # Number of cycles decode is idle
-system.cpu2.decode.DECODE:RunCycles 144226 # Number of cycles decode is running
-system.cpu2.decode.DECODE:SquashCycles 34255 # Number of cycles decode is squashing
-system.cpu2.decode.DECODE:UnblockCycles 161 # Number of cycles decode is unblocking
-system.cpu2.fetch.Branches 81408 # Number of branches that fetch encountered
-system.cpu2.fetch.CacheLines 81347 # Number of cache lines fetched
-system.cpu2.fetch.Cycles 236913 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu2.fetch.IcacheSquashes 10044 # Number of outstanding Icache misses that were squashed
-system.cpu2.fetch.Insts 412447 # Number of instructions fetch has processed
-system.cpu2.fetch.SquashCycles 30579 # Number of cycles fetch has spent squashing
-system.cpu2.fetch.branchRate 0.206084 # Number of branch fetches per cycle
-system.cpu2.fetch.icacheStallCycles 81347 # Number of cycles fetch is stalled on an Icache miss
-system.cpu2.fetch.predictedBranches 52073 # Number of branches that fetch has predicted taken
-system.cpu2.fetch.rate 1.044109 # Number of inst fetches per cycle
-system.cpu2.fetch.rateDist::samples 389876 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::mean 1.057893 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::stdev 1.974904 # Number of instructions fetched each cycle (Total)
+system.cpu2.decode.DECODE:BlockedCycles 22115 # Number of cycles decode is blocked
+system.cpu2.decode.DECODE:DecodedInsts 275229 # Number of instructions handled by decode
+system.cpu2.decode.DECODE:IdleCycles 60651 # Number of cycles decode is idle
+system.cpu2.decode.DECODE:RunCycles 96513 # Number of cycles decode is running
+system.cpu2.decode.DECODE:SquashCycles 1718 # Number of cycles decode is squashing
+system.cpu2.decode.DECODE:UnblockCycles 6488 # Number of cycles decode is unblocking
+system.cpu2.fetch.Branches 50180 # Number of branches that fetch encountered
+system.cpu2.fetch.CacheLines 22951 # Number of cache lines fetched
+system.cpu2.fetch.Cycles 126346 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu2.fetch.IcacheSquashes 219 # Number of outstanding Icache misses that were squashed
+system.cpu2.fetch.Insts 276356 # Number of instructions fetch has processed
+system.cpu2.fetch.SquashCycles 1162 # Number of cycles fetch has spent squashing
+system.cpu2.fetch.branchRate 0.251017 # Number of branch fetches per cycle
+system.cpu2.fetch.icacheStallCycles 22951 # Number of cycles fetch is stalled on an Icache miss
+system.cpu2.fetch.predictedBranches 47889 # Number of branches that fetch has predicted taken
+system.cpu2.fetch.rate 1.382423 # Number of inst fetches per cycle
+system.cpu2.fetch.rateDist::samples 194083 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::mean 1.423906 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::stdev 1.970447 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::0 234334 60.10% 60.10% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::1 83865 21.51% 81.62% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::2 17837 4.58% 86.19% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::3 14411 3.70% 89.89% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::4 2742 0.70% 90.59% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::5 16550 4.24% 94.84% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::6 1358 0.35% 95.18% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::7 2423 0.62% 95.80% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::8 16356 4.20% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::0 90718 46.74% 46.74% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::1 54044 27.85% 74.59% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::2 8214 4.23% 78.82% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::3 2581 1.33% 80.15% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::4 1900 0.98% 81.13% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::5 32424 16.71% 97.83% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::6 2464 1.27% 99.10% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::7 267 0.14% 99.24% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::8 1471 0.76% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::total 389876 # Number of instructions fetched each cycle (Total)
-system.cpu2.icache.ReadReq_accesses 81347 # number of ReadReq accesses(hits+misses)
-system.cpu2.icache.ReadReq_avg_miss_latency 18963.235294 # average ReadReq miss latency
-system.cpu2.icache.ReadReq_avg_mshr_miss_latency 16003.955696 # average ReadReq mshr miss latency
-system.cpu2.icache.ReadReq_hits 80599 # number of ReadReq hits
-system.cpu2.icache.ReadReq_miss_latency 14184500 # number of ReadReq miss cycles
-system.cpu2.icache.ReadReq_miss_rate 0.009195 # miss rate for ReadReq accesses
-system.cpu2.icache.ReadReq_misses 748 # number of ReadReq misses
-system.cpu2.icache.ReadReq_mshr_hits 116 # number of ReadReq MSHR hits
-system.cpu2.icache.ReadReq_mshr_miss_latency 10114500 # number of ReadReq MSHR miss cycles
-system.cpu2.icache.ReadReq_mshr_miss_rate 0.007769 # mshr miss rate for ReadReq accesses
-system.cpu2.icache.ReadReq_mshr_misses 632 # number of ReadReq MSHR misses
-system.cpu2.icache.avg_blocked_cycles::no_mshrs 32500 # average number of cycles each access was blocked
+system.cpu2.fetch.rateDist::total 194083 # Number of instructions fetched each cycle (Total)
+system.cpu2.icache.ReadReq_accesses 22951 # number of ReadReq accesses(hits+misses)
+system.cpu2.icache.ReadReq_avg_miss_latency 21668.711656 # average ReadReq miss latency
+system.cpu2.icache.ReadReq_avg_mshr_miss_latency 18378.959276 # average ReadReq mshr miss latency
+system.cpu2.icache.ReadReq_hits 22462 # number of ReadReq hits
+system.cpu2.icache.ReadReq_miss_latency 10596000 # number of ReadReq miss cycles
+system.cpu2.icache.ReadReq_miss_rate 0.021306 # miss rate for ReadReq accesses
+system.cpu2.icache.ReadReq_misses 489 # number of ReadReq misses
+system.cpu2.icache.ReadReq_mshr_hits 47 # number of ReadReq MSHR hits
+system.cpu2.icache.ReadReq_mshr_miss_latency 8123500 # number of ReadReq MSHR miss cycles
+system.cpu2.icache.ReadReq_mshr_miss_rate 0.019258 # mshr miss rate for ReadReq accesses
+system.cpu2.icache.ReadReq_mshr_misses 442 # number of ReadReq MSHR misses
+system.cpu2.icache.avg_blocked_cycles::no_mshrs 18250 # average number of cycles each access was blocked
system.cpu2.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu2.icache.avg_refs 127.530063 # Average number of references to valid blocks.
-system.cpu2.icache.blocked::no_mshrs 1 # number of cycles access was blocked
+system.cpu2.icache.avg_refs 50.819005 # Average number of references to valid blocks.
+system.cpu2.icache.blocked::no_mshrs 2 # number of cycles access was blocked
system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu2.icache.blocked_cycles::no_mshrs 32500 # number of cycles access was blocked
+system.cpu2.icache.blocked_cycles::no_mshrs 36500 # number of cycles access was blocked
system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu2.icache.cache_copies 0 # number of cache copies performed
-system.cpu2.icache.demand_accesses 81347 # number of demand (read+write) accesses
-system.cpu2.icache.demand_avg_miss_latency 18963.235294 # average overall miss latency
-system.cpu2.icache.demand_avg_mshr_miss_latency 16003.955696 # average overall mshr miss latency
-system.cpu2.icache.demand_hits 80599 # number of demand (read+write) hits
-system.cpu2.icache.demand_miss_latency 14184500 # number of demand (read+write) miss cycles
-system.cpu2.icache.demand_miss_rate 0.009195 # miss rate for demand accesses
-system.cpu2.icache.demand_misses 748 # number of demand (read+write) misses
-system.cpu2.icache.demand_mshr_hits 116 # number of demand (read+write) MSHR hits
-system.cpu2.icache.demand_mshr_miss_latency 10114500 # number of demand (read+write) MSHR miss cycles
-system.cpu2.icache.demand_mshr_miss_rate 0.007769 # mshr miss rate for demand accesses
-system.cpu2.icache.demand_mshr_misses 632 # number of demand (read+write) MSHR misses
+system.cpu2.icache.demand_accesses 22951 # number of demand (read+write) accesses
+system.cpu2.icache.demand_avg_miss_latency 21668.711656 # average overall miss latency
+system.cpu2.icache.demand_avg_mshr_miss_latency 18378.959276 # average overall mshr miss latency
+system.cpu2.icache.demand_hits 22462 # number of demand (read+write) hits
+system.cpu2.icache.demand_miss_latency 10596000 # number of demand (read+write) miss cycles
+system.cpu2.icache.demand_miss_rate 0.021306 # miss rate for demand accesses
+system.cpu2.icache.demand_misses 489 # number of demand (read+write) misses
+system.cpu2.icache.demand_mshr_hits 47 # number of demand (read+write) MSHR hits
+system.cpu2.icache.demand_mshr_miss_latency 8123500 # number of demand (read+write) MSHR miss cycles
+system.cpu2.icache.demand_mshr_miss_rate 0.019258 # mshr miss rate for demand accesses
+system.cpu2.icache.demand_mshr_misses 442 # number of demand (read+write) MSHR misses
system.cpu2.icache.fast_writes 0 # number of fast writes performed
system.cpu2.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu2.icache.occ_%::0 0.191472 # Average percentage of cache occupancy
-system.cpu2.icache.occ_blocks::0 98.033912 # Average occupied blocks per context
-system.cpu2.icache.overall_accesses 81347 # number of overall (read+write) accesses
-system.cpu2.icache.overall_avg_miss_latency 18963.235294 # average overall miss latency
-system.cpu2.icache.overall_avg_mshr_miss_latency 16003.955696 # average overall mshr miss latency
+system.cpu2.icache.occ_%::0 0.176802 # Average percentage of cache occupancy
+system.cpu2.icache.occ_blocks::0 90.522409 # Average occupied blocks per context
+system.cpu2.icache.overall_accesses 22951 # number of overall (read+write) accesses
+system.cpu2.icache.overall_avg_miss_latency 21668.711656 # average overall miss latency
+system.cpu2.icache.overall_avg_mshr_miss_latency 18378.959276 # average overall mshr miss latency
system.cpu2.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu2.icache.overall_hits 80599 # number of overall hits
-system.cpu2.icache.overall_miss_latency 14184500 # number of overall miss cycles
-system.cpu2.icache.overall_miss_rate 0.009195 # miss rate for overall accesses
-system.cpu2.icache.overall_misses 748 # number of overall misses
-system.cpu2.icache.overall_mshr_hits 116 # number of overall MSHR hits
-system.cpu2.icache.overall_mshr_miss_latency 10114500 # number of overall MSHR miss cycles
-system.cpu2.icache.overall_mshr_miss_rate 0.007769 # mshr miss rate for overall accesses
-system.cpu2.icache.overall_mshr_misses 632 # number of overall MSHR misses
+system.cpu2.icache.overall_hits 22462 # number of overall hits
+system.cpu2.icache.overall_miss_latency 10596000 # number of overall miss cycles
+system.cpu2.icache.overall_miss_rate 0.021306 # miss rate for overall accesses
+system.cpu2.icache.overall_misses 489 # number of overall misses
+system.cpu2.icache.overall_mshr_hits 47 # number of overall MSHR hits
+system.cpu2.icache.overall_mshr_miss_latency 8123500 # number of overall MSHR miss cycles
+system.cpu2.icache.overall_mshr_miss_rate 0.019258 # mshr miss rate for overall accesses
+system.cpu2.icache.overall_mshr_misses 442 # number of overall MSHR misses
system.cpu2.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu2.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu2.icache.replacements 522 # number of replacements
-system.cpu2.icache.sampled_refs 632 # Sample count of references to valid blocks.
+system.cpu2.icache.replacements 332 # number of replacements
+system.cpu2.icache.sampled_refs 442 # Sample count of references to valid blocks.
system.cpu2.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu2.icache.tagsinuse 98.033912 # Cycle average of tags in use
-system.cpu2.icache.total_refs 80599 # Total number of references to valid blocks.
+system.cpu2.icache.tagsinuse 90.522409 # Cycle average of tags in use
+system.cpu2.icache.total_refs 22462 # Total number of references to valid blocks.
system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu2.icache.writebacks 0 # number of writebacks
-system.cpu2.idleCycles 5147 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu2.iew.EXEC:branches 37149 # Number of branches executed
-system.cpu2.iew.EXEC:nop 47058 # number of nop insts executed
-system.cpu2.iew.EXEC:rate 0.419988 # Inst execution rate
-system.cpu2.iew.EXEC:refs 49104 # number of memory reference insts executed
-system.cpu2.iew.EXEC:stores 13043 # Number of stores executed
+system.cpu2.idleCycles 5824 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu2.iew.EXEC:branches 48041 # Number of branches executed
+system.cpu2.iew.EXEC:nop 38985 # number of nop insts executed
+system.cpu2.iew.EXEC:rate 1.144757 # Inst execution rate
+system.cpu2.iew.EXEC:refs 111164 # number of memory reference insts executed
+system.cpu2.iew.EXEC:stores 34874 # Number of stores executed
system.cpu2.iew.EXEC:swp 0 # number of swp insts executed
-system.cpu2.iew.WB:consumers 81150 # num instructions consuming a value
-system.cpu2.iew.WB:count 162295 # cumulative count of insts written-back
-system.cpu2.iew.WB:fanout 0.931855 # average fanout of values written-back
+system.cpu2.iew.WB:consumers 131236 # num instructions consuming a value
+system.cpu2.iew.WB:count 228477 # cumulative count of insts written-back
+system.cpu2.iew.WB:fanout 0.972142 # average fanout of values written-back
system.cpu2.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu2.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu2.iew.WB:producers 75620 # num instructions producing a value
-system.cpu2.iew.WB:rate 0.410849 # insts written-back per cycle
-system.cpu2.iew.WB:sent 162544 # cumulative count of insts sent to commit
-system.cpu2.iew.branchMispredicts 31026 # Number of branch mispredicts detected at execute
-system.cpu2.iew.iewBlockCycles 0 # Number of cycles IEW is blocking
-system.cpu2.iew.iewDispLoadInsts 40176 # Number of dispatched load instructions
-system.cpu2.iew.iewDispNonSpecInsts 9384 # Number of dispatched non-speculative instructions
-system.cpu2.iew.iewDispSquashedInsts 3614 # Number of squashed instructions skipped by dispatch
-system.cpu2.iew.iewDispStoreInsts 22433 # Number of dispatched store instructions
-system.cpu2.iew.iewDispatchedInsts 266034 # Number of instructions dispatched to IQ
-system.cpu2.iew.iewExecLoadInsts 36061 # Number of load instructions executed
-system.cpu2.iew.iewExecSquashedInsts 34221 # Number of squashed instructions skipped in execute
-system.cpu2.iew.iewExecutedInsts 165905 # Number of executed instructions
-system.cpu2.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
+system.cpu2.iew.WB:producers 127580 # num instructions producing a value
+system.cpu2.iew.WB:rate 1.142916 # insts written-back per cycle
+system.cpu2.iew.WB:sent 228606 # cumulative count of insts sent to commit
+system.cpu2.iew.branchMispredicts 1190 # Number of branch mispredicts detected at execute
+system.cpu2.iew.iewBlockCycles 1615 # Number of cycles IEW is blocking
+system.cpu2.iew.iewDispLoadInsts 76990 # Number of dispatched load instructions
+system.cpu2.iew.iewDispNonSpecInsts 921 # Number of dispatched non-speculative instructions
+system.cpu2.iew.iewDispSquashedInsts 577 # Number of squashed instructions skipped by dispatch
+system.cpu2.iew.iewDispStoreInsts 35262 # Number of dispatched store instructions
+system.cpu2.iew.iewDispatchedInsts 271358 # Number of instructions dispatched to IQ
+system.cpu2.iew.iewExecLoadInsts 76290 # Number of load instructions executed
+system.cpu2.iew.iewExecSquashedInsts 955 # Number of squashed instructions skipped in execute
+system.cpu2.iew.iewExecutedInsts 228845 # Number of executed instructions
+system.cpu2.iew.iewIQFullEvents 46 # Number of times the IQ has become full, causing a stall
system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
-system.cpu2.iew.iewSquashCycles 34255 # Number of cycles IEW is squashing
-system.cpu2.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking
+system.cpu2.iew.iewSquashCycles 1718 # Number of cycles IEW is squashing
+system.cpu2.iew.iewUnblockCycles 53 # Number of cycles IEW is unblocking
system.cpu2.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu2.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
-system.cpu2.iew.lsq.thread.0.forwLoads 7459 # Number of loads that had data forwarded from stores
-system.cpu2.iew.lsq.thread.0.ignoredResponses 11 # Number of memory responses ignored because the instruction is squashed
+system.cpu2.iew.lsq.thread.0.forwLoads 30669 # Number of loads that had data forwarded from stores
+system.cpu2.iew.lsq.thread.0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
system.cpu2.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu2.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu2.iew.lsq.thread.0.memOrderViolation 698 # Number of memory ordering violations
+system.cpu2.iew.lsq.thread.0.memOrderViolation 36 # Number of memory ordering violations
system.cpu2.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled
-system.cpu2.iew.lsq.thread.0.squashedLoads 10039 # Number of loads squashed
-system.cpu2.iew.lsq.thread.0.squashedStores 11000 # Number of stores squashed
-system.cpu2.iew.memOrderViolationEvents 698 # Number of memory order violations
-system.cpu2.iew.predictedNotTakenIncorrect 1011 # Number of branches that were predicted not taken incorrectly
-system.cpu2.iew.predictedTakenIncorrect 30015 # Number of branches that were predicted taken incorrectly
-system.cpu2.ipc 0.263810 # IPC: Instructions Per Cycle
-system.cpu2.ipc_total 0.263810 # IPC: Total IPC of All Threads
+system.cpu2.iew.lsq.thread.0.squashedLoads 1419 # Number of loads squashed
+system.cpu2.iew.lsq.thread.0.squashedStores 711 # Number of stores squashed
+system.cpu2.iew.memOrderViolationEvents 36 # Number of memory order violations
+system.cpu2.iew.predictedNotTakenIncorrect 197 # Number of branches that were predicted not taken incorrectly
+system.cpu2.iew.predictedTakenIncorrect 993 # Number of branches that were predicted taken incorrectly
+system.cpu2.ipc 1.091448 # IPC: Instructions Per Cycle
+system.cpu2.ipc_total 1.091448 # IPC: Total IPC of All Threads
system.cpu2.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu2.iq.ISSUE:FU_type_0::IntAlu 141339 70.63% 70.63% # Type of FU issued
-system.cpu2.iq.ISSUE:FU_type_0::IntMult 0 0.00% 70.63% # Type of FU issued
-system.cpu2.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 70.63% # Type of FU issued
-system.cpu2.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 70.63% # Type of FU issued
-system.cpu2.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 70.63% # Type of FU issued
-system.cpu2.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 70.63% # Type of FU issued
-system.cpu2.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 70.63% # Type of FU issued
-system.cpu2.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 70.63% # Type of FU issued
-system.cpu2.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 70.63% # Type of FU issued
-system.cpu2.iq.ISSUE:FU_type_0::MemRead 45052 22.51% 93.14% # Type of FU issued
-system.cpu2.iq.ISSUE:FU_type_0::MemWrite 13735 6.86% 100.00% # Type of FU issued
+system.cpu2.iq.ISSUE:FU_type_0::IntAlu 111446 48.50% 48.50% # Type of FU issued
+system.cpu2.iq.ISSUE:FU_type_0::IntMult 0 0.00% 48.50% # Type of FU issued
+system.cpu2.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 48.50% # Type of FU issued
+system.cpu2.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 48.50% # Type of FU issued
+system.cpu2.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 48.50% # Type of FU issued
+system.cpu2.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 48.50% # Type of FU issued
+system.cpu2.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 48.50% # Type of FU issued
+system.cpu2.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 48.50% # Type of FU issued
+system.cpu2.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 48.50% # Type of FU issued
+system.cpu2.iq.ISSUE:FU_type_0::MemRead 83455 36.32% 84.81% # Type of FU issued
+system.cpu2.iq.ISSUE:FU_type_0::MemWrite 34899 15.19% 100.00% # Type of FU issued
system.cpu2.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu2.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu2.iq.ISSUE:FU_type_0::total 200126 # Type of FU issued
-system.cpu2.iq.ISSUE:fu_busy_cnt 181 # FU busy when requested
-system.cpu2.iq.ISSUE:fu_busy_rate 0.000904 # FU busy rate (busy events/executed inst)
+system.cpu2.iq.ISSUE:FU_type_0::total 229800 # Type of FU issued
+system.cpu2.iq.ISSUE:fu_busy_cnt 187 # FU busy when requested
+system.cpu2.iq.ISSUE:fu_busy_rate 0.000814 # FU busy rate (busy events/executed inst)
system.cpu2.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu2.iq.ISSUE:fu_full::IntAlu 19 10.50% 10.50% # attempts to use FU when none available
-system.cpu2.iq.ISSUE:fu_full::IntMult 0 0.00% 10.50% # attempts to use FU when none available
-system.cpu2.iq.ISSUE:fu_full::IntDiv 0 0.00% 10.50% # attempts to use FU when none available
-system.cpu2.iq.ISSUE:fu_full::FloatAdd 0 0.00% 10.50% # attempts to use FU when none available
-system.cpu2.iq.ISSUE:fu_full::FloatCmp 0 0.00% 10.50% # attempts to use FU when none available
-system.cpu2.iq.ISSUE:fu_full::FloatCvt 0 0.00% 10.50% # attempts to use FU when none available
-system.cpu2.iq.ISSUE:fu_full::FloatMult 0 0.00% 10.50% # attempts to use FU when none available
-system.cpu2.iq.ISSUE:fu_full::FloatDiv 0 0.00% 10.50% # attempts to use FU when none available
-system.cpu2.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 10.50% # attempts to use FU when none available
-system.cpu2.iq.ISSUE:fu_full::MemRead 17 9.39% 19.89% # attempts to use FU when none available
-system.cpu2.iq.ISSUE:fu_full::MemWrite 145 80.11% 100.00% # attempts to use FU when none available
+system.cpu2.iq.ISSUE:fu_full::IntAlu 11 5.88% 5.88% # attempts to use FU when none available
+system.cpu2.iq.ISSUE:fu_full::IntMult 0 0.00% 5.88% # attempts to use FU when none available
+system.cpu2.iq.ISSUE:fu_full::IntDiv 0 0.00% 5.88% # attempts to use FU when none available
+system.cpu2.iq.ISSUE:fu_full::FloatAdd 0 0.00% 5.88% # attempts to use FU when none available
+system.cpu2.iq.ISSUE:fu_full::FloatCmp 0 0.00% 5.88% # attempts to use FU when none available
+system.cpu2.iq.ISSUE:fu_full::FloatCvt 0 0.00% 5.88% # attempts to use FU when none available
+system.cpu2.iq.ISSUE:fu_full::FloatMult 0 0.00% 5.88% # attempts to use FU when none available
+system.cpu2.iq.ISSUE:fu_full::FloatDiv 0 0.00% 5.88% # attempts to use FU when none available
+system.cpu2.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 5.88% # attempts to use FU when none available
+system.cpu2.iq.ISSUE:fu_full::MemRead 48 25.67% 31.55% # attempts to use FU when none available
+system.cpu2.iq.ISSUE:fu_full::MemWrite 128 68.45% 100.00% # attempts to use FU when none available
system.cpu2.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu2.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu2.iq.ISSUE:issued_per_cycle::samples 389876 # Number of insts issued each cycle
-system.cpu2.iq.ISSUE:issued_per_cycle::mean 0.513307 # Number of insts issued each cycle
-system.cpu2.iq.ISSUE:issued_per_cycle::stdev 0.969448 # Number of insts issued each cycle
+system.cpu2.iq.ISSUE:issued_per_cycle::samples 194083 # Number of insts issued each cycle
+system.cpu2.iq.ISSUE:issued_per_cycle::mean 1.184030 # Number of insts issued each cycle
+system.cpu2.iq.ISSUE:issued_per_cycle::stdev 1.270781 # Number of insts issued each cycle
system.cpu2.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu2.iq.ISSUE:issued_per_cycle::0 272512 69.90% 69.90% # Number of insts issued each cycle
-system.cpu2.iq.ISSUE:issued_per_cycle::1 69416 17.80% 87.70% # Number of insts issued each cycle
-system.cpu2.iq.ISSUE:issued_per_cycle::2 25173 6.46% 94.16% # Number of insts issued each cycle
-system.cpu2.iq.ISSUE:issued_per_cycle::3 14490 3.72% 97.87% # Number of insts issued each cycle
-system.cpu2.iq.ISSUE:issued_per_cycle::4 5424 1.39% 99.27% # Number of insts issued each cycle
-system.cpu2.iq.ISSUE:issued_per_cycle::5 2186 0.56% 99.83% # Number of insts issued each cycle
-system.cpu2.iq.ISSUE:issued_per_cycle::6 485 0.12% 99.95% # Number of insts issued each cycle
-system.cpu2.iq.ISSUE:issued_per_cycle::7 162 0.04% 99.99% # Number of insts issued each cycle
-system.cpu2.iq.ISSUE:issued_per_cycle::8 28 0.01% 100.00% # Number of insts issued each cycle
+system.cpu2.iq.ISSUE:issued_per_cycle::0 86865 44.76% 44.76% # Number of insts issued each cycle
+system.cpu2.iq.ISSUE:issued_per_cycle::1 30647 15.79% 60.55% # Number of insts issued each cycle
+system.cpu2.iq.ISSUE:issued_per_cycle::2 37170 19.15% 79.70% # Number of insts issued each cycle
+system.cpu2.iq.ISSUE:issued_per_cycle::3 34973 18.02% 97.72% # Number of insts issued each cycle
+system.cpu2.iq.ISSUE:issued_per_cycle::4 2604 1.34% 99.06% # Number of insts issued each cycle
+system.cpu2.iq.ISSUE:issued_per_cycle::5 1569 0.81% 99.87% # Number of insts issued each cycle
+system.cpu2.iq.ISSUE:issued_per_cycle::6 161 0.08% 99.95% # Number of insts issued each cycle
+system.cpu2.iq.ISSUE:issued_per_cycle::7 85 0.04% 100.00% # Number of insts issued each cycle
+system.cpu2.iq.ISSUE:issued_per_cycle::8 9 0.00% 100.00% # Number of insts issued each cycle
system.cpu2.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu2.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu2.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu2.iq.ISSUE:issued_per_cycle::total 389876 # Number of insts issued each cycle
-system.cpu2.iq.ISSUE:rate 0.506619 # Inst issue rate
-system.cpu2.iq.iqInstsAdded 201728 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu2.iq.iqInstsIssued 200126 # Number of instructions issued
-system.cpu2.iq.iqNonSpecInstsAdded 17248 # Number of non-speculative instructions added to the IQ
-system.cpu2.iq.iqSquashedInstsExamined 77302 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu2.iq.iqSquashedInstsIssued 3 # Number of squashed instructions issued
-system.cpu2.iq.iqSquashedNonSpecRemoved 8735 # Number of squashed non-spec instructions that were removed
-system.cpu2.iq.iqSquashedOperandsExamined 33615 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu2.memDep0.conflictingLoads 7669 # Number of conflicting loads.
-system.cpu2.memDep0.conflictingStores 92 # Number of conflicting stores.
-system.cpu2.memDep0.insertedLoads 40176 # Number of loads inserted to the mem dependence unit.
-system.cpu2.memDep0.insertedStores 22433 # Number of stores inserted to the mem dependence unit.
-system.cpu2.numCycles 395023 # number of cpu cycles simulated
-system.cpu2.rename.RENAME:CommittedMaps 87600 # Number of HB maps that are committed
-system.cpu2.rename.RENAME:IdleCycles 183597 # Number of cycles rename is idle
-system.cpu2.rename.RENAME:RenameLookups 458439 # Number of register rename lookups that rename has made
-system.cpu2.rename.RENAME:RenamedInsts 293451 # Number of instructions processed by rename
-system.cpu2.rename.RENAME:RenamedOperands 211386 # Number of destination operands rename has renamed
-system.cpu2.rename.RENAME:RunCycles 131636 # Number of cycles rename is running
-system.cpu2.rename.RENAME:SquashCycles 34255 # Number of cycles rename is squashing
-system.cpu2.rename.RENAME:UnblockCycles 645 # Number of cycles rename is unblocking
-system.cpu2.rename.RENAME:UndoneMaps 123786 # Number of HB maps that are undone due to squashing
-system.cpu2.rename.RENAME:serializeStallCycles 31130 # count of cycles rename stalled for serializing inst
-system.cpu2.rename.RENAME:serializingInsts 9653 # count of serializing insts renamed
-system.cpu2.rename.RENAME:skidInsts 36749 # count of insts added to the skid buffer
-system.cpu2.rename.RENAME:tempSerializingInsts 9784 # count of temporary serializing insts renamed
-system.cpu2.timesIdled 292 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu2.iq.ISSUE:issued_per_cycle::total 194083 # Number of insts issued each cycle
+system.cpu2.iq.ISSUE:rate 1.149535 # Inst issue rate
+system.cpu2.iq.iqInstsAdded 224135 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu2.iq.iqInstsIssued 229800 # Number of instructions issued
+system.cpu2.iq.iqNonSpecInstsAdded 8238 # Number of non-speculative instructions added to the IQ
+system.cpu2.iq.iqSquashedInstsExamined 6304 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu2.iq.iqSquashedNonSpecRemoved 541 # Number of squashed non-spec instructions that were removed
+system.cpu2.iq.iqSquashedOperandsExamined 5829 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu2.memDep0.conflictingLoads 38114 # Number of conflicting loads.
+system.cpu2.memDep0.conflictingStores 30803 # Number of conflicting stores.
+system.cpu2.memDep0.insertedLoads 76990 # Number of loads inserted to the mem dependence unit.
+system.cpu2.memDep0.insertedStores 35262 # Number of stores inserted to the mem dependence unit.
+system.cpu2.numCycles 199907 # number of cpu cycles simulated
+system.cpu2.rename.RENAME:BlockCycles 8148 # Number of cycles rename is blocking
+system.cpu2.rename.RENAME:CommittedMaps 179272 # Number of HB maps that are committed
+system.cpu2.rename.RENAME:IQFullEvents 31 # Number of times rename has blocked due to IQ full
+system.cpu2.rename.RENAME:IdleCycles 61263 # Number of cycles rename is idle
+system.cpu2.rename.RENAME:LSQFullEvents 56 # Number of times rename has blocked due to LSQ full
+system.cpu2.rename.RENAME:RenameLookups 515407 # Number of register rename lookups that rename has made
+system.cpu2.rename.RENAME:RenamedInsts 273547 # Number of instructions processed by rename
+system.cpu2.rename.RENAME:RenamedOperands 187363 # Number of destination operands rename has renamed
+system.cpu2.rename.RENAME:RunCycles 102562 # Number of cycles rename is running
+system.cpu2.rename.RENAME:SquashCycles 1718 # Number of cycles rename is squashing
+system.cpu2.rename.RENAME:UnblockCycles 553 # Number of cycles rename is unblocking
+system.cpu2.rename.RENAME:UndoneMaps 8091 # Number of HB maps that are undone due to squashing
+system.cpu2.rename.RENAME:serializeStallCycles 13241 # count of cycles rename stalled for serializing inst
+system.cpu2.rename.RENAME:serializingInsts 943 # count of serializing insts renamed
+system.cpu2.rename.RENAME:skidInsts 2678 # count of insts added to the skid buffer
+system.cpu2.rename.RENAME:tempSerializingInsts 998 # count of temporary serializing insts renamed
+system.cpu2.timesIdled 306 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu3.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu3.BPredUnit.BTBHits 48405 # Number of BTB hits
-system.cpu3.BPredUnit.BTBLookups 65841 # Number of BTB lookups
+system.cpu3.BPredUnit.BTBHits 51000 # Number of BTB hits
+system.cpu3.BPredUnit.BTBLookups 53222 # Number of BTB lookups
system.cpu3.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
-system.cpu3.BPredUnit.condIncorrect 32660 # Number of conditional branches incorrect
-system.cpu3.BPredUnit.condPredicted 82266 # Number of conditional branches predicted
-system.cpu3.BPredUnit.lookups 82266 # Number of BP lookups
+system.cpu3.BPredUnit.condIncorrect 1107 # Number of conditional branches incorrect
+system.cpu3.BPredUnit.condPredicted 53282 # Number of conditional branches predicted
+system.cpu3.BPredUnit.lookups 53282 # Number of BP lookups
system.cpu3.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
-system.cpu3.commit.COM:branches 25082 # Number of branches committed
-system.cpu3.commit.COM:bw_lim_events 576 # number cycles where commit BW limit reached
+system.cpu3.commit.COM:branches 50377 # Number of branches committed
+system.cpu3.commit.COM:bw_lim_events 486 # number cycles where commit BW limit reached
system.cpu3.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
-system.cpu3.commit.COM:committed_per_cycle::samples 346536 # Number of insts commited each cycle
-system.cpu3.commit.COM:committed_per_cycle::mean 0.381828 # Number of insts commited each cycle
-system.cpu3.commit.COM:committed_per_cycle::stdev 0.836481 # Number of insts commited each cycle
+system.cpu3.commit.COM:committed_per_cycle::samples 188057 # Number of insts commited each cycle
+system.cpu3.commit.COM:committed_per_cycle::mean 1.497514 # Number of insts commited each cycle
+system.cpu3.commit.COM:committed_per_cycle::stdev 1.921417 # Number of insts commited each cycle
system.cpu3.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu3.commit.COM:committed_per_cycle::0 257870 74.41% 74.41% # Number of insts commited each cycle
-system.cpu3.commit.COM:committed_per_cycle::1 60023 17.32% 91.73% # Number of insts commited each cycle
-system.cpu3.commit.COM:committed_per_cycle::2 23680 6.83% 98.57% # Number of insts commited each cycle
-system.cpu3.commit.COM:committed_per_cycle::3 1288 0.37% 98.94% # Number of insts commited each cycle
-system.cpu3.commit.COM:committed_per_cycle::4 802 0.23% 99.17% # Number of insts commited each cycle
-system.cpu3.commit.COM:committed_per_cycle::5 567 0.16% 99.33% # Number of insts commited each cycle
-system.cpu3.commit.COM:committed_per_cycle::6 1691 0.49% 99.82% # Number of insts commited each cycle
-system.cpu3.commit.COM:committed_per_cycle::7 39 0.01% 99.83% # Number of insts commited each cycle
-system.cpu3.commit.COM:committed_per_cycle::8 576 0.17% 100.00% # Number of insts commited each cycle
+system.cpu3.commit.COM:committed_per_cycle::0 82996 44.13% 44.13% # Number of insts commited each cycle
+system.cpu3.commit.COM:committed_per_cycle::1 51194 27.22% 71.36% # Number of insts commited each cycle
+system.cpu3.commit.COM:committed_per_cycle::2 7476 3.98% 75.33% # Number of insts commited each cycle
+system.cpu3.commit.COM:committed_per_cycle::3 8061 4.29% 79.62% # Number of insts commited each cycle
+system.cpu3.commit.COM:committed_per_cycle::4 2450 1.30% 80.92% # Number of insts commited each cycle
+system.cpu3.commit.COM:committed_per_cycle::5 34892 18.55% 99.47% # Number of insts commited each cycle
+system.cpu3.commit.COM:committed_per_cycle::6 373 0.20% 99.67% # Number of insts commited each cycle
+system.cpu3.commit.COM:committed_per_cycle::7 129 0.07% 99.74% # Number of insts commited each cycle
+system.cpu3.commit.COM:committed_per_cycle::8 486 0.26% 100.00% # Number of insts commited each cycle
system.cpu3.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu3.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu3.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu3.commit.COM:committed_per_cycle::total 346536 # Number of insts commited each cycle
-system.cpu3.commit.COM:count 132317 # Number of instructions committed
-system.cpu3.commit.COM:loads 32415 # Number of loads committed
-system.cpu3.commit.COM:membars 5314 # Number of memory barriers committed
-system.cpu3.commit.COM:refs 46218 # Number of memory references committed
+system.cpu3.commit.COM:committed_per_cycle::total 188057 # Number of insts commited each cycle
+system.cpu3.commit.COM:count 281618 # Number of instructions committed
+system.cpu3.commit.COM:loads 81766 # Number of loads committed
+system.cpu3.commit.COM:membars 6531 # Number of memory barriers committed
+system.cpu3.commit.COM:refs 119649 # Number of memory references committed
system.cpu3.commit.COM:swp_count 0 # Number of s/w prefetches committed
-system.cpu3.commit.branchMispredicts 32660 # The number of times a branch was mispredicted
-system.cpu3.commit.commitCommittedInsts 132317 # The number of committed instructions
-system.cpu3.commit.commitNonSpecStalls 6025 # The number of times commit has been forced to stall to communicate backwards
-system.cpu3.commit.commitSquashedInsts 152378 # The number of squashed insts skipped by commit
-system.cpu3.committedInsts 111128 # Number of Instructions Simulated
-system.cpu3.committedInsts_total 111128 # Number of Instructions Simulated
-system.cpu3.cpi 3.551805 # CPI: Cycles Per Instruction
-system.cpu3.cpi_total 3.551805 # CPI: Total CPI of All Threads
-system.cpu3.dcache.ReadReq_accesses 28485 # number of ReadReq accesses(hits+misses)
-system.cpu3.dcache.ReadReq_avg_miss_latency 16678.947368 # average ReadReq miss latency
-system.cpu3.dcache.ReadReq_avg_mshr_miss_latency 14832.258065 # average ReadReq mshr miss latency
-system.cpu3.dcache.ReadReq_hits 28295 # number of ReadReq hits
-system.cpu3.dcache.ReadReq_miss_latency 3169000 # number of ReadReq miss cycles
-system.cpu3.dcache.ReadReq_miss_rate 0.006670 # miss rate for ReadReq accesses
-system.cpu3.dcache.ReadReq_misses 190 # number of ReadReq misses
-system.cpu3.dcache.ReadReq_mshr_hits 35 # number of ReadReq MSHR hits
-system.cpu3.dcache.ReadReq_mshr_miss_latency 2299000 # number of ReadReq MSHR miss cycles
-system.cpu3.dcache.ReadReq_mshr_miss_rate 0.005441 # mshr miss rate for ReadReq accesses
-system.cpu3.dcache.ReadReq_mshr_misses 155 # number of ReadReq MSHR misses
-system.cpu3.dcache.SwapReq_accesses 65 # number of SwapReq accesses(hits+misses)
-system.cpu3.dcache.SwapReq_avg_miss_latency 22773.584906 # average SwapReq miss latency
-system.cpu3.dcache.SwapReq_avg_mshr_miss_latency 22782.608696 # average SwapReq mshr miss latency
-system.cpu3.dcache.SwapReq_hits 12 # number of SwapReq hits
-system.cpu3.dcache.SwapReq_miss_latency 1207000 # number of SwapReq miss cycles
-system.cpu3.dcache.SwapReq_miss_rate 0.815385 # miss rate for SwapReq accesses
-system.cpu3.dcache.SwapReq_misses 53 # number of SwapReq misses
-system.cpu3.dcache.SwapReq_mshr_hits 7 # number of SwapReq MSHR hits
-system.cpu3.dcache.SwapReq_mshr_miss_latency 1048000 # number of SwapReq MSHR miss cycles
-system.cpu3.dcache.SwapReq_mshr_miss_rate 0.707692 # mshr miss rate for SwapReq accesses
-system.cpu3.dcache.SwapReq_mshr_misses 46 # number of SwapReq MSHR misses
-system.cpu3.dcache.WriteReq_accesses 13738 # number of WriteReq accesses(hits+misses)
-system.cpu3.dcache.WriteReq_avg_miss_latency 22585.271318 # average WriteReq miss latency
-system.cpu3.dcache.WriteReq_avg_mshr_miss_latency 14535.714286 # average WriteReq mshr miss latency
-system.cpu3.dcache.WriteReq_hits 13609 # number of WriteReq hits
-system.cpu3.dcache.WriteReq_miss_latency 2913500 # number of WriteReq miss cycles
-system.cpu3.dcache.WriteReq_miss_rate 0.009390 # miss rate for WriteReq accesses
-system.cpu3.dcache.WriteReq_misses 129 # number of WriteReq misses
+system.cpu3.commit.branchMispredicts 1107 # The number of times a branch was mispredicted
+system.cpu3.commit.commitCommittedInsts 281618 # The number of committed instructions
+system.cpu3.commit.commitNonSpecStalls 7250 # The number of times commit has been forced to stall to communicate backwards
+system.cpu3.commit.commitSquashedInsts 8574 # The number of squashed insts skipped by commit
+system.cpu3.committedInsts 233925 # Number of Instructions Simulated
+system.cpu3.committedInsts_total 233925 # Number of Instructions Simulated
+system.cpu3.cpi 0.853423 # CPI: Cycles Per Instruction
+system.cpu3.cpi_total 0.853423 # CPI: Total CPI of All Threads
+system.cpu3.dcache.ReadReq_accesses 48473 # number of ReadReq accesses(hits+misses)
+system.cpu3.dcache.ReadReq_avg_miss_latency 22753.504673 # average ReadReq miss latency
+system.cpu3.dcache.ReadReq_avg_mshr_miss_latency 14018.518519 # average ReadReq mshr miss latency
+system.cpu3.dcache.ReadReq_hits 48045 # number of ReadReq hits
+system.cpu3.dcache.ReadReq_miss_latency 9738500 # number of ReadReq miss cycles
+system.cpu3.dcache.ReadReq_miss_rate 0.008830 # miss rate for ReadReq accesses
+system.cpu3.dcache.ReadReq_misses 428 # number of ReadReq misses
+system.cpu3.dcache.ReadReq_mshr_hits 266 # number of ReadReq MSHR hits
+system.cpu3.dcache.ReadReq_mshr_miss_latency 2271000 # number of ReadReq MSHR miss cycles
+system.cpu3.dcache.ReadReq_mshr_miss_rate 0.003342 # mshr miss rate for ReadReq accesses
+system.cpu3.dcache.ReadReq_mshr_misses 162 # number of ReadReq MSHR misses
+system.cpu3.dcache.SwapReq_accesses 73 # number of SwapReq accesses(hits+misses)
+system.cpu3.dcache.SwapReq_avg_miss_latency 25166.666667 # average SwapReq miss latency
+system.cpu3.dcache.SwapReq_avg_mshr_miss_latency 22166.666667 # average SwapReq mshr miss latency
+system.cpu3.dcache.SwapReq_hits 13 # number of SwapReq hits
+system.cpu3.dcache.SwapReq_miss_latency 1510000 # number of SwapReq miss cycles
+system.cpu3.dcache.SwapReq_miss_rate 0.821918 # miss rate for SwapReq accesses
+system.cpu3.dcache.SwapReq_misses 60 # number of SwapReq misses
+system.cpu3.dcache.SwapReq_mshr_miss_latency 1330000 # number of SwapReq MSHR miss cycles
+system.cpu3.dcache.SwapReq_mshr_miss_rate 0.821918 # mshr miss rate for SwapReq accesses
+system.cpu3.dcache.SwapReq_mshr_misses 60 # number of SwapReq MSHR misses
+system.cpu3.dcache.WriteReq_accesses 37810 # number of WriteReq accesses(hits+misses)
+system.cpu3.dcache.WriteReq_avg_miss_latency 24109.243697 # average WriteReq miss latency
+system.cpu3.dcache.WriteReq_avg_mshr_miss_latency 15764.705882 # average WriteReq mshr miss latency
+system.cpu3.dcache.WriteReq_hits 37691 # number of WriteReq hits
+system.cpu3.dcache.WriteReq_miss_latency 2869000 # number of WriteReq miss cycles
+system.cpu3.dcache.WriteReq_miss_rate 0.003147 # miss rate for WriteReq accesses
+system.cpu3.dcache.WriteReq_misses 119 # number of WriteReq misses
system.cpu3.dcache.WriteReq_mshr_hits 17 # number of WriteReq MSHR hits
-system.cpu3.dcache.WriteReq_mshr_miss_latency 1628000 # number of WriteReq MSHR miss cycles
-system.cpu3.dcache.WriteReq_mshr_miss_rate 0.008153 # mshr miss rate for WriteReq accesses
-system.cpu3.dcache.WriteReq_mshr_misses 112 # number of WriteReq MSHR misses
+system.cpu3.dcache.WriteReq_mshr_miss_latency 1608000 # number of WriteReq MSHR miss cycles
+system.cpu3.dcache.WriteReq_mshr_miss_rate 0.002698 # mshr miss rate for WriteReq accesses
+system.cpu3.dcache.WriteReq_mshr_misses 102 # number of WriteReq MSHR misses
system.cpu3.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu3.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu3.dcache.avg_refs 810.166667 # Average number of references to valid blocks.
+system.cpu3.dcache.avg_refs 1503.344828 # Average number of references to valid blocks.
system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu3.dcache.cache_copies 0 # number of cache copies performed
-system.cpu3.dcache.demand_accesses 42223 # number of demand (read+write) accesses
-system.cpu3.dcache.demand_avg_miss_latency 19067.398119 # average overall miss latency
-system.cpu3.dcache.demand_avg_mshr_miss_latency 14707.865169 # average overall mshr miss latency
-system.cpu3.dcache.demand_hits 41904 # number of demand (read+write) hits
-system.cpu3.dcache.demand_miss_latency 6082500 # number of demand (read+write) miss cycles
-system.cpu3.dcache.demand_miss_rate 0.007555 # miss rate for demand accesses
-system.cpu3.dcache.demand_misses 319 # number of demand (read+write) misses
-system.cpu3.dcache.demand_mshr_hits 52 # number of demand (read+write) MSHR hits
-system.cpu3.dcache.demand_mshr_miss_latency 3927000 # number of demand (read+write) MSHR miss cycles
-system.cpu3.dcache.demand_mshr_miss_rate 0.006324 # mshr miss rate for demand accesses
-system.cpu3.dcache.demand_mshr_misses 267 # number of demand (read+write) MSHR misses
+system.cpu3.dcache.demand_accesses 86283 # number of demand (read+write) accesses
+system.cpu3.dcache.demand_avg_miss_latency 23048.446069 # average overall miss latency
+system.cpu3.dcache.demand_avg_mshr_miss_latency 14693.181818 # average overall mshr miss latency
+system.cpu3.dcache.demand_hits 85736 # number of demand (read+write) hits
+system.cpu3.dcache.demand_miss_latency 12607500 # number of demand (read+write) miss cycles
+system.cpu3.dcache.demand_miss_rate 0.006340 # miss rate for demand accesses
+system.cpu3.dcache.demand_misses 547 # number of demand (read+write) misses
+system.cpu3.dcache.demand_mshr_hits 283 # number of demand (read+write) MSHR hits
+system.cpu3.dcache.demand_mshr_miss_latency 3879000 # number of demand (read+write) MSHR miss cycles
+system.cpu3.dcache.demand_mshr_miss_rate 0.003060 # mshr miss rate for demand accesses
+system.cpu3.dcache.demand_mshr_misses 264 # number of demand (read+write) MSHR misses
system.cpu3.dcache.fast_writes 0 # number of fast writes performed
system.cpu3.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu3.dcache.occ_%::0 0.054908 # Average percentage of cache occupancy
-system.cpu3.dcache.occ_%::1 -0.015654 # Average percentage of cache occupancy
-system.cpu3.dcache.occ_blocks::0 28.113086 # Average occupied blocks per context
-system.cpu3.dcache.occ_blocks::1 -8.014642 # Average occupied blocks per context
-system.cpu3.dcache.overall_accesses 42223 # number of overall (read+write) accesses
-system.cpu3.dcache.overall_avg_miss_latency 19067.398119 # average overall miss latency
-system.cpu3.dcache.overall_avg_mshr_miss_latency 14707.865169 # average overall mshr miss latency
+system.cpu3.dcache.occ_%::0 0.049266 # Average percentage of cache occupancy
+system.cpu3.dcache.occ_%::1 -0.015422 # Average percentage of cache occupancy
+system.cpu3.dcache.occ_blocks::0 25.223945 # Average occupied blocks per context
+system.cpu3.dcache.occ_blocks::1 -7.896204 # Average occupied blocks per context
+system.cpu3.dcache.overall_accesses 86283 # number of overall (read+write) accesses
+system.cpu3.dcache.overall_avg_miss_latency 23048.446069 # average overall miss latency
+system.cpu3.dcache.overall_avg_mshr_miss_latency 14693.181818 # average overall mshr miss latency
system.cpu3.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu3.dcache.overall_hits 41904 # number of overall hits
-system.cpu3.dcache.overall_miss_latency 6082500 # number of overall miss cycles
-system.cpu3.dcache.overall_miss_rate 0.007555 # miss rate for overall accesses
-system.cpu3.dcache.overall_misses 319 # number of overall misses
-system.cpu3.dcache.overall_mshr_hits 52 # number of overall MSHR hits
-system.cpu3.dcache.overall_mshr_miss_latency 3927000 # number of overall MSHR miss cycles
-system.cpu3.dcache.overall_mshr_miss_rate 0.006324 # mshr miss rate for overall accesses
-system.cpu3.dcache.overall_mshr_misses 267 # number of overall MSHR misses
+system.cpu3.dcache.overall_hits 85736 # number of overall hits
+system.cpu3.dcache.overall_miss_latency 12607500 # number of overall miss cycles
+system.cpu3.dcache.overall_miss_rate 0.006340 # miss rate for overall accesses
+system.cpu3.dcache.overall_misses 547 # number of overall misses
+system.cpu3.dcache.overall_mshr_hits 283 # number of overall MSHR hits
+system.cpu3.dcache.overall_mshr_miss_latency 3879000 # number of overall MSHR miss cycles
+system.cpu3.dcache.overall_mshr_miss_rate 0.003060 # mshr miss rate for overall accesses
+system.cpu3.dcache.overall_mshr_misses 264 # number of overall MSHR misses
system.cpu3.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu3.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu3.dcache.replacements 2 # number of replacements
-system.cpu3.dcache.sampled_refs 30 # Sample count of references to valid blocks.
+system.cpu3.dcache.sampled_refs 29 # Sample count of references to valid blocks.
system.cpu3.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu3.dcache.tagsinuse 20.098444 # Cycle average of tags in use
-system.cpu3.dcache.total_refs 24305 # Total number of references to valid blocks.
+system.cpu3.dcache.tagsinuse 17.327741 # Cycle average of tags in use
+system.cpu3.dcache.total_refs 43597 # Total number of references to valid blocks.
system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu3.dcache.writebacks 1 # number of writebacks
-system.cpu3.decode.DECODE:BlockedCycles 35593 # Number of cycles decode is blocked
-system.cpu3.decode.DECODE:DecodedInsts 394229 # Number of instructions handled by decode
-system.cpu3.decode.DECODE:IdleCycles 164873 # Number of cycles decode is idle
-system.cpu3.decode.DECODE:RunCycles 145919 # Number of cycles decode is running
-system.cpu3.decode.DECODE:SquashCycles 36967 # Number of cycles decode is squashing
-system.cpu3.decode.DECODE:UnblockCycles 151 # Number of cycles decode is unblocking
-system.cpu3.fetch.Branches 82266 # Number of branches that fetch encountered
-system.cpu3.fetch.CacheLines 80954 # Number of cache lines fetched
-system.cpu3.fetch.Cycles 235714 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu3.fetch.IcacheSquashes 12405 # Number of outstanding Icache misses that were squashed
-system.cpu3.fetch.Insts 435938 # Number of instructions fetch has processed
-system.cpu3.fetch.SquashCycles 32818 # Number of cycles fetch has spent squashing
-system.cpu3.fetch.branchRate 0.208424 # Number of branch fetches per cycle
-system.cpu3.fetch.icacheStallCycles 80954 # Number of cycles fetch is stalled on an Icache miss
-system.cpu3.fetch.predictedBranches 48405 # Number of branches that fetch has predicted taken
-system.cpu3.fetch.rate 1.104465 # Number of inst fetches per cycle
-system.cpu3.fetch.rateDist::samples 392184 # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::mean 1.111565 # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::stdev 2.082267 # Number of instructions fetched each cycle (Total)
+system.cpu3.decode.DECODE:BlockedCycles 21716 # Number of cycles decode is blocked
+system.cpu3.decode.DECODE:DecodedInsts 294261 # Number of instructions handled by decode
+system.cpu3.decode.DECODE:IdleCycles 57777 # Number of cycles decode is idle
+system.cpu3.decode.DECODE:RunCycles 102518 # Number of cycles decode is running
+system.cpu3.decode.DECODE:SquashCycles 1820 # Number of cycles decode is squashing
+system.cpu3.decode.DECODE:UnblockCycles 6046 # Number of cycles decode is unblocking
+system.cpu3.fetch.Branches 53282 # Number of branches that fetch encountered
+system.cpu3.fetch.CacheLines 21872 # Number of cache lines fetched
+system.cpu3.fetch.Cycles 130835 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu3.fetch.IcacheSquashes 221 # Number of outstanding Icache misses that were squashed
+system.cpu3.fetch.Insts 295412 # Number of instructions fetch has processed
+system.cpu3.fetch.SquashCycles 1181 # Number of cycles fetch has spent squashing
+system.cpu3.fetch.branchRate 0.266894 # Number of branch fetches per cycle
+system.cpu3.fetch.icacheStallCycles 21872 # Number of cycles fetch is stalled on an Icache miss
+system.cpu3.fetch.predictedBranches 51000 # Number of branches that fetch has predicted taken
+system.cpu3.fetch.rate 1.479746 # Number of inst fetches per cycle
+system.cpu3.fetch.rateDist::samples 196481 # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::mean 1.503514 # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::stdev 2.005027 # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::0 237449 60.55% 60.55% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::1 82939 21.15% 81.69% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::2 12394 3.16% 84.85% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::3 15941 4.06% 88.92% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::4 2706 0.69% 89.61% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::5 16830 4.29% 93.90% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::6 1787 0.46% 94.36% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::7 2412 0.62% 94.97% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::8 19726 5.03% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::0 87542 44.55% 44.55% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::1 56519 28.77% 73.32% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::2 7661 3.90% 77.22% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::3 2862 1.46% 78.68% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::4 1914 0.97% 79.65% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::5 35774 18.21% 97.86% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::6 2478 1.26% 99.12% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::7 257 0.13% 99.25% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::8 1474 0.75% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::total 392184 # Number of instructions fetched each cycle (Total)
-system.cpu3.icache.ReadReq_accesses 80954 # number of ReadReq accesses(hits+misses)
-system.cpu3.icache.ReadReq_avg_miss_latency 13933.423913 # average ReadReq miss latency
-system.cpu3.icache.ReadReq_avg_mshr_miss_latency 11485.915493 # average ReadReq mshr miss latency
-system.cpu3.icache.ReadReq_hits 80218 # number of ReadReq hits
-system.cpu3.icache.ReadReq_miss_latency 10255000 # number of ReadReq miss cycles
-system.cpu3.icache.ReadReq_miss_rate 0.009092 # miss rate for ReadReq accesses
-system.cpu3.icache.ReadReq_misses 736 # number of ReadReq misses
-system.cpu3.icache.ReadReq_mshr_hits 97 # number of ReadReq MSHR hits
-system.cpu3.icache.ReadReq_mshr_miss_latency 7339500 # number of ReadReq MSHR miss cycles
-system.cpu3.icache.ReadReq_mshr_miss_rate 0.007893 # mshr miss rate for ReadReq accesses
-system.cpu3.icache.ReadReq_mshr_misses 639 # number of ReadReq MSHR misses
+system.cpu3.fetch.rateDist::total 196481 # Number of instructions fetched each cycle (Total)
+system.cpu3.icache.ReadReq_accesses 21872 # number of ReadReq accesses(hits+misses)
+system.cpu3.icache.ReadReq_avg_miss_latency 14323.590814 # average ReadReq miss latency
+system.cpu3.icache.ReadReq_avg_mshr_miss_latency 11652.370203 # average ReadReq mshr miss latency
+system.cpu3.icache.ReadReq_hits 21393 # number of ReadReq hits
+system.cpu3.icache.ReadReq_miss_latency 6861000 # number of ReadReq miss cycles
+system.cpu3.icache.ReadReq_miss_rate 0.021900 # miss rate for ReadReq accesses
+system.cpu3.icache.ReadReq_misses 479 # number of ReadReq misses
+system.cpu3.icache.ReadReq_mshr_hits 36 # number of ReadReq MSHR hits
+system.cpu3.icache.ReadReq_mshr_miss_latency 5162000 # number of ReadReq MSHR miss cycles
+system.cpu3.icache.ReadReq_mshr_miss_rate 0.020254 # mshr miss rate for ReadReq accesses
+system.cpu3.icache.ReadReq_mshr_misses 443 # number of ReadReq MSHR misses
system.cpu3.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu3.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu3.icache.avg_refs 125.536776 # Average number of references to valid blocks.
+system.cpu3.icache.avg_refs 48.291196 # Average number of references to valid blocks.
system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu3.icache.cache_copies 0 # number of cache copies performed
-system.cpu3.icache.demand_accesses 80954 # number of demand (read+write) accesses
-system.cpu3.icache.demand_avg_miss_latency 13933.423913 # average overall miss latency
-system.cpu3.icache.demand_avg_mshr_miss_latency 11485.915493 # average overall mshr miss latency
-system.cpu3.icache.demand_hits 80218 # number of demand (read+write) hits
-system.cpu3.icache.demand_miss_latency 10255000 # number of demand (read+write) miss cycles
-system.cpu3.icache.demand_miss_rate 0.009092 # miss rate for demand accesses
-system.cpu3.icache.demand_misses 736 # number of demand (read+write) misses
-system.cpu3.icache.demand_mshr_hits 97 # number of demand (read+write) MSHR hits
-system.cpu3.icache.demand_mshr_miss_latency 7339500 # number of demand (read+write) MSHR miss cycles
-system.cpu3.icache.demand_mshr_miss_rate 0.007893 # mshr miss rate for demand accesses
-system.cpu3.icache.demand_mshr_misses 639 # number of demand (read+write) MSHR misses
+system.cpu3.icache.demand_accesses 21872 # number of demand (read+write) accesses
+system.cpu3.icache.demand_avg_miss_latency 14323.590814 # average overall miss latency
+system.cpu3.icache.demand_avg_mshr_miss_latency 11652.370203 # average overall mshr miss latency
+system.cpu3.icache.demand_hits 21393 # number of demand (read+write) hits
+system.cpu3.icache.demand_miss_latency 6861000 # number of demand (read+write) miss cycles
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+system.cpu3.icache.demand_mshr_miss_latency 5162000 # number of demand (read+write) MSHR miss cycles
+system.cpu3.icache.demand_mshr_miss_rate 0.020254 # mshr miss rate for demand accesses
+system.cpu3.icache.demand_mshr_misses 443 # number of demand (read+write) MSHR misses
system.cpu3.icache.fast_writes 0 # number of fast writes performed
system.cpu3.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu3.icache.occ_%::0 0.189077 # Average percentage of cache occupancy
-system.cpu3.icache.occ_blocks::0 96.807549 # Average occupied blocks per context
-system.cpu3.icache.overall_accesses 80954 # number of overall (read+write) accesses
-system.cpu3.icache.overall_avg_miss_latency 13933.423913 # average overall miss latency
-system.cpu3.icache.overall_avg_mshr_miss_latency 11485.915493 # average overall mshr miss latency
+system.cpu3.icache.occ_%::0 0.173082 # Average percentage of cache occupancy
+system.cpu3.icache.occ_blocks::0 88.617750 # Average occupied blocks per context
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system.cpu3.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu3.icache.overall_hits 80218 # number of overall hits
-system.cpu3.icache.overall_miss_latency 10255000 # number of overall miss cycles
-system.cpu3.icache.overall_miss_rate 0.009092 # miss rate for overall accesses
-system.cpu3.icache.overall_misses 736 # number of overall misses
-system.cpu3.icache.overall_mshr_hits 97 # number of overall MSHR hits
-system.cpu3.icache.overall_mshr_miss_latency 7339500 # number of overall MSHR miss cycles
-system.cpu3.icache.overall_mshr_miss_rate 0.007893 # mshr miss rate for overall accesses
-system.cpu3.icache.overall_mshr_misses 639 # number of overall MSHR misses
+system.cpu3.icache.overall_hits 21393 # number of overall hits
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system.cpu3.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu3.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu3.icache.replacements 527 # number of replacements
-system.cpu3.icache.sampled_refs 639 # Sample count of references to valid blocks.
+system.cpu3.icache.replacements 331 # number of replacements
+system.cpu3.icache.sampled_refs 443 # Sample count of references to valid blocks.
system.cpu3.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu3.icache.tagsinuse 96.807549 # Cycle average of tags in use
-system.cpu3.icache.total_refs 80218 # Total number of references to valid blocks.
+system.cpu3.icache.tagsinuse 88.617750 # Cycle average of tags in use
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system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu3.icache.writebacks 0 # number of writebacks
-system.cpu3.idleCycles 2521 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu3.iew.EXEC:branches 39408 # Number of branches executed
-system.cpu3.iew.EXEC:nop 47237 # number of nop insts executed
-system.cpu3.iew.EXEC:rate 0.449837 # Inst execution rate
-system.cpu3.iew.EXEC:refs 53769 # number of memory reference insts executed
-system.cpu3.iew.EXEC:stores 15425 # Number of stores executed
+system.cpu3.idleCycles 3156 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu3.iew.EXEC:branches 50931 # Number of branches executed
+system.cpu3.iew.EXEC:nop 42039 # number of nop insts executed
+system.cpu3.iew.EXEC:rate 1.222935 # Inst execution rate
+system.cpu3.iew.EXEC:refs 120716 # number of memory reference insts executed
+system.cpu3.iew.EXEC:stores 38219 # Number of stores executed
system.cpu3.iew.EXEC:swp 0 # number of swp insts executed
-system.cpu3.iew.WB:consumers 88234 # num instructions consuming a value
-system.cpu3.iew.WB:count 173934 # cumulative count of insts written-back
-system.cpu3.iew.WB:fanout 0.937246 # average fanout of values written-back
+system.cpu3.iew.WB:consumers 140772 # num instructions consuming a value
+system.cpu3.iew.WB:count 243777 # cumulative count of insts written-back
+system.cpu3.iew.WB:fanout 0.974072 # average fanout of values written-back
system.cpu3.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu3.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu3.iew.WB:producers 82697 # num instructions producing a value
-system.cpu3.iew.WB:rate 0.440668 # insts written-back per cycle
-system.cpu3.iew.WB:sent 174194 # cumulative count of insts sent to commit
-system.cpu3.iew.branchMispredicts 33269 # Number of branch mispredicts detected at execute
-system.cpu3.iew.iewBlockCycles 0 # Number of cycles IEW is blocking
-system.cpu3.iew.iewDispLoadInsts 43341 # Number of dispatched load instructions
-system.cpu3.iew.iewDispNonSpecInsts 11749 # Number of dispatched non-speculative instructions
-system.cpu3.iew.iewDispSquashedInsts 3545 # Number of squashed instructions skipped by dispatch
-system.cpu3.iew.iewDispStoreInsts 27172 # Number of dispatched store instructions
-system.cpu3.iew.iewDispatchedInsts 284714 # Number of instructions dispatched to IQ
-system.cpu3.iew.iewExecLoadInsts 38344 # Number of load instructions executed
-system.cpu3.iew.iewExecSquashedInsts 36975 # Number of squashed instructions skipped in execute
-system.cpu3.iew.iewExecutedInsts 177553 # Number of executed instructions
-system.cpu3.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
+system.cpu3.iew.WB:producers 137122 # num instructions producing a value
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+system.cpu3.iew.WB:sent 243910 # cumulative count of insts sent to commit
+system.cpu3.iew.branchMispredicts 1214 # Number of branch mispredicts detected at execute
+system.cpu3.iew.iewBlockCycles 1676 # Number of cycles IEW is blocking
+system.cpu3.iew.iewDispLoadInsts 83353 # Number of dispatched load instructions
+system.cpu3.iew.iewDispNonSpecInsts 943 # Number of dispatched non-speculative instructions
+system.cpu3.iew.iewDispSquashedInsts 577 # Number of squashed instructions skipped by dispatch
+system.cpu3.iew.iewDispStoreInsts 38642 # Number of dispatched store instructions
+system.cpu3.iew.iewDispatchedInsts 290221 # Number of instructions dispatched to IQ
+system.cpu3.iew.iewExecLoadInsts 82497 # Number of load instructions executed
+system.cpu3.iew.iewExecSquashedInsts 962 # Number of squashed instructions skipped in execute
+system.cpu3.iew.iewExecutedInsts 244143 # Number of executed instructions
+system.cpu3.iew.iewIQFullEvents 55 # Number of times the IQ has become full, causing a stall
system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
-system.cpu3.iew.iewSquashCycles 36967 # Number of cycles IEW is squashing
-system.cpu3.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking
+system.cpu3.iew.iewSquashCycles 1820 # Number of cycles IEW is squashing
+system.cpu3.iew.iewUnblockCycles 60 # Number of cycles IEW is unblocking
system.cpu3.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu3.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
-system.cpu3.iew.lsq.thread.0.forwLoads 9839 # Number of loads that had data forwarded from stores
-system.cpu3.iew.lsq.thread.0.ignoredResponses 11 # Number of memory responses ignored because the instruction is squashed
+system.cpu3.iew.lsq.thread.0.forwLoads 34006 # Number of loads that had data forwarded from stores
+system.cpu3.iew.lsq.thread.0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed
system.cpu3.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu3.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu3.iew.lsq.thread.0.memOrderViolation 701 # Number of memory ordering violations
+system.cpu3.iew.lsq.thread.0.memOrderViolation 33 # Number of memory ordering violations
system.cpu3.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled
-system.cpu3.iew.lsq.thread.0.squashedLoads 10926 # Number of loads squashed
-system.cpu3.iew.lsq.thread.0.squashedStores 13369 # Number of stores squashed
-system.cpu3.iew.memOrderViolationEvents 701 # Number of memory order violations
-system.cpu3.iew.predictedNotTakenIncorrect 1030 # Number of branches that were predicted not taken incorrectly
-system.cpu3.iew.predictedTakenIncorrect 32239 # Number of branches that were predicted taken incorrectly
-system.cpu3.ipc 0.281547 # IPC: Instructions Per Cycle
-system.cpu3.ipc_total 0.281547 # IPC: Total IPC of All Threads
+system.cpu3.iew.lsq.thread.0.squashedLoads 1587 # Number of loads squashed
+system.cpu3.iew.lsq.thread.0.squashedStores 759 # Number of stores squashed
+system.cpu3.iew.memOrderViolationEvents 33 # Number of memory order violations
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+system.cpu3.iew.predictedTakenIncorrect 1023 # Number of branches that were predicted taken incorrectly
+system.cpu3.ipc 1.171752 # IPC: Instructions Per Cycle
+system.cpu3.ipc_total 1.171752 # IPC: Total IPC of All Threads
system.cpu3.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu3.iq.ISSUE:FU_type_0::IntAlu 153538 71.57% 71.57% # Type of FU issued
-system.cpu3.iq.ISSUE:FU_type_0::IntMult 0 0.00% 71.57% # Type of FU issued
-system.cpu3.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 71.57% # Type of FU issued
-system.cpu3.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 71.57% # Type of FU issued
-system.cpu3.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 71.57% # Type of FU issued
-system.cpu3.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 71.57% # Type of FU issued
-system.cpu3.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 71.57% # Type of FU issued
-system.cpu3.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 71.57% # Type of FU issued
-system.cpu3.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 71.57% # Type of FU issued
-system.cpu3.iq.ISSUE:FU_type_0::MemRead 44868 20.91% 92.48% # Type of FU issued
-system.cpu3.iq.ISSUE:FU_type_0::MemWrite 16122 7.52% 100.00% # Type of FU issued
+system.cpu3.iq.ISSUE:FU_type_0::IntAlu 117646 48.00% 48.00% # Type of FU issued
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system.cpu3.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu3.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu3.iq.ISSUE:FU_type_0::total 214528 # Type of FU issued
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-system.cpu3.iq.ISSUE:fu_busy_rate 0.000867 # FU busy rate (busy events/executed inst)
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system.cpu3.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu3.iq.ISSUE:fu_full::IntAlu 24 12.90% 12.90% # attempts to use FU when none available
-system.cpu3.iq.ISSUE:fu_full::IntMult 0 0.00% 12.90% # attempts to use FU when none available
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-system.cpu3.iq.ISSUE:fu_full::FloatAdd 0 0.00% 12.90% # attempts to use FU when none available
-system.cpu3.iq.ISSUE:fu_full::FloatCmp 0 0.00% 12.90% # attempts to use FU when none available
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-system.cpu3.iq.ISSUE:fu_full::FloatMult 0 0.00% 12.90% # attempts to use FU when none available
-system.cpu3.iq.ISSUE:fu_full::FloatDiv 0 0.00% 12.90% # attempts to use FU when none available
-system.cpu3.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 12.90% # attempts to use FU when none available
-system.cpu3.iq.ISSUE:fu_full::MemRead 17 9.14% 22.04% # attempts to use FU when none available
-system.cpu3.iq.ISSUE:fu_full::MemWrite 145 77.96% 100.00% # attempts to use FU when none available
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system.cpu3.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu3.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
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system.cpu3.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
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-system.cpu3.iq.ISSUE:issued_per_cycle::1 66150 16.87% 85.84% # Number of insts issued each cycle
-system.cpu3.iq.ISSUE:issued_per_cycle::2 30383 7.75% 93.58% # Number of insts issued each cycle
-system.cpu3.iq.ISSUE:issued_per_cycle::3 16859 4.30% 97.88% # Number of insts issued each cycle
-system.cpu3.iq.ISSUE:issued_per_cycle::4 5420 1.38% 99.26% # Number of insts issued each cycle
-system.cpu3.iq.ISSUE:issued_per_cycle::5 2202 0.56% 99.83% # Number of insts issued each cycle
-system.cpu3.iq.ISSUE:issued_per_cycle::6 491 0.13% 99.95% # Number of insts issued each cycle
-system.cpu3.iq.ISSUE:issued_per_cycle::7 161 0.04% 99.99% # Number of insts issued each cycle
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system.cpu3.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu3.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu3.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu3.iq.ISSUE:issued_per_cycle::total 392184 # Number of insts issued each cycle
-system.cpu3.iq.ISSUE:rate 0.543515 # Inst issue rate
-system.cpu3.iq.iqInstsAdded 219886 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu3.iq.iqInstsIssued 214528 # Number of instructions issued
-system.cpu3.iq.iqNonSpecInstsAdded 17591 # Number of non-speculative instructions added to the IQ
-system.cpu3.iq.iqSquashedInstsExamined 86635 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu3.iq.iqSquashedInstsIssued 4 # Number of squashed instructions issued
-system.cpu3.iq.iqSquashedNonSpecRemoved 11566 # Number of squashed non-spec instructions that were removed
-system.cpu3.iq.iqSquashedOperandsExamined 36678 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu3.memDep0.conflictingLoads 10938 # Number of conflicting loads.
-system.cpu3.memDep0.conflictingStores 96 # Number of conflicting stores.
-system.cpu3.memDep0.insertedLoads 43341 # Number of loads inserted to the mem dependence unit.
-system.cpu3.memDep0.insertedStores 27172 # Number of stores inserted to the mem dependence unit.
-system.cpu3.numCycles 394705 # number of cpu cycles simulated
-system.cpu3.rename.RENAME:CommittedMaps 94626 # Number of HB maps that are committed
-system.cpu3.rename.RENAME:IdleCycles 180043 # Number of cycles rename is idle
-system.cpu3.rename.RENAME:LSQFullEvents 1 # Number of times rename has blocked due to LSQ full
-system.cpu3.rename.RENAME:RenameLookups 494732 # Number of register rename lookups that rename has made
-system.cpu3.rename.RENAME:RenamedInsts 312015 # Number of instructions processed by rename
-system.cpu3.rename.RENAME:RenamedOperands 231166 # Number of destination operands rename has renamed
-system.cpu3.rename.RENAME:RunCycles 130989 # Number of cycles rename is running
-system.cpu3.rename.RENAME:SquashCycles 36967 # Number of cycles rename is squashing
-system.cpu3.rename.RENAME:UnblockCycles 619 # Number of cycles rename is unblocking
-system.cpu3.rename.RENAME:UndoneMaps 136540 # Number of HB maps that are undone due to squashing
-system.cpu3.rename.RENAME:serializeStallCycles 34885 # count of cycles rename stalled for serializing inst
-system.cpu3.rename.RENAME:serializingInsts 11999 # count of serializing insts renamed
-system.cpu3.rename.RENAME:skidInsts 46061 # count of insts added to the skid buffer
-system.cpu3.rename.RENAME:tempSerializingInsts 12120 # count of temporary serializing insts renamed
-system.cpu3.timesIdled 278 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu3.iq.ISSUE:issued_per_cycle::total 196481 # Number of insts issued each cycle
+system.cpu3.iq.ISSUE:rate 1.227753 # Inst issue rate
+system.cpu3.iq.iqInstsAdded 240238 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu3.iq.iqInstsIssued 245105 # Number of instructions issued
+system.cpu3.iq.iqNonSpecInstsAdded 7944 # Number of non-speculative instructions added to the IQ
+system.cpu3.iq.iqSquashedInstsExamined 6797 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu3.iq.iqSquashedInstsIssued 1 # Number of squashed instructions issued
+system.cpu3.iq.iqSquashedNonSpecRemoved 694 # Number of squashed non-spec instructions that were removed
+system.cpu3.iq.iqSquashedOperandsExamined 6548 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu3.memDep0.conflictingLoads 41135 # Number of conflicting loads.
+system.cpu3.memDep0.conflictingStores 34159 # Number of conflicting stores.
+system.cpu3.memDep0.insertedLoads 83353 # Number of loads inserted to the mem dependence unit.
+system.cpu3.memDep0.insertedStores 38642 # Number of stores inserted to the mem dependence unit.
+system.cpu3.numCycles 199637 # number of cpu cycles simulated
+system.cpu3.rename.RENAME:BlockCycles 7787 # Number of cycles rename is blocking
+system.cpu3.rename.RENAME:CommittedMaps 192127 # Number of HB maps that are committed
+system.cpu3.rename.RENAME:IQFullEvents 59 # Number of times rename has blocked due to IQ full
+system.cpu3.rename.RENAME:IdleCycles 58403 # Number of cycles rename is idle
+system.cpu3.rename.RENAME:LSQFullEvents 39 # Number of times rename has blocked due to LSQ full
+system.cpu3.rename.RENAME:RenameLookups 554400 # Number of register rename lookups that rename has made
+system.cpu3.rename.RENAME:RenamedInsts 292478 # Number of instructions processed by rename
+system.cpu3.rename.RENAME:RenamedOperands 200449 # Number of destination operands rename has renamed
+system.cpu3.rename.RENAME:RunCycles 108083 # Number of cycles rename is running
+system.cpu3.rename.RENAME:SquashCycles 1820 # Number of cycles rename is squashing
+system.cpu3.rename.RENAME:UnblockCycles 588 # Number of cycles rename is unblocking
+system.cpu3.rename.RENAME:UndoneMaps 8322 # Number of HB maps that are undone due to squashing
+system.cpu3.rename.RENAME:serializeStallCycles 13196 # count of cycles rename stalled for serializing inst
+system.cpu3.rename.RENAME:serializingInsts 964 # count of serializing insts renamed
+system.cpu3.rename.RENAME:skidInsts 2784 # count of insts added to the skid buffer
+system.cpu3.rename.RENAME:tempSerializingInsts 1016 # count of temporary serializing insts renamed
+system.cpu3.timesIdled 293 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.l2c.ReadExReq_accesses::0 94 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::1 12 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::2 13 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::3 12 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 131 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_avg_miss_latency::0 73117.021277 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::1 572750 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::2 528692.307692 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::3 572750 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 1747309.328969 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency 40309.160305 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_miss_latency 6873000 # number of ReadExReq miss cycles
+system.l2c.ReadExReq_avg_miss_latency::0 73191.489362 # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::1 573333.333333 # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::2 529230.769231 # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::3 573333.333333 # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 1749088.925259 # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency 40335.877863 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_miss_latency 6880000 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_rate::0 1 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::1 1 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::2 1 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_misses::2 13 # number of ReadExReq misses
system.l2c.ReadExReq_misses::3 12 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 131 # number of ReadExReq misses
-system.l2c.ReadExReq_mshr_miss_latency 5280500 # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency 5284000 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_rate::0 1.393617 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::1 10.916667 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::2 10.076923 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::3 10.916667 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 33.303873 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_misses 131 # number of ReadExReq MSHR misses
-system.l2c.ReadReq_accesses::0 751 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::1 650 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::2 646 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::3 653 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total 2700 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_avg_miss_latency::0 63452.850877 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::1 2225730.769231 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::2 361681.250000 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::3 4822416.666667 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 7473281.536775 # average ReadReq miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency 39996.370236 # average ReadReq mshr miss latency
-system.l2c.ReadReq_hits::0 295 # number of ReadReq hits
-system.l2c.ReadReq_hits::1 637 # number of ReadReq hits
-system.l2c.ReadReq_hits::2 566 # number of ReadReq hits
-system.l2c.ReadReq_hits::3 647 # number of ReadReq hits
-system.l2c.ReadReq_hits::total 2145 # number of ReadReq hits
-system.l2c.ReadReq_miss_latency 28934500 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_rate::0 0.607190 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::1 0.020000 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::2 0.123839 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::3 0.009188 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total 0.760218 # miss rate for ReadReq accesses
-system.l2c.ReadReq_misses::0 456 # number of ReadReq misses
-system.l2c.ReadReq_misses::1 13 # number of ReadReq misses
-system.l2c.ReadReq_misses::2 80 # number of ReadReq misses
-system.l2c.ReadReq_misses::3 6 # number of ReadReq misses
-system.l2c.ReadReq_misses::total 555 # number of ReadReq misses
-system.l2c.ReadReq_mshr_hits 4 # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_miss_latency 22038000 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_rate::0 0.733688 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::1 0.847692 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::2 0.852941 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::3 0.843798 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total 3.278120 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_misses 551 # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_accesses::0 31 # number of UpgradeReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::0 689 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::1 459 # number of ReadReq accesses(hits+misses)
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+system.l2c.ReadReq_accesses::3 456 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total 2060 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_avg_miss_latency::0 63650.334076 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::1 2381583.333333 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::2 340226.190476 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::3 5715800 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 8501259.857885 # average ReadReq miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency 40001.841621 # average ReadReq mshr miss latency
+system.l2c.ReadReq_hits::0 240 # number of ReadReq hits
+system.l2c.ReadReq_hits::1 447 # number of ReadReq hits
+system.l2c.ReadReq_hits::2 372 # number of ReadReq hits
+system.l2c.ReadReq_hits::3 451 # number of ReadReq hits
+system.l2c.ReadReq_hits::total 1510 # number of ReadReq hits
+system.l2c.ReadReq_miss_latency 28579000 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_rate::0 0.651669 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::1 0.026144 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::2 0.184211 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::3 0.010965 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total 0.872988 # miss rate for ReadReq accesses
+system.l2c.ReadReq_misses::0 449 # number of ReadReq misses
+system.l2c.ReadReq_misses::1 12 # number of ReadReq misses
+system.l2c.ReadReq_misses::2 84 # number of ReadReq misses
+system.l2c.ReadReq_misses::3 5 # number of ReadReq misses
+system.l2c.ReadReq_misses::total 550 # number of ReadReq misses
+system.l2c.ReadReq_mshr_hits 7 # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_miss_latency 21721000 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_rate::0 0.788099 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::1 1.183007 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::2 1.190789 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::3 1.190789 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total 4.352684 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_misses 543 # number of ReadReq MSHR misses
+system.l2c.UpgradeReq_accesses::0 29 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::1 21 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::2 21 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::3 22 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total 95 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_avg_miss_latency::0 5625 # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::1 7500 # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::2 7500 # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::3 7159.090909 # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total 27784.090909 # average UpgradeReq miss latency
+system.l2c.UpgradeReq_accesses::2 25 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::3 23 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total 98 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_avg_miss_latency::0 6000 # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::1 7428.571429 # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::2 6240 # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::3 6782.608696 # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total 26451.180124 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_hits::0 3 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 3 # number of UpgradeReq hits
-system.l2c.UpgradeReq_miss_latency 157500 # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_rate::0 0.903226 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_latency 156000 # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_rate::0 0.896552 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::1 1 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::2 1 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::3 1 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total 3.903226 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_misses::0 28 # number of UpgradeReq misses
+system.l2c.UpgradeReq_miss_rate::total 3.896552 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_misses::0 26 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::1 21 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::2 21 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::3 22 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total 92 # number of UpgradeReq misses
-system.l2c.UpgradeReq_mshr_miss_latency 3680000 # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_rate::0 2.967742 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::1 4.380952 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::2 4.380952 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::3 4.181818 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total 15.911465 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_misses 92 # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_misses::2 25 # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::3 23 # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total 95 # number of UpgradeReq misses
+system.l2c.UpgradeReq_mshr_miss_latency 3800000 # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_rate::0 3.275862 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::1 4.523810 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::2 3.800000 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::3 4.130435 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total 15.730106 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_misses 95 # number of UpgradeReq MSHR misses
system.l2c.Writeback_accesses::0 9 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 9 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_hits::0 9 # number of Writeback hits
system.l2c.Writeback_hits::total 9 # number of Writeback hits
system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.l2c.avg_refs 3.873418 # Average number of references to valid blocks.
+system.l2c.avg_refs 2.765138 # Average number of references to valid blocks.
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.cache_copies 0 # number of cache copies performed
-system.l2c.demand_accesses::0 845 # number of demand (read+write) accesses
-system.l2c.demand_accesses::1 662 # number of demand (read+write) accesses
-system.l2c.demand_accesses::2 659 # number of demand (read+write) accesses
-system.l2c.demand_accesses::3 665 # number of demand (read+write) accesses
-system.l2c.demand_accesses::total 2831 # number of demand (read+write) accesses
-system.l2c.demand_avg_miss_latency::0 65104.545455 # average overall miss latency
-system.l2c.demand_avg_miss_latency::1 1432300 # average overall miss latency
-system.l2c.demand_avg_miss_latency::2 385026.881720 # average overall miss latency
-system.l2c.demand_avg_miss_latency::3 1989305.555556 # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 3871736.982731 # average overall miss latency
-system.l2c.demand_avg_mshr_miss_latency 40056.451613 # average overall mshr miss latency
-system.l2c.demand_hits::0 295 # number of demand (read+write) hits
-system.l2c.demand_hits::1 637 # number of demand (read+write) hits
-system.l2c.demand_hits::2 566 # number of demand (read+write) hits
-system.l2c.demand_hits::3 647 # number of demand (read+write) hits
-system.l2c.demand_hits::total 2145 # number of demand (read+write) hits
-system.l2c.demand_miss_latency 35807500 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_rate::0 0.650888 # miss rate for demand accesses
-system.l2c.demand_miss_rate::1 0.037764 # miss rate for demand accesses
-system.l2c.demand_miss_rate::2 0.141123 # miss rate for demand accesses
-system.l2c.demand_miss_rate::3 0.027068 # miss rate for demand accesses
-system.l2c.demand_miss_rate::total 0.856843 # miss rate for demand accesses
-system.l2c.demand_misses::0 550 # number of demand (read+write) misses
-system.l2c.demand_misses::1 25 # number of demand (read+write) misses
-system.l2c.demand_misses::2 93 # number of demand (read+write) misses
-system.l2c.demand_misses::3 18 # number of demand (read+write) misses
-system.l2c.demand_misses::total 686 # number of demand (read+write) misses
-system.l2c.demand_mshr_hits 4 # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_miss_latency 27318500 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_rate::0 0.807101 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::1 1.030211 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::2 1.034901 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::3 1.025564 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total 3.897777 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_misses 682 # number of demand (read+write) MSHR misses
+system.l2c.demand_accesses::0 783 # number of demand (read+write) accesses
+system.l2c.demand_accesses::1 471 # number of demand (read+write) accesses
+system.l2c.demand_accesses::2 469 # number of demand (read+write) accesses
+system.l2c.demand_accesses::3 468 # number of demand (read+write) accesses
+system.l2c.demand_accesses::total 2191 # number of demand (read+write) accesses
+system.l2c.demand_avg_miss_latency::0 65302.025783 # average overall miss latency
+system.l2c.demand_avg_miss_latency::1 1477458.333333 # average overall miss latency
+system.l2c.demand_avg_miss_latency::2 365556.701031 # average overall miss latency
+system.l2c.demand_avg_miss_latency::3 2085823.529412 # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 3994140.589559 # average overall miss latency
+system.l2c.demand_avg_mshr_miss_latency 40066.765579 # average overall mshr miss latency
+system.l2c.demand_hits::0 240 # number of demand (read+write) hits
+system.l2c.demand_hits::1 447 # number of demand (read+write) hits
+system.l2c.demand_hits::2 372 # number of demand (read+write) hits
+system.l2c.demand_hits::3 451 # number of demand (read+write) hits
+system.l2c.demand_hits::total 1510 # number of demand (read+write) hits
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projects / gem5.git / commitdiff