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diff --git a/openpower/sv/rfc/ls001.mdwn b/openpower/sv/rfc/ls001.mdwn
index 7e841b516d53564b4e086aab7bd2fcfb536b2a53..19a23febd2531a6c024a8520ad5be014dfd7be12 100644 (file)
--- a/openpower/sv/rfc/ls001.mdwn
+++ b/openpower/sv/rfc/ls001.mdwn
@@ -61,12 +61,25 @@ they are all required
 # Simple-V Resources
 
 * No new Interrupt types are required.
-* Register numbers are extended to 128 (including CR Fields).
+* GPR FPR and CR Field Register numbers are extended to 128.
   A future version may extend to 256 or beyond [^extend]
+* (A future version or other Stakeholder *may* wish to drop Simple-V
+  onto VSX: extension of the number of VSX registers will be discussed at that
+  time)
 * 24-bits are needed within the main SVP64 Prefix (equivalent to a 2-bit XO)
 * Another 24-bit (a second 2-bit XO) is needed for a planned future encoding, currently
   named "SVP64-Single" [^likeext001]
-* A third 24-bits (third 2-bit XO) is strongly recommended to be **reserved**
+* A third 24-bits (third 2-bit XO) is strongly recommended to be **reserved**comprehensive
+* To hold all Vector Context, five SPRs are needed for userspace (MSR.PR=1 Problem State).
+  If Supervisor and Hypervisor mode are to also support Simple-V they will correspondingly
+  need five SPRs each.
+
+# SVP64 24-bit Prefix
+
+The SVP64 24-bit Prefix provides several options 
+
+* Due to a concept called "Element-width Overrides
+
 
 [^extend]: Prefix opcode space **must** be reserved in advance to to so, in order to avoid the catastrophic binary-incompatibility mistake made by RISC-V RVV and ARM SVE/2
 [^likeext001]: SVP64-Single is remarkably similar to the "bit 1" of EXT001 being set to indicate that the 64-bits is to be allocated in full to a new encoding, but in fact it still embeds v3.0 Scalar operations.