https://bugs.libre-soc.org/show_bug.cgi?id=1091

* rename shadd to sadd
* rename sm to SH
* update CSV files with instruction definition
* move shadd unit tests to separate class

diff --git a/openpower/isa/bitmanip.mdwn b/openpower/isa/bitmanip.mdwn
index 6942ff5f26895418d13aeaf3c90767a377a786c9..830962c9ed6cea423a837fc077cce23c904f6682 100644 (file)
--- a/openpower/isa/bitmanip.mdwn
+++ b/openpower/isa/bitmanip.mdwn
@@ -105,13 +105,13 @@ Special Registers Altered:
 
 Z23-Form
 
-* shadd RT,RA,RB,sm (Rc=0)
-* shadd. RT,RA,RB,sm (Rc=1)
+* sadd RT,RA,RB,SH (Rc=0)
+* sadd. RT,RA,RB,SH (Rc=1)
 
 Pseudo-code:
 
     n <- (RB)
-    m <- ((0b0 || sm) + 1)
+    m <- ((0b0 || SH) + 1)
     RT <- (n[m:XLEN-1] || [0]*m) + (RA)
 
 Special Registers Altered:
@@ -122,15 +122,15 @@ Special Registers Altered:
 
 Z23-Form
 
-* shaddw RT,RA,RB,sm (Rc=0)
-* shaddw. RT,RA,RB,sm (Rc=1)
+* saddw RT,RA,RB,SH (Rc=0)
+* saddw. RT,RA,RB,SH (Rc=1)
 
 Pseudo-code:
 
     n <- ([0]*(XLEN/2)) || (RB)[XLEN/2:XLEN-1]
     if (RB)[XLEN/2] = 1 then
         n[0:XLEN/2-1] <- [1]*(XLEN/2)
-    m <- ((0b0 || sm) + 1)
+    m <- ((0b0 || SH) + 1)
     RT <- (n[m:XLEN-1] || [0]*m) + (RA)
 
 Special Registers Altered:
@@ -141,13 +141,13 @@ Special Registers Altered:
 
 Z23-Form
 
-* shadduw RT,RA,RB,sm (Rc=0)
-* shadduw. RT,RA,RB,sm (Rc=1)
+* sadduw RT,RA,RB,SH (Rc=0)
+* sadduw. RT,RA,RB,SH (Rc=1)
 
 Pseudo-code:
 
     n <- ([0]*(XLEN/2)) || (RB)[XLEN/2:XLEN-1]
-    m <- ((0b0 || sm) + 1)
+    m <- ((0b0 || SH) + 1)
     RT <- (n[m:XLEN-1] || [0]*m) + (RA)
 
 Special Registers Altered:

diff --git a/openpower/isatables/RM-1P-2S1D.csv b/openpower/isatables/RM-1P-2S1D.csv
index 9f747b8a1a23953ba62b5af334196a08ff4e3b43..5890ef24f6cfc3f7ef39ca0598ab75493d1f8690 100644 (file)
--- a/openpower/isatables/RM-1P-2S1D.csv
+++ b/openpower/isatables/RM-1P-2S1D.csv
@@ -26,9 +26,9 @@ modsw,NORMAL,,1P,EXTRA3,NO,d:RT,s:RA,s:RB,0,RA,RB,0,RT,0,0,0
 30/6=fmrgew,NORMAL,,1P,EXTRA3,NO,d:FRT,s:FRA,s:FRB,0,FRA,FRB,0,FRT,0,0,0
 rlwnm,NORMAL,,1P,EXTRA3,NO,d:RA;d:CR0,s:RB,s:RS,0,0,RB,RS,RA,0,CR0,0
 minmax,NORMAL,,1P,EXTRA3,NO,d:RT;d:CR0,s:RA,s:RB,0,RA_OR_ZERO,RB,0,RT,0,CR0,0
-shadd,NORMAL,,1P,EXTRA3,NO,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
-shaddw,NORMAL,,1P,EXTRA3,NO,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
-shadduw,NORMAL,,1P,EXTRA3,NO,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
+sadd,NORMAL,,1P,EXTRA3,NO,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
+saddw,NORMAL,,1P,EXTRA3,NO,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
+sadduw,NORMAL,,1P,EXTRA3,NO,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
 cprop,NORMAL,,1P,EXTRA3,NO,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
 absds,NORMAL,,1P,EXTRA3,NO,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
 absdu,NORMAL,,1P,EXTRA3,NO,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0

diff --git a/openpower/isatables/minor_22.csv b/openpower/isatables/minor_22.csv
index a2a6e8fe5bfd70b193d0a6749d8eb17f971f6674..5f14c358e8d5cc5f468ffbc2e1c9c726d7965a31 100644 (file)
--- a/openpower/isatables/minor_22.csv
+++ b/openpower/isatables/minor_22.csv
@@ -27,9 +27,9 @@ opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry ou
 100--011001,VL,OP_SVSHAPE,NONE,NONE,NONE,NONE,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,svshape2,SVM2,,1,unofficial until submitted and approved/renumbered by the opf isa wg
 # A/V bitmanip
 1101001110-,ALU,OP_AVGADD,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,avgadd,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg
---01101110-,ALU,OP_SHADD,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,shadd,Z23,,1,unofficial until submitted and approved/renumbered by the opf isa wg
---10101110-,ALU,OP_SHADD,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,shaddw,Z23,,1,unofficial until submitted and approved/renumbered by the opf isa wg
---11101110-,ALU,OP_SHADD,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,shadduw,Z23,,1,unofficial until submitted and approved/renumbered by the opf isa wg
+--01101110-,ALU,OP_SHADD,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,sadd,Z23,,1,unofficial until submitted and approved/renumbered by the opf isa wg
+--10101110-,ALU,OP_SHADD,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,saddw,Z23,,1,unofficial until submitted and approved/renumbered by the opf isa wg
+--11101110-,ALU,OP_SHADD,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,sadduw,Z23,,1,unofficial until submitted and approved/renumbered by the opf isa wg
 1011110110-,ALU,OP_ABSDIFF,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,absdu,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg
 1001110110-,ALU,OP_ABSDIFF,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,absds,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg
 1111110110-,ALU,OP_ABSADD,RA,RB,RT,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,absdacu,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg

diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py
index c02db670ca19485d8e794a1ba1973e9dfa9134f3..9dd55b869e9d9536dc6cdf27327627a4ba8ed55f 100644 (file)
--- a/src/openpower/decoder/isa/caller.py
+++ b/src/openpower/decoder/isa/caller.py
@@ -1954,7 +1954,7 @@ class ISACaller(ISACallerHelper, ISAFPHelpers, StepLoop):
                        'absdu', 'absds', 'absdacs', 'absdacu', 'avgadd',
                        'fmvis', 'fishmv', 'pcdec', "maddedu", "divmod2du",
                        "dsld", "dsrd", "maddedus",
-                       "shadd", "shaddw", "shadduw",
+                       "sadd", "saddw", "sadduw",
                        "fcvttg", "fcvttgo", "fcvttgs", "fcvttgso",
                        "fmvtg", "fmvtgs",
                        "fcvtfg", "fcvtfgs",

diff --git a/src/openpower/decoder/isa/test_caller_shadd.py b/src/openpower/decoder/isa/test_caller_shadd.py
new file mode 100644 (file)
index 0000000..84ad9df
--- /dev/null
+++ b/src/openpower/decoder/isa/test_caller_shadd.py
@@ -0,0 +1,23 @@
+""" bigint tests
+"""
+
+import unittest
+
+from openpower.test.bigint.shadd_cases import ShiftAddCases
+from openpower.test.runner import TestRunnerBase
+
+# writing the test_caller invocation this way makes it work with pytest
+
+
+class TestShAdd(TestRunnerBase):
+    def __init__(self, test):
+        assert test == 'test'
+        super().__init__(ShiftAddCases().test_data)
+
+    def test(self):
+        # dummy function to make unittest try to test this class
+        pass
+
+
+if __name__ == "__main__":
+    unittest.main()

diff --git a/src/openpower/decoder/power_enums.py b/src/openpower/decoder/power_enums.py
index 27f860b434f3ad12fae4e1c351e3d88d5d598e28..247acee71423fae379b8a9ac6c199c00ea0087b2 100644 (file)
--- a/src/openpower/decoder/power_enums.py
+++ b/src/openpower/decoder/power_enums.py
@@ -781,7 +781,7 @@ _insns = [
     "svshape2",  # https://libre-soc.org/openpower/sv/remap/discussion TODO
     "svstep",  # https://libre-soc.org/openpower/sv/setvl
     "sim_cfg",
-    "shadd", "shaddw", "shadduw",
+    "sadd", "saddw", "sadduw",
     "slbia", "sld", "slw", "srad", "sradi",
     "sraw", "srawi", "srd", "srw",
     "stb", "stbcix", "stbcx", "stbu", "stbux", "stbx",

diff --git a/src/openpower/sv/trans/test_pysvp64dis.py b/src/openpower/sv/trans/test_pysvp64dis.py
index f0a0542fae31ac8fc3cc335ef04faec87fbe2780..a2e0cc1a44092d840d3ee13b8f89881fa4d833b8 100644 (file)
--- a/src/openpower/sv/trans/test_pysvp64dis.py
+++ b/src/openpower/sv/trans/test_pysvp64dis.py
@@ -422,32 +422,32 @@ class SVSTATETestCase(unittest.TestCase):
                         ]
         self._do_tst(expected)
 
-    def test_31_shadd_shaddw_shadduw(self):
-        expected = [
-                    "shadd 31,0,0,0",
-                    "shadd 0,31,0,0",
-                    "shadd 0,0,31,0",
-                    "shadd 0,0,0,3",
-                    "shadd. 31,0,0,0",
-                    "shadd. 0,31,0,0",
-                    "shadd. 0,0,31,0",
-                    "shadd. 0,0,0,3",
-                    "shaddw 31,0,0,0",
-                    "shaddw 0,31,0,0",
-                    "shaddw 0,0,31,0",
-                    "shaddw 0,0,0,3",
-                    "shaddw. 31,0,0,0",
-                    "shaddw. 0,31,0,0",
-                    "shaddw. 0,0,31,0",
-                    "shaddw. 0,0,0,3",
-                    "shadduw 31,0,0,0",
-                    "shadduw 0,31,0,0",
-                    "shadduw 0,0,31,0",
-                    "shadduw 0,0,0,3",
-                    "shadduw. 31,0,0,0",
-                    "shadduw. 0,31,0,0",
-                    "shadduw. 0,0,31,0",
-                    "shadduw. 0,0,0,3",
+    def test_31_sadd_saddw_sadduw(self):
+        expected = [
+                    "sadd 31,0,0,0",
+                    "sadd 0,31,0,0",
+                    "sadd 0,0,31,0",
+                    "sadd 0,0,0,3",
+                    "sadd. 31,0,0,0",
+                    "sadd. 0,31,0,0",
+                    "sadd. 0,0,31,0",
+                    "sadd. 0,0,0,3",
+                    "saddw 31,0,0,0",
+                    "saddw 0,31,0,0",
+                    "saddw 0,0,31,0",
+                    "saddw 0,0,0,3",
+                    "saddw. 31,0,0,0",
+                    "saddw. 0,31,0,0",
+                    "saddw. 0,0,31,0",
+                    "saddw. 0,0,0,3",
+                    "sadduw 31,0,0,0",
+                    "sadduw 0,31,0,0",
+                    "sadduw 0,0,31,0",
+                    "sadduw 0,0,0,3",
+                    "sadduw. 31,0,0,0",
+                    "sadduw. 0,31,0,0",
+                    "sadduw. 0,0,31,0",
+                    "sadduw. 0,0,0,3",
                         ]
         self._do_tst(expected)
 

diff --git a/src/openpower/test/bigint/bigint_cases.py b/src/openpower/test/bigint/bigint_cases.py
index 260d8b7cdfc366d0cf846dbb2f93ed7729aa2090..092c8468abcae2cbaae007ed5c1d1942c0f3d727 100644 (file)
--- a/src/openpower/test/bigint/bigint_cases.py
+++ b/src/openpower/test/bigint/bigint_cases.py
@@ -123,50 +123,6 @@ class BigIntCases(TestAccumulatorBase):
                 e.intregs[6] = v % 2 ** 64
                 self.add_case(prog, gprs, expected=e)
 
-    def case_shadd(self):
-        for sm in range(4):
-            with self.subTest(sm=sm):
-                insn = ("shadd 3,4,5,%d" % sm)
-                prog = Program(list(SVP64Asm([insn])), False)
-                gprs = [0] * 32
-                gprs[3] = 0x01234567890abcde
-                RA = gprs[4] = 0xf00dcafedeadbeef
-                RB = gprs[5] = 0xabadbabedefec8ed
-                RT = ((((RB << (sm+1)) & _MASK64) + RA) & _MASK64)
-                e = ExpectedState(pc=4, int_regs=gprs)
-                e.intregs[3] = RT
-                self.add_case(prog, gprs, expected=e)
-
-    def case_shaddw(self):
-        for sm in range(4):
-            with self.subTest(sm=sm):
-                insn = ("shaddw 3,4,5,%d" % sm)
-                prog = Program(list(SVP64Asm([insn])), False)
-                gprs = [0] * 32
-                gprs[3] = 0x01234567890abcde
-                RA = gprs[4] = 0xf00dcafedeadbeef
-                RB = gprs[5] = 0xabadbabedefec8ed
-                RB_i32 = RB & _MASK32
-                if RB_i32 >> 31:
-                    RB_i32 -= 1 << 32
-                RT = ((((RB_i32 << (sm+1)) & _MASK64) + RA) & _MASK64)
-                e = ExpectedState(pc=4, int_regs=gprs)
-                e.intregs[3] = RT
-                self.add_case(prog, gprs, expected=e)
-
-    def case_shadduw(self):
-        for sm in range(4):
-            with self.subTest(sm=sm):
-                insn = ("shadduw 3,4,5,%d" % sm)
-                prog = Program(list(SVP64Asm([insn])), False)
-                gprs = [0] * 32
-                gprs[3] = 0x01234567890abcde
-                RA = gprs[4] = 0xf00dcafedeadbeef
-                RB = gprs[5] = 0xabadbabedefec8ed
-                RT = (((((RB & _MASK32) << (sm+1)) & _MASK64) + RA) & _MASK64)
-                e = ExpectedState(pc=4, int_regs=gprs)
-                e.intregs[3] = RT
-                self.add_case(prog, gprs, expected=e)
 
 
 class SVP64BigIntCases(TestAccumulatorBase):

diff --git a/src/openpower/test/bigint/shadd_cases.py b/src/openpower/test/bigint/shadd_cases.py
new file mode 100644 (file)
index 0000000..1534a8e
--- /dev/null
+++ b/src/openpower/test/bigint/shadd_cases.py
@@ -0,0 +1,59 @@
+from openpower.test.common import TestAccumulatorBase, skip_case
+from openpower.sv.trans.svp64 import SVP64Asm
+from openpower.test.state import ExpectedState
+from openpower.simulator.program import Program
+from openpower.decoder.isa.caller import SVP64State
+from openpower.decoder.helpers import exts
+
+
+_MASK32 = ((2 ** 32) - 1)
+_MASK64 = ((2 ** 64) - 1)
+
+
+class ShiftAddCases(TestAccumulatorBase):
+
+    def case_sadd(self):
+        for SH in range(4):
+            with self.subTest(SH=SH):
+                insn = ("sadd 3,4,5,%d" % SH)
+                prog = Program(list(SVP64Asm([insn])), False)
+                gprs = [0] * 32
+                gprs[3] = 0x01234567890abcde
+                RA = gprs[4] = 0xf00dcafedeadbeef
+                RB = gprs[5] = 0xabadbabedefec8ed
+                RT = ((((RB << (SH+1)) & _MASK64) + RA) & _MASK64)
+                e = ExpectedState(pc=4, int_regs=gprs)
+                e.intregs[3] = RT
+                self.add_case(prog, gprs, expected=e)
+
+    def case_saddw(self):
+        for SH in range(4):
+            with self.subTest(SH=SH):
+                insn = ("saddw 3,4,5,%d" % SH)
+                prog = Program(list(SVP64Asm([insn])), False)
+                gprs = [0] * 32
+                gprs[3] = 0x01234567890abcde
+                RA = gprs[4] = 0xf00dcafedeadbeef
+                RB = gprs[5] = 0xabadbabedefec8ed
+                RB_i32 = RB & _MASK32
+                if RB_i32 >> 31:
+                    RB_i32 -= 1 << 32
+                RT = ((((RB_i32 << (SH+1)) & _MASK64) + RA) & _MASK64)
+                e = ExpectedState(pc=4, int_regs=gprs)
+                e.intregs[3] = RT
+                self.add_case(prog, gprs, expected=e)
+
+    def case_sadduw(self):
+        for SH in range(4):
+            with self.subTest(SH=SH):
+                insn = ("sadduw 3,4,5,%d" % SH)
+                prog = Program(list(SVP64Asm([insn])), False)
+                gprs = [0] * 32
+                gprs[3] = 0x01234567890abcde
+                RA = gprs[4] = 0xf00dcafedeadbeef
+                RB = gprs[5] = 0xabadbabedefec8ed
+                RT = (((((RB & _MASK32) << (SH+1)) & _MASK64) + RA) & _MASK64)
+                e = ExpectedState(pc=4, int_regs=gprs)
+                e.intregs[3] = RT
+                self.add_case(prog, gprs, expected=e)
+