radv: Enforce the contiguous memory for DCC layers in ac_surface.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5194>

diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c
index 0a7d9e0d9b26b7e23cf303cc02e691be9b0d1fae..b29bf552c9f66e2b2556f6ca83a42b0c637dab2f 100644 (file)
--- a/src/amd/common/ac_surface.c
+++ b/src/amd/common/ac_surface.c
@@ -343,6 +343,13 @@ static int gfx6_compute_level(ADDR_HANDLE addrlib,
                                        else
                                                surf_level->dcc_slice_fast_clear_size = 0;
                                }
+
+                               if (surf->flags & RADEON_SURF_CONTIGUOUS_DCC_LAYERS &&
+                                   surf->dcc_slice_size != surf_level->dcc_slice_fast_clear_size) {
+                                       surf->dcc_size = 0;
+                                       surf->num_dcc_levels = 0;
+                                       AddrDccOut->subLvlCompressible = false;
+                               }
                        } else {
                                surf_level->dcc_slice_fast_clear_size = surf_level->dcc_fast_clear_size;
                        }

diff --git a/src/amd/common/ac_surface.h b/src/amd/common/ac_surface.h
index 7405192d57c87d44eebd75433130722e23b13c9a..161a54c988837e70ff88f744de715006b859e768 100644 (file)
--- a/src/amd/common/ac_surface.h
+++ b/src/amd/common/ac_surface.h
@@ -69,7 +69,7 @@ enum radeon_micro_mode {
 #define RADEON_SURF_DISABLE_DCC                 (1 << 22)
 #define RADEON_SURF_TC_COMPATIBLE_HTILE         (1 << 23)
 #define RADEON_SURF_IMPORTED                    (1 << 24)
-/* gap */
+#define RADEON_SURF_CONTIGUOUS_DCC_LAYERS       (1 << 25)
 #define RADEON_SURF_SHAREABLE                   (1 << 26)
 #define RADEON_SURF_NO_RENDER_TARGET            (1 << 27)
 /* Force a swizzle mode (gfx9+) or tile mode (gfx6-8).

diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index 09b086dbcea3a510f1f8e82ffa3e94a40e907194..b84f71b9a581853d74dcecec1267771a56551575 100644 (file)
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -447,6 +447,9 @@ radv_init_surface(struct radv_device *device,
                unreachable("unhandled image type");
        }
 
+       /* Required for clearing/initializing a specific layer on GFX8. */
+       surface->flags |= RADEON_SURF_CONTIGUOUS_DCC_LAYERS;
+
        if (is_depth) {
                surface->flags |= RADEON_SURF_ZBUFFER;
                if (radv_use_tc_compat_htile_for_image(device, pCreateInfo, image_format))
@@ -1288,21 +1291,6 @@ radv_image_can_enable_dcc(struct radv_device *device, struct radv_image *image)
            !radv_image_has_dcc(image))
                return false;
 
-       /* On GFX8, DCC layers can be interleaved and it's currently only
-        * enabled if slice size is equal to the per slice fast clear size
-        * because the driver assumes that portions of multiple layers are
-        * contiguous during fast clears.
-        */
-       if (image->info.array_size > 1) {
-               const struct legacy_surf_level *surf_level =
-                       &image->planes[0].surface.u.legacy.level[0];
-
-               assert(device->physical_device->rad_info.chip_class == GFX8);
-
-               if (image->planes[0].surface.dcc_slice_size != surf_level->dcc_fast_clear_size)
-                       return false;
-       }
-
        return true;
 }