interconnect/avalon: minor cleanup, remove max on SyncFIFO depth.

diff --git a/litex/soc/interconnect/avalon.py b/litex/soc/interconnect/avalon.py
index dd6a46339d3d0b3eea6705af1dcd8c7941f881ad..a14be66c3481ef299fc7ef4265355263c4e32a07 100644 (file)
--- a/litex/soc/interconnect/avalon.py
+++ b/litex/soc/interconnect/avalon.py
@@ -1,4 +1,4 @@
-# This file is Copyright (c) 2019 Florent Kermarrec <florent@enjoy-digital.fr>
+# This file is Copyright (c) 2019-2020 Florent Kermarrec <florent@enjoy-digital.fr>
 # License: BSD
 
 """Avalon support for LiteX"""
@@ -19,7 +19,7 @@ from litex.soc.interconnect import stream
 class Native2AvalonST(Module):
     """Native LiteX's stream to Avalon-ST stream"""
     def __init__(self, layout, latency=2):
-        self.sink = sink = stream.Endpoint(layout)
+        self.sink   = sink   = stream.Endpoint(layout)
         self.source = source = stream.Endpoint(layout)
 
         # # #
@@ -38,15 +38,13 @@ class Native2AvalonST(Module):
 class AvalonST2Native(Module):
     """Avalon-ST Stream to native LiteX's stream"""
     def __init__(self, layout, latency=2):
-        self.sink = sink = stream.Endpoint(layout)
+        self.sink   = sink   = stream.Endpoint(layout)
         self.source = source = stream.Endpoint(layout)
 
         # # #
 
-        buf = stream.SyncFIFO(layout, max(latency, 4))
+        buf = stream.SyncFIFO(layout, latency)
         self.submodules += buf
-        self.comb += [
-            sink.connect(buf.sink, omit={"ready"}),
-            sink.ready.eq(source.ready),
-            buf.source.connect(source)
-        ]
+        self.comb += sink.connect(buf.sink, omit={"ready"})
+        self.comb += sink.ready.eq(source.ready)
+        self.comb += buf.source.connect(source)