connect to dcache.bus standard interface when using wb_get

diff --git a/src/openpower/test/runner.py b/src/openpower/test/runner.py
index 51f4a596e1b4d8a638fe5a68db4d5248e6ba104c..2d6a825ed542ad797626d9dabcd6054621cff9c1 100644 (file)
--- a/src/openpower/test/runner.py
+++ b/src/openpower/test/runner.py
@@ -461,7 +461,8 @@ class TestRunnerBase(FHDLTestCase):
         if self.rom is not None:
             dcache = hdlrun.issuer.core.fus.fus["mmu0"].alu.dcache
             default_mem = self.rom
-            sim.add_sync_process(wrap(wb_get(dcache, default_mem, "DCACHE")))
+            sim.add_sync_process(wrap(wb_get(dcache.bus,
+                                             default_mem, "DCACHE")))
 
         with sim.write_vcd("issuer_simulator.vcd"):
             sim.run()