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diff --git a/openpower/sv/svp64/appendix.mdwn b/openpower/sv/svp64/appendix.mdwn
index 994d17e4d984f4dfb61c5515fddc69df791c7c80..57eeef79173f714468fdbab567aaf2f3a81a7b3f 100644 (file)
--- a/openpower/sv/svp64/appendix.mdwn
+++ b/openpower/sv/svp64/appendix.mdwn
@@ -23,6 +23,40 @@ so that soft-emulation is possible,
 even for future revisions of SVP64. With SVP64 being partly controlled
 through contextual SPRs, a little care has to be taken.
 
+**All** SPRs
+not implemented including reserved ones for future use must raise an illegal
+instruction trap if read or written. This allows software the
+opportunity to emulate the context created by the given SPR.
+
+**Embedded Scalar Scenario**
+
+In this scenario an implementation does not wish to implement the Vectorisation
+but simply wishes to take advantage of predication or other feature
+of SVP64, such as instructions that might only be available if prefixed.
+Such an implementation would be entirely free to do so with the proviso
+that:
+
+* any attempts to call `setvl` shall either raise an illegal instruction
+  or be partially implemented to set SVSTATE correctly.
+* if SVSTATE contains any value in any bit that is not supported
+  in hardware, an illegal instruction shall be raised when an SVP64
+  prefixed instruction is executed.
+* if SVSTATE contains values requesting supported features at the time
+  that the prefixed instruction is executed then it is executed in
+  hardware as per specification, with no illegal exception trap raised.
+
+Example, assuming that hardware implements predication but not
+elwidth overrides:
+
+    setvli r0, 4            # sets VL equal to 4
+    sv.addi r5, r0, 1       # raises an 0x700 trap
+    setvli r0, 1            # sets VL equal to 1
+    sv.addi r5, r0, 1       # gets executed by hardware
+    sv.addi/ew=8 r5, r0, 1  # raises an 0x700 trap
+    sv.ori/sm=EQ r5, r0, 1  # executed by hardware
+
+The first 
+
 # XER, SO and other global flags
 
 Vector systems are expected to be high performance.  This is achieved