radeonsi: enable displayable DCC on Ravens
authorMarek Olšák <marek.olsak@amd.com>
Wed, 9 Jan 2019 01:08:08 +0000 (20:08 -0500)
committerMarek Olšák <marek.olsak@amd.com>
Thu, 4 Apr 2019 13:53:24 +0000 (09:53 -0400)
src/amd/common/ac_gpu_info.c
src/amd/vulkan/winsys/amdgpu/radv_amdgpu_winsys.c

index d890172227cbfbbdb31af40c33291b6809b5e205..c53335bbb7de65f829deafec580cb6155ff86965 100644 (file)
@@ -458,6 +458,14 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
        assert(ib_align);
        info->ib_start_alignment = ib_align;
 
+       if (info->drm_minor >= 31 &&
+           (info->family == CHIP_RAVEN ||
+            info->family == CHIP_RAVEN2)) {
+               if (info->num_render_backends == 1)
+                       info->use_display_dcc_unaligned = true;
+               else
+                       info->use_display_dcc_with_retile_blit = true;
+       }
        return true;
 }
 
index d3a57f6b4f3f2a1c7222513a69b3cd61e42c635e..35a585a5693a863db448afa7096608bec8db31f3 100644 (file)
@@ -45,6 +45,10 @@ do_winsys_init(struct radv_amdgpu_winsys *ws, int fd)
        if (!ac_query_gpu_info(fd, ws->dev, &ws->info, &ws->amdinfo))
                return false;
 
+       /* temporary */
+       ws->info.use_display_dcc_unaligned = false;
+       ws->info.use_display_dcc_with_retile_blit = false;
+
        ws->addrlib = amdgpu_addr_create(&ws->info, &ws->amdinfo, &ws->info.max_alignment);
        if (!ws->addrlib) {
                fprintf(stderr, "amdgpu: Cannot create addrlib.\n");