3000.md: Improve description.

2004-06-30  Richard Sandiford  <rsandifo@redhat.com>
	    Eric Christopher  <echristo@redhat.com>

	* config/mips/3000.md: Improve description.

From-SVN: r83917

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 5ca2417a697a7bd5b36403537c0857151e7c7f18..04562d7d06665c7c33afb234ddc77e829da1f240 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2004-06-30  Richard Sandiford  <rsandifo@redhat.com>
+           Eric Christopher  <echristo@redhat.com>
+
+       * config/mips/3000.md: Improve description.
+
 2004-06-30  Paul Brook  <paul@codesourcery.com>
 
        * config/arm/cirrus.md (cirrus_arm_movdi, cirrus_movsf_hard_insn,
@@ -146,7 +151,7 @@
 
 2004-06-29  Per Bothner  <per@bothner.com>
 
-       * config/i386/winnt.c (i386_pe_encode_section_info):  Smash rtlname's 
+       * config/i386/winnt.c (i386_pe_encode_section_info):  Smash rtlname's
        XSTR in place, so we don't lose SYMBOL_REF_DECL info.
 
 2004-06-29  Zack Weinberg  <zack@codesourcery.com>

diff --git a/gcc/config/mips/3000.md b/gcc/config/mips/3000.md
index 92825978002498527829187d24e3830299e81d37..8c9a0d6429f5b24e9146003175b6d9c56027c2fa 100644 (file)
--- a/gcc/config/mips/3000.md
+++ b/gcc/config/mips/3000.md
@@ -2,68 +2,77 @@
 ;; This is a special pipeline - this is also the default schedule and
 ;; so we need to schedule instructions that may not exist on the r2k/r3k.
 
-;; Generic processor description that assumes that the only latencies are for
-;; hazards or delay slots, otherwise everything is assumed to issue and execute
-;; in one cycle.
-(define_automaton "r3k")
+(define_automaton "r3k_alu,r3k_imuldiv")
 
-(define_cpu_unit "r3k_alu" "r3k")
+(define_cpu_unit "r3k_alu" "r3k_alu")
+(define_cpu_unit "r3k_imuldiv" "r3k_imuldiv")
 
-(define_insn_reservation "r3k_generic_alu" 1
+(define_insn_reservation "r3k_generic" 1
   (and (eq_attr "cpu" "r3000")
-       (eq_attr "type" "unknown,prefetch,prefetchx,condmove,mthilo,const,arith,shift,slt,clz,trap,fmove,fadd,fmadd,fabs,fneg,fcvt,fsqrt,frsqrt,multi,nop"))
+       (eq_attr "type" "unknown,prefetch,prefetchx,condmove,const,arith,
+                       shift,slt,clz,trap,multi,nop"))
   "r3k_alu")
 
-(define_insn_reservation "r3k_load_alu" 2
+(define_insn_reservation "r3k_load" 2
   (and (eq_attr "cpu" "r3000")
-       (eq_attr "type" "load, fpload, fpidxload, xfer"))
-  "r3k_alu*2")
+       (eq_attr "type" "load,fpload,fpidxload,xfer"))
+  "r3k_alu")
 
-(define_insn_reservation "r3k_call_alu" 2
+(define_insn_reservation "r3k_store" 1
   (and (eq_attr "cpu" "r3000")
-       (eq_attr "type" "branch,jump,call"))
-  "r3k_alu*2")
+       (eq_attr "type" "store,fpstore,fpidxstore"))
+  "r3k_alu")
 
-(define_insn_reservation "r3k_hilo_alu" 3
+(define_insn_reservation "r3k_branch" 1
   (and (eq_attr "cpu" "r3000")
-       (eq_attr "type" "mfhilo"))
-  "r3k_alu*3")
+       (eq_attr "type" "branch,jump,call"))
+  "r3k_alu")
 
-(define_insn_reservation "r3k_fcmp_alu" 2
+(define_insn_reservation "r3k_hilo" 1
   (and (eq_attr "cpu" "r3000")
-       (eq_attr "type" "fcmp, fadd"))
-  "r3k_alu*2")
+       (eq_attr "type" "mfhilo,mthilo"))
+  "r3k_imuldiv*3")
 
-(define_insn_reservation "r3k_imul_alu" 12
+(define_insn_reservation "r3k_imul" 12
   (and (eq_attr "cpu" "r3000")
-       (eq_attr "type" "imul, imadd"))
-  "r3k_alu*12")
+       (eq_attr "type" "imul,imadd"))
+  "r3k_imuldiv*12")
 
-(define_insn_reservation "r3k_idiv_alu" 35
+(define_insn_reservation "r3k_idiv" 35
   (and (eq_attr "cpu" "r3000")
        (eq_attr "type" "idiv"))
-  "r3k_alu*35")
+  "r3k_imuldiv*35")
+
+(define_insn_reservation "r3k_fmove" 1
+  (and (eq_attr "cpu" "r3000")
+       (eq_attr "type" "fabs,fneg,fmove,fcvt"))
+  "r3k_alu")
 
-(define_insn_reservation "r3k_fmul_single_alu" 4
+(define_insn_reservation "r3k_fadd" 2
   (and (eq_attr "cpu" "r3000")
-       (and (eq_attr "type" "fmul")
+       (eq_attr "type" "fcmp,fadd"))
+  "r3k_alu")
+
+(define_insn_reservation "r3k_fmul_single" 4
+  (and (eq_attr "cpu" "r3000")
+       (and (eq_attr "type" "fmul,fmadd")
            (eq_attr "mode" "SF")))
-  "r3k_alu*4")
+  "r3k_alu")
 
-(define_insn_reservation "r3k_fmul_double_alu" 5
+(define_insn_reservation "r3k_fmul_double" 5
   (and (eq_attr "cpu" "r3000")
-       (and (eq_attr "type" "fmul")
+       (and (eq_attr "type" "fmul,fmadd")
            (eq_attr "mode" "DF")))
-  "r3k_alu*5")
+  "r3k_alu")
 
-(define_insn_reservation "r3k_fdiv_single_alu" 12
+(define_insn_reservation "r3k_fdiv_single" 12
   (and (eq_attr "cpu" "r3000")
-       (and (eq_attr "type" "fdiv")
+       (and (eq_attr "type" "fdiv,fsqrt,frsqrt")
            (eq_attr "mode" "SF")))
-  "r3k_alu*12")
+  "r3k_alu")
 
-(define_insn_reservation "r3k_fdiv_double_alu" 19
+(define_insn_reservation "r3k_fdiv_double" 19
   (and (eq_attr "cpu" "r3000")
-       (and (eq_attr "type" "fdiv")
+       (and (eq_attr "type" "fdiv,fsqrt,frsqrt")
            (eq_attr "mode" "DF")))
-  "r3k_alu*19")
+  "r3k_alu")