rs6000: Remove TM regs

We do not need to expose the TM registers in debug info.  It isn't
actually useful there, because none of the things that can modify
these registers (other than explicit moves) are marked.

We also do not need the registers for GCC itself internally.  This
patch deletes them.

	* config/rs6000/rs6000.md (TFHAR_REGNO, TFIAR_REGNO, TEXASR_REGNO):
	Delete.
	* config/rs6000/rs6000.h (FIRST_PSEUDO_REGISTER): Adjust.
	(DWARF_FRAME_REGISTERS): Adjust.
	(FIXED_REGISTERS, CALL_USED_REGISTERS, CALL_REALLY_USED_REGISTERS):
	Adjust.
	(REG_ALLOC_ORDER): Adjust.
	(enum reg_class): Delete SPR_REGS.
	(REG_CLASS_NAMES): Delete SPR_REGS.
	(REG_CLASS_CONTENTS): Delete SPR_REGS.  Adjust for deleted TM regs.
	(REGISTER_NAMES): Adjust.
	(ADDITIONAL_REGISTER_NAMES): Adjust.
	* config/rs6000/darwin.h (REGISTER_NAMES): Adjust.
	* config/rs6000/htm.md (htm_mfspr_<mode>, htm_mtspr_<mode>): Adjust.
	* config/rs6000/predicates.md (htm_spr_reg_operand): Delete.
	* config/rs6000/rs6000.c (rs6000_init_hard_regno_mode_ok): Adjust.
	(htm_spr_regno): Delete.
	(htm_expand_builtin): Adjust: the HTM builtins now have one fewer
	argument.
	(rs6000_dbx_register_number): Adjust.

From-SVN: r270927

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 652aa88a26969145856f37962ee35a8d4bad7559..bf16557218df067dac26c2341e5dc0e43d75e113 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,26 @@
+2019-05-06  Segher Boessenkool  <segher@kernel.crashing.org>
+
+       * config/rs6000/rs6000.md (TFHAR_REGNO, TFIAR_REGNO, TEXASR_REGNO):
+       Delete.
+       * config/rs6000/rs6000.h (FIRST_PSEUDO_REGISTER): Adjust.
+       (DWARF_FRAME_REGISTERS): Adjust.
+       (FIXED_REGISTERS, CALL_USED_REGISTERS, CALL_REALLY_USED_REGISTERS):
+       Adjust.
+       (REG_ALLOC_ORDER): Adjust.
+       (enum reg_class): Delete SPR_REGS.
+       (REG_CLASS_NAMES): Delete SPR_REGS.
+       (REG_CLASS_CONTENTS): Delete SPR_REGS.  Adjust for deleted TM regs.
+       (REGISTER_NAMES): Adjust.
+       (ADDITIONAL_REGISTER_NAMES): Adjust.
+       * config/rs6000/darwin.h (REGISTER_NAMES): Adjust.
+       * config/rs6000/htm.md (htm_mfspr_<mode>, htm_mtspr_<mode>): Adjust.
+       * config/rs6000/predicates.md (htm_spr_reg_operand): Delete.
+       * config/rs6000/rs6000.c (rs6000_init_hard_regno_mode_ok): Adjust.
+       (htm_spr_regno): Delete.
+       (htm_expand_builtin): Adjust: the HTM builtins now have one fewer
+       argument.
+       (rs6000_dbx_register_number): Adjust.
+
 2019-05-06  Segher Boessenkool  <segher@kernel.crashing.org>
 
        * config/rs6000/rs6000.h (PRE_GCC3_DWARF_FRAME_REGISTERS): Delete.

diff --git a/gcc/config/rs6000/darwin.h b/gcc/config/rs6000/darwin.h
index 9fb36e41e7dc34d1e0b6d1633492e5aadc7836c6..d86333d94290244950a9e0127e7e9241f2414409 100644 (file)
--- a/gcc/config/rs6000/darwin.h
+++ b/gcc/config/rs6000/darwin.h
@@ -231,8 +231,7 @@ extern int darwin_emit_branch_islands;
     "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",             \
     "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",             \
     "vrsave", "vscr",                                                  \
-    "sfp",                                                             \
-    "tfhar", "tfiar", "texasr"                                         \
+    "sfp"                                                              \
 }
 
 /* This outputs NAME to FILE.  */

diff --git a/gcc/config/rs6000/htm.md b/gcc/config/rs6000/htm.md
index 66b583d92804b8391ee256d6c6ad18988b34eabe..9e99afad9c0df374d2a22f12d53023cc6e1dee1e 100644 (file)
--- a/gcc/config/rs6000/htm.md
+++ b/gcc/config/rs6000/htm.md
@@ -267,18 +267,16 @@
 
 (define_insn "htm_mfspr_<mode>"
   [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
-        (unspec_volatile:GPR [(match_operand 1 "u10bit_cint_operand" "n")
-                             (match_operand:GPR 2 "htm_spr_reg_operand" "")]
+        (unspec_volatile:GPR [(match_operand 1 "u10bit_cint_operand" "n")]
                             UNSPECV_HTM_MFSPR))]
   "TARGET_HTM"
   "mfspr %0,%1";
   [(set_attr "type" "htm")])
 
 (define_insn "htm_mtspr_<mode>"
-  [(set (match_operand:GPR 2 "htm_spr_reg_operand" "")
-        (unspec_volatile:GPR [(match_operand:GPR 0 "gpc_reg_operand" "r")
-                             (match_operand 1 "u10bit_cint_operand" "n")]
-                            UNSPECV_HTM_MTSPR))]
+  [(unspec_volatile [(match_operand:GPR 0 "gpc_reg_operand" "r")
+                    (match_operand 1 "u10bit_cint_operand" "n")]
+                   UNSPECV_HTM_MTSPR)]
   "TARGET_HTM"
   "mtspr %1,%0";
   [(set_attr "type" "htm")])

diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md
index 5cc80dea66c061712478c523c6103705d46ea18b..2643f1abd2ee604c4bef980ca1703ac98aa23d64 100644 (file)
--- a/gcc/config/rs6000/predicates.md
+++ b/gcc/config/rs6000/predicates.md
@@ -406,33 +406,6 @@
   return FP_REGNO_P (r);
 })
 
-;; Return 1 if op is a HTM specific SPR register.
-(define_predicate "htm_spr_reg_operand"
-  (match_operand 0 "register_operand")
-{
-  if (!TARGET_HTM)
-    return 0;
-
-  if (SUBREG_P (op))
-    op = SUBREG_REG (op);
-
-  if (!REG_P (op))
-    return 0;
-
-  switch (REGNO (op))
-    {
-      case TFHAR_REGNO:
-      case TFIAR_REGNO:
-      case TEXASR_REGNO:
-       return 1;
-      default:
-       break;
-    }
-  
-  /* Unknown SPR.  */
-  return 0;
-})
-
 ;; Return 1 if op is a general purpose register that is an even register
 ;; which suitable for a load/store quad operation
 ;; Subregs are not allowed here because when they are combine can

diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 1e5eef8d51b76e1c6465bbbd9f2c8a5e46b1ccd0..d7b75263df417921a4944177e6319cc7528f7e55 100644 (file)
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -3011,9 +3011,6 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
   rs6000_regno_regclass[CA_REGNO] = NO_REGS;
   rs6000_regno_regclass[VRSAVE_REGNO] = VRSAVE_REGS;
   rs6000_regno_regclass[VSCR_REGNO] = VRSAVE_REGS;
-  rs6000_regno_regclass[TFHAR_REGNO] = SPR_REGS;
-  rs6000_regno_regclass[TFIAR_REGNO] = SPR_REGS;
-  rs6000_regno_regclass[TEXASR_REGNO] = SPR_REGS;
   rs6000_regno_regclass[ARG_POINTER_REGNUM] = BASE_REGS;
   rs6000_regno_regclass[FRAME_POINTER_REGNUM] = BASE_REGS;
 
@@ -14098,23 +14095,6 @@ htm_spr_num (enum rs6000_builtins code)
   return TEXASRU_SPR;
 }
 
-/* Return the appropriate SPR regno associated with the given builtin.  */
-static inline HOST_WIDE_INT
-htm_spr_regno (enum rs6000_builtins code)
-{
-  if (code == HTM_BUILTIN_GET_TFHAR
-      || code == HTM_BUILTIN_SET_TFHAR)
-    return TFHAR_REGNO;
-  else if (code == HTM_BUILTIN_GET_TFIAR
-          || code == HTM_BUILTIN_SET_TFIAR)
-    return TFIAR_REGNO;
-  gcc_assert (code == HTM_BUILTIN_GET_TEXASR
-             || code == HTM_BUILTIN_SET_TEXASR
-             || code == HTM_BUILTIN_GET_TEXASRU
-             || code == HTM_BUILTIN_SET_TEXASRU);
-  return TEXASR_REGNO;
-}
-
 /* Return the correct ICODE value depending on whether we are
    setting or reading the HTM SPRs.  */
 static inline enum insn_code
@@ -14231,7 +14211,6 @@ htm_expand_builtin (tree exp, rtx target, bool * expandedp)
          {
            machine_mode mode = (TARGET_POWERPC64) ? DImode : SImode;
            op[nopnds++] = gen_rtx_CONST_INT (mode, htm_spr_num (fcode));
-           op[nopnds++] = gen_rtx_REG (mode, htm_spr_regno (fcode));
          }
        /* If this builtin accesses a CR, then pass in a scratch
           CR as the last operand.  */
@@ -14252,7 +14231,7 @@ htm_expand_builtin (tree exp, rtx target, bool * expandedp)
            if (!(attr & RS6000_BTC_VOID))
              expected_nopnds += 1;
            if (uses_spr)
-             expected_nopnds += 2;
+             expected_nopnds += 1;
 
            gcc_assert (nopnds == expected_nopnds
                        && nopnds <= MAX_HTM_OPERANDS);
@@ -36302,12 +36281,6 @@ rs6000_dbx_register_number (unsigned int regno, unsigned int format)
        return 356;
       if (regno == VSCR_REGNO)
        return 67;
-      if (regno == TFHAR_REGNO)
-       return 228;
-      if (regno == TFIAR_REGNO)
-       return 229;
-      if (regno == TEXASR_REGNO)
-       return 230;
 
       /* These do not make much sense.  */
       if (regno == FRAME_POINTER_REGNUM)
@@ -36342,12 +36315,6 @@ rs6000_dbx_register_number (unsigned int regno, unsigned int format)
     return 109;
   if (regno == VSCR_REGNO)
     return 110;
-  if (regno == TFHAR_REGNO)
-    return 114;
-  if (regno == TFIAR_REGNO)
-    return 115;
-  if (regno == TEXASR_REGNO)
-    return 116;
 
   if (regno == FRAME_POINTER_REGNUM)
     return 111;

diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 3829e8f0a825914139f9dc155d28339566dd889c..3a32c11503681028b60a2c7efc509acd797e9ac8 100644 (file)
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -815,11 +815,10 @@ enum data_align { align_abi, align_opt, align_both };
 
    The 3 HTM registers aren't also included in DWARF_FRAME_REGISTERS.  */
 
-#define FIRST_PSEUDO_REGISTER 115
+#define FIRST_PSEUDO_REGISTER 112
 
-/* The sfp register and 3 HTM registers
-   aren't included in DWARF_FRAME_REGISTERS.  */
-#define DWARF_FRAME_REGISTERS (FIRST_PSEUDO_REGISTER - 4)
+/* The sfp register isn't included in DWARF_FRAME_REGISTERS.  */
+#define DWARF_FRAME_REGISTERS (FIRST_PSEUDO_REGISTER - 1)
 
 /* Use standard DWARF numbering for DWARF debugging information.  */
 #define DBX_REGISTER_NUMBER(REGNO) rs6000_dbx_register_number ((REGNO), 0)
@@ -851,7 +850,7 @@ enum data_align { align_abi, align_opt, align_both };
    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
    1, 1                                                   \
-   , 1, 1, 1, 1                                           \
+   , 1                                            \
 }
 
 /* 1 for registers not available across function calls.
@@ -871,7 +870,7 @@ enum data_align { align_abi, align_opt, align_both };
    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
    1, 1                                                   \
-   , 1, 1, 1, 1                                           \
+   , 1                                            \
 }
 
 /* Like `CALL_USED_REGISTERS' except this macro doesn't require that
@@ -890,7 +889,7 @@ enum data_align { align_abi, align_opt, align_both };
    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
    0, 0                                                   \
-   , 0, 0, 0, 0                                           \
+   , 0                                            \
 }
 
 #define TOTAL_ALTIVEC_REGS     (LAST_ALTIVEC_REGNO - FIRST_ALTIVEC_REGNO + 1)
@@ -929,9 +928,6 @@ enum data_align { align_abi, align_opt, align_both };
        v31 - v20       (saved; order given to save least number)
        vrsave, vscr    (fixed)
        sfp             (fixed)
-       tfhar           (fixed)
-       tfiar           (fixed)
-       texasr          (fixed)
 */
 
 #if FIXED_R2 == 1
@@ -973,7 +969,7 @@ enum data_align { align_abi, align_opt, align_both };
    96, 95, 94, 93, 92, 91,                                     \
    108, 107, 106, 105, 104, 103, 102, 101, 100, 99, 98, 97,    \
    109, 110,                                                   \
-   111, 112, 113, 114                                          \
+   111                                                         \
 }
 
 /* True if register is floating-point.  */
@@ -1134,7 +1130,6 @@ enum reg_class
   VSX_REGS,
   VRSAVE_REGS,
   VSCR_REGS,
-  SPR_REGS,
   GEN_OR_FLOAT_REGS,
   LINK_REGS,
   CTR_REGS,
@@ -1163,7 +1158,6 @@ enum reg_class
   "VSX_REGS",                                                          \
   "VRSAVE_REGS",                                                       \
   "VSCR_REGS",                                                         \
-  "SPR_REGS",                                                          \
   "GEN_OR_FLOAT_REGS",                                                 \
   "LINK_REGS",                                                         \
   "CTR_REGS",                                                          \
@@ -1199,8 +1193,6 @@ enum reg_class
   { 0x00000000, 0x00000000, 0x00000000, 0x00002000 },                  \
   /* VSCR_REGS.  */                                                    \
   { 0x00000000, 0x00000000, 0x00000000, 0x00004000 },                  \
-  /* SPR_REGS.  */                                                     \
-  { 0x00000000, 0x00000000, 0x00000000, 0x00010000 },                  \
   /* GEN_OR_FLOAT_REGS.  */                                            \
   { 0xffffffff, 0xffffffff, 0x00000008, 0x00008000 },                  \
   /* LINK_REGS.  */                                                    \
@@ -1222,7 +1214,7 @@ enum reg_class
   /* CA_REGS.  */                                                      \
   { 0x00000000, 0x00000000, 0x00001000, 0x00000000 },                  \
   /* ALL_REGS.  */                                                     \
-  { 0xffffffff, 0xffffffff, 0xfffffffe, 0x0001ffff }                   \
+  { 0xffffffff, 0xffffffff, 0xfffffffe, 0x0000ffff }                   \
 }
 
 /* The same information, inverted:
@@ -2144,10 +2136,7 @@ extern char rs6000_reg_names[][8];       /* register names (0 vs. %r0).  */
   &rs6000_reg_names[108][0],   /* v31  */                              \
   &rs6000_reg_names[109][0],   /* vrsave  */                           \
   &rs6000_reg_names[110][0],   /* vscr  */                             \
-  &rs6000_reg_names[111][0],   /* sfp  */                              \
-  &rs6000_reg_names[112][0],   /* tfhar  */                            \
-  &rs6000_reg_names[113][0],   /* tfiar  */                            \
-  &rs6000_reg_names[114][0],   /* texasr  */                           \
+  &rs6000_reg_names[111][0]    /* sfp  */                              \
 }
 
 /* Table of additional register names to use in user input.  */
@@ -2201,8 +2190,6 @@ extern char rs6000_reg_names[][8];        /* register names (0 vs. %r0).  */
   {"vs52", 97}, {"vs53", 98}, {"vs54", 99}, {"vs55", 100},     \
   {"vs56", 101},{"vs57", 102},{"vs58", 103},{"vs59", 104},      \
   {"vs60", 105},{"vs61", 106},{"vs62", 107},{"vs63", 108},     \
-  /* Transactional Memory Facility (HTM) Registers.  */                \
-  {"tfhar",  112}, {"tfiar",  113}, {"texasr",  114},          \
 }
 
 /* This is how to output an element of a case-vector that is relative.  */

diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index ad80592765d047db68d61e64bb48a7ec0cf48ddd..9c1a645741c200cb2443f8434a840e859e99b8a1 100644 (file)
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -51,9 +51,6 @@
    (VRSAVE_REGNO               109)
    (VSCR_REGNO                 110)
    (FRAME_POINTER_REGNUM       111)
-   (TFHAR_REGNO                        112)
-   (TFIAR_REGNO                        113)
-   (TEXASR_REGNO               114)
   ])
 
 ;;