fhdl/verilog: improve error reporting

diff --git a/migen/fhdl/verilog.py b/migen/fhdl/verilog.py
index 66c28799988c0d5bbdd6df0529afc5b88e20c07b..8dc404fe07986b6be27c88a3481daae9af850a5b 100644 (file)
--- a/migen/fhdl/verilog.py
+++ b/migen/fhdl/verilog.py
@@ -80,7 +80,7 @@ def _printexpr(ns, node):
        elif isinstance(node, Replicate):
                return "{" + str(node.n) + "{" + _printexpr(ns, node.v)[0] + "}}", False
        else:
-               raise TypeError
+               raise TypeError("Expression of unrecognized type: "+str(type(node)))
 
 (_AT_BLOCKING, _AT_NONBLOCKING, _AT_SIGNAL) = range(3)
 
@@ -124,7 +124,7 @@ def _printnode(ns, at, level, node):
                else:
                        return ""
        else:
-               raise TypeError
+               raise TypeError("Node of unrecognized type: "+str(type(node)))
 
 def _list_comb_wires(f):
        r = set()