v3d: Rename "configuration" and "config" in the XML to "cfg"

This matches what CLIF parsing expects, and makes
TILE_BINNING_MODE_CONFIGURATION_COMMON_CONFIGURATION into a much more
legible TILE_BINNING_MODE_CFG_COMMON.

diff --git a/src/broadcom/cle/v3d_packet_v33.xml b/src/broadcom/cle/v3d_packet_v33.xml
index 6fe9d7481c2a2e0e3fc83989f18e5e1066735be2..5b9be0fcab9b10c994905e74a1df22e920a7ed9b 100644 (file)
--- a/src/broadcom/cle/v3d_packet_v33.xml
+++ b/src/broadcom/cle/v3d_packet_v33.xml
@@ -563,7 +563,7 @@
     <field name="address" size="32" start="0" type="address"/>
   </struct>
 
-  <packet code="80" name="Stencil Config">
+  <packet code="80" name="Stencil Cfg">
     <field name="Stencil Write Mask" size="8" start="32" type="uint"/>
     <field name="Back Config" size="1" start="29" type="bool"/>
     <field name="Front Config" size="1" start="28" type="bool"/>
@@ -579,7 +579,7 @@
     <field name="Mask" size="8" start="0" type="uint"/>
   </packet>
 
-  <packet code="84" name="Blend Config" max_ver="33">
+  <packet code="84" name="Blend Cfg" max_ver="33">
     <field name="Color blend dst factor" size="4" start="20" type="Blend Factor"/>
     <field name="Color blend src factor" size="4" start="16" type="Blend Factor"/>
     <field name="Color blend mode" size="4" start="12" type="Blend Mode"/>
@@ -588,7 +588,7 @@
     <field name="Alpha blend mode" size="4" start="0" type="Blend Mode"/>
   </packet>
 
-  <packet code="84" name="Blend Config" min_ver="41">
+  <packet code="84" name="Blend Cfg" min_ver="41">
     <field name="Render Target Mask" size="4" start="24" type="uint"/>
     <field name="Color blend dst factor" size="4" start="20" type="Blend Factor"/>
     <field name="Color blend src factor" size="4" start="16" type="Blend Factor"/>
@@ -627,7 +627,7 @@
     <field name="address" size="32" start="0" type="address"/>
   </packet>
 
-  <packet code="96" name="Configuration Bits">
+  <packet code="96" name="Cfg Bits">
     <field name="Direct3D Provoking Vertex" size="1" start="21" type="bool"/>
     <field name="Direct3D 'Point-fill' mode" size="1" start="20" type="bool"/>
     <field name="Blend enable" size="1" start="19" type="bool"/>
@@ -720,7 +720,7 @@
     <field name="Number of Layers" size="8" start="0" type="uint" minus_one="true"/>
   </packet>
 
-  <packet code="120" name="Tile Binning Mode Configuration (Part1)" max_ver="33">
+  <packet code="120" name="Tile Binning Mode Cfg (Part1)" max_ver="33">
     <field name="Double-buffer in non-ms mode" size="1" start="63" type="bool"/>
     <field name="Multisample Mode (4x)" size="1" start="62" type="bool"/>
 
@@ -746,7 +746,7 @@
     <field name="sub-id" size="1" start="0" type="uint" default="0"/>
   </packet>
 
-  <packet code="120" name="Tile Binning Mode Configuration (Part1)" min_ver="41">
+  <packet code="120" name="Tile Binning Mode Cfg" min_ver="41">
 
     <field name="Height (in pixels)" size="12" start="48" type="uint" minus_one="true"/>
     <field name="Width (in pixels)" size="12" start="32" type="uint" minus_one="true"/>
@@ -774,14 +774,14 @@
     </field>
   </packet>
 
-  <packet code="120" name="Tile Binning Mode Configuration (Part2)" cl="B" max_ver="33">
+  <packet code="120" name="Tile Binning Mode Cfg (Part2)" cl="B" max_ver="33">
     <field name="Tile Allocation Memory Address" size="32" start="32" type="address"/>
     <field name="Tile Allocation Memory Size" size="32" start="0" type="uint"/>
 
     <field name="sub-id" size="1" start="0" type="uint" default="1"/>
   </packet>
 
-  <packet code="121" name="Tile Rendering Mode Configuration (Common Configuration)" cl="R" max_ver="33">
+  <packet code="121" name="Tile Rendering Mode Cfg (Common)" cl="R" max_ver="33">
     <field name="Disable Render Target Stores" size="8" start="56" type="uint"/>
     <field name="Enable Z Store" size="1" start="55" type="bool"/>
     <field name="Enable Stencil Store" size="1" start="54" type="bool"/>
@@ -809,7 +809,7 @@
     <field name="sub-id" size="4" start="0" type="uint" default="0"/>
   </packet>
 
-  <packet code="121" name="Tile Rendering Mode Configuration (Common Configuration)" cl="R" min_ver="41">
+  <packet code="121" name="Tile Rendering Mode Cfg (Common)" cl="R" min_ver="41">
     <field name="Pad" size="12" start="52" type="uint"/>
 
     <field name="Early Depth/Stencil Clear" size="1" start="51" type="bool"/>
@@ -834,7 +834,7 @@
     <field name="sub-id" size="4" start="0" type="uint" default="0"/>
   </packet>
 
-  <packet code="121" name="Tile Rendering Mode Configuration (Render Target config)" cl="R" max_ver="33">
+  <packet code="121" name="Tile Rendering Mode Cfg (Color)" cl="R" max_ver="33">
     <field name="Address" size="32" start="32" type="address"/>
 
     <field name="Pad" size="4" start="28" type="uint"/>
@@ -855,7 +855,7 @@
     <field name="sub-id" size="4" start="0" type="uint" default="2"/>
   </packet>
 
-  <packet code="121" name="Tile Rendering Mode Configuration (Render Target config)" cl="R" min_ver="41">
+  <packet code="121" name="Tile Rendering Mode Cfg (Color)" cl="R" min_ver="41">
 
     <field name="Pad" size="28" start="34" type="uint"/>
 
@@ -878,7 +878,7 @@
     <field name="sub-id" size="4" start="0" type="uint" default="1"/>
   </packet>
 
-  <packet code="121" name="Tile Rendering Mode Configuration (Z/Stencil config)" cl="R" max_ver="33">
+  <packet code="121" name="Tile Rendering Mode Cfg (Z/Stencil)" cl="R" max_ver="33">
     <field name="Address" size="26" start="38" type="address"/>
 
     <field name="Padded height of output image in UIF blocks" size="13" start="25" type="uint"/>
@@ -897,7 +897,7 @@
     <field name="sub-id" size="4" start="0" type="uint" default="1"/>
   </packet>
 
-  <packet code="121" name="Tile Rendering Mode Configuration (Z Stencil Clear Values)" cl="R" max_ver="33">
+  <packet code="121" name="Tile Rendering Mode Cfg (ZS Clear Values)" cl="R" max_ver="33">
     <field name="unused" size="16" start="48" type="uint"/>
 
     <field name="Z Clear Value" size="32" start="16" type="float"/>
@@ -906,7 +906,7 @@
     <field name="sub-id" size="4" start="0" type="uint" default="3"/>
   </packet>
 
-  <packet code="121" name="Tile Rendering Mode Configuration (Z Stencil Clear Values)" cl="R" min_ver="41">
+  <packet code="121" name="Tile Rendering Mode Cfg (ZS Clear Values)" cl="R" min_ver="41">
     <field name="unused" size="16" start="48" type="uint"/>
 
     <field name="Z Clear Value" size="32" start="16" type="float"/>
@@ -915,7 +915,7 @@
     <field name="sub-id" size="4" start="0" type="uint" default="2"/>
   </packet>
 
-  <packet code="121" name="Tile Rendering Mode Configuration (Clear Colors Part1)" cl="R" max_ver="33">
+  <packet code="121" name="Tile Rendering Mode Cfg (Clear Colors Part1)" cl="R" max_ver="33">
     <!-- Express this as a 56-bit field? -->
     <field name="Clear Color next 24 bits" size="24" start="40" type="uint"/>
     <field name="Clear Color low 32 bits" size="32" start="8" type="uint"/>
@@ -924,7 +924,7 @@
     <field name="sub-id" size="4" start="0" type="uint" default="4"/>
   </packet>
 
-  <packet code="121" name="Tile Rendering Mode Configuration (Clear Colors Part1)" cl="R" min_ver="41">
+  <packet code="121" name="Tile Rendering Mode Cfg (Clear Colors Part1)" cl="R" min_ver="41">
     <!-- Express this as a 56-bit field? -->
     <field name="Clear Color next 24 bits" size="24" start="40" type="uint"/>
     <field name="Clear Color low 32 bits" size="32" start="8" type="uint"/>
@@ -933,7 +933,7 @@
     <field name="sub-id" size="4" start="0" type="uint" default="3"/>
   </packet>
 
-  <packet code="121" name="Tile Rendering Mode Configuration (Clear Colors Part2)" cl="R" max_ver="33">
+  <packet code="121" name="Tile Rendering Mode Cfg (Clear Colors Part2)" cl="R" max_ver="33">
     <!-- Express this as a 56-bit field? -->
     <field name="Clear Color mid-high 24 bits" size="24" start="40" type="uint"/>
     <field name="Clear Color mid-low 32 bits" size="32" start="8" type="uint"/>
@@ -942,7 +942,7 @@
     <field name="sub-id" size="4" start="0" type="uint" default="5"/>
   </packet>
 
-  <packet code="121" name="Tile Rendering Mode Configuration (Clear Colors Part2)" cl="R" min_ver="41">
+  <packet code="121" name="Tile Rendering Mode Cfg (Clear Colors Part2)" cl="R" min_ver="41">
     <!-- Express this as a 56-bit field? -->
     <field name="Clear Color mid-high 24 bits" size="24" start="40" type="uint"/>
     <field name="Clear Color mid-low 32 bits" size="32" start="8" type="uint"/>
@@ -951,7 +951,7 @@
     <field name="sub-id" size="4" start="0" type="uint" default="4"/>
   </packet>
 
-  <packet code="121" name="Tile Rendering Mode Configuration (Clear Colors Part3)" cl="R" max_ver="33">
+  <packet code="121" name="Tile Rendering Mode Cfg (Clear Colors Part3)" cl="R" max_ver="33">
     <field name="pad" size="11" start="53" type="uint"/>
     <field name="UIF padded height in UIF blocks" size="13" start="40" type="uint"/>
     <!-- image height is for Y flipping -->
@@ -962,7 +962,7 @@
     <field name="sub-id" size="4" start="0" type="uint" default="6"/>
   </packet>
 
-  <packet code="121" name="Tile Rendering Mode Configuration (Clear Colors Part3)" cl="R" min_ver="41">
+  <packet code="121" name="Tile Rendering Mode Cfg (Clear Colors Part3)" cl="R" min_ver="41">
     <field name="pad" size="11" start="53" type="uint"/>
     <field name="UIF padded height in UIF blocks" size="13" start="40" type="uint"/>
     <!-- image height is for Y flipping -->
@@ -978,7 +978,7 @@
     <field name="tile column number" size="12" start="0" type="uint"/>
   </packet>
 
-  <packet code="122" name="Multicore Rendering Supertile Configuration" cl="R">
+  <packet code="122" name="Multicore Rendering Supertile Cfg" cl="R">
     <field name="Number of Bin Tile Lists" size="3" start="61" type="uint" minus_one="true"/>
     <field name="Supertile Raster Order" size="1" start="60" type="bool"/>
     <field name="Multicore Enable" size="1" start="56" type="bool"/>

diff --git a/src/gallium/drivers/v3d/v3dx_draw.c b/src/gallium/drivers/v3d/v3dx_draw.c
index 03762e529dff53a23c884a2bf729a1956ae2008e..479adb70fdb8ad09a2a58729eb919713fbbead4c 100644 (file)
--- a/src/gallium/drivers/v3d/v3dx_draw.c
+++ b/src/gallium/drivers/v3d/v3dx_draw.c
@@ -63,26 +63,30 @@ v3d_start_draw(struct v3d_context *v3d)
                                        tsda_per_tile_size,
                                        "TSDA");
 
-#if V3D_VERSION < 40
+#if V3D_VERSION >= 40
+        cl_emit(&job->bcl, TILE_BINNING_MODE_CFG, config) {
+                config.width_in_pixels = v3d->framebuffer.width;
+                config.height_in_pixels = v3d->framebuffer.height;
+                config.number_of_render_targets =
+                        MAX2(v3d->framebuffer.nr_cbufs, 1);
+
+                config.multisample_mode_4x = job->msaa;
+
+                config.maximum_bpp_of_all_render_targets = job->internal_bpp;
+        }
+#else /* V3D_VERSION < 40 */
         /* "Binning mode lists start with a Tile Binning Mode Configuration
          * item (120)"
          *
          * Part1 signals the end of binning config setup.
          */
-        cl_emit(&job->bcl, TILE_BINNING_MODE_CONFIGURATION_PART2, config) {
+        cl_emit(&job->bcl, TILE_BINNING_MODE_CFG_PART2, config) {
                 config.tile_allocation_memory_address =
                         cl_address(job->tile_alloc, 0);
                 config.tile_allocation_memory_size = job->tile_alloc->size;
         }
-#endif
 
-        cl_emit(&job->bcl, TILE_BINNING_MODE_CONFIGURATION_PART1, config) {
-#if V3D_VERSION >= 40
-                config.width_in_pixels = v3d->framebuffer.width;
-                config.height_in_pixels = v3d->framebuffer.height;
-                config.number_of_render_targets =
-                        MAX2(v3d->framebuffer.nr_cbufs, 1);
-#else /* V3D_VERSION < 40 */
+        cl_emit(&job->bcl, TILE_BINNING_MODE_CFG_PART1, config) {
                 config.tile_state_data_array_base_address =
                         cl_address(job->tile_state, 0);
 
@@ -91,12 +95,12 @@ v3d_start_draw(struct v3d_context *v3d)
                 /* Must be >= 1 */
                 config.number_of_render_targets =
                         MAX2(v3d->framebuffer.nr_cbufs, 1);
-#endif /* V3D_VERSION < 40 */
 
                 config.multisample_mode_4x = job->msaa;
 
                 config.maximum_bpp_of_all_render_targets = job->internal_bpp;
         }
+#endif /* V3D_VERSION < 40 */
 
         /* There's definitely nothing in the VCD cache we want. */
         cl_emit(&job->bcl, FLUSH_VCD_CACHE, bin);

diff --git a/src/gallium/drivers/v3d/v3dx_emit.c b/src/gallium/drivers/v3d/v3dx_emit.c
index 59bcf126c78f0e6d222600bdbf7e7de9aaa25d98..c58ac4b44a2207cc3470b282655de438029cc95c 100644 (file)
--- a/src/gallium/drivers/v3d/v3dx_emit.c
+++ b/src/gallium/drivers/v3d/v3dx_emit.c
@@ -284,7 +284,7 @@ emit_rt_blend(struct v3d_context *v3d, struct v3d_job *job,
                 return;
 #endif
 
-        cl_emit(&job->bcl, BLEND_CONFIG, config) {
+        cl_emit(&job->bcl, BLEND_CFG, config) {
 #if V3D_VERSION >= 40
                 if (blend->independent_blend_enable)
                         config.render_target_mask = 1 << rt;
@@ -463,7 +463,7 @@ v3dX(emit_state)(struct pipe_context *pctx)
                           VC5_DIRTY_ZSA |
                           VC5_DIRTY_BLEND |
                           VC5_DIRTY_COMPILED_FS)) {
-                cl_emit(&job->bcl, CONFIGURATION_BITS, config) {
+                cl_emit(&job->bcl, CFG_BITS, config) {
                         config.enable_forward_facing_primitive =
                                 !rasterizer_discard &&
                                 !(v3d->rasterizer->base.cull_face &
@@ -630,7 +630,7 @@ v3dX(emit_state)(struct pipe_context *pctx)
                 struct pipe_stencil_state *back = &v3d->zsa->base.stencil[1];
 
                 if (front->enabled) {
-                        cl_emit_with_prepacked(&job->bcl, STENCIL_CONFIG,
+                        cl_emit_with_prepacked(&job->bcl, STENCIL_CFG,
                                                v3d->zsa->stencil_front, config) {
                                 config.stencil_ref_value =
                                         v3d->stencil_ref.ref_value[0];
@@ -638,7 +638,7 @@ v3dX(emit_state)(struct pipe_context *pctx)
                 }
 
                 if (back->enabled) {
-                        cl_emit_with_prepacked(&job->bcl, STENCIL_CONFIG,
+                        cl_emit_with_prepacked(&job->bcl, STENCIL_CFG,
                                                v3d->zsa->stencil_back, config) {
                                 config.stencil_ref_value =
                                         v3d->stencil_ref.ref_value[1];

diff --git a/src/gallium/drivers/v3d/v3dx_rcl.c b/src/gallium/drivers/v3d/v3dx_rcl.c
index acd6e9297e4d9d3d2ae34e145b6e439d6ce600ab..3a76b0f3b24ff2b972859009f57eae01132939d3 100644 (file)
--- a/src/gallium/drivers/v3d/v3dx_rcl.c
+++ b/src/gallium/drivers/v3d/v3dx_rcl.c
@@ -457,7 +457,7 @@ static void
 v3d_emit_z_stencil_config(struct v3d_job *job, struct v3d_surface *surf,
                           struct v3d_resource *rsc, bool is_separate_stencil)
 {
-        cl_emit(&job->rcl, TILE_RENDERING_MODE_CONFIGURATION_Z_STENCIL_CONFIG, zs) {
+        cl_emit(&job->rcl, TILE_RENDERING_MODE_CFG_Z_STENCIL, zs) {
                 zs.address = cl_address(rsc->bo, surf->offset);
 
                 if (!is_separate_stencil) {
@@ -501,12 +501,11 @@ v3dX(emit_rcl)(struct v3d_job *job)
                         nr_cbufs = i + 1;
         }
 
-        /* Comon config must be the first TILE_RENDERING_MODE_CONFIGURATION
+        /* Comon config must be the first TILE_RENDERING_MODE_CFG
          * and Z_STENCIL_CLEAR_VALUES must be last.  The ones in between are
          * optional updates to the previous HW state.
          */
-        cl_emit(&job->rcl, TILE_RENDERING_MODE_CONFIGURATION_COMMON_CONFIGURATION,
-                config) {
+        cl_emit(&job->rcl, TILE_RENDERING_MODE_CFG_COMMON, config) {
 #if V3D_VERSION < 40
                 config.enable_z_store = job->store & PIPE_CLEAR_DEPTH;
                 config.enable_stencil_store = job->store & PIPE_CLEAR_STENCIL;
@@ -572,7 +571,7 @@ v3dX(emit_rcl)(struct v3d_job *job)
                 }
 
 #if V3D_VERSION < 40
-                cl_emit(&job->rcl, TILE_RENDERING_MODE_CONFIGURATION_RENDER_TARGET_CONFIG, rt) {
+                cl_emit(&job->rcl, TILE_RENDERING_MODE_CFG_COLOR, rt) {
                         rt.address = cl_address(rsc->bo, surf->offset);
                         rt.internal_type = surf->internal_type;
                         rt.output_image_format = surf->format;
@@ -586,7 +585,7 @@ v3dX(emit_rcl)(struct v3d_job *job)
                 }
 #endif /* V3D_VERSION < 40 */
 
-                cl_emit(&job->rcl, TILE_RENDERING_MODE_CONFIGURATION_CLEAR_COLORS_PART1,
+                cl_emit(&job->rcl, TILE_RENDERING_MODE_CFG_CLEAR_COLORS_PART1,
                         clear) {
                         clear.clear_color_low_32_bits = job->clear_color[i][0];
                         clear.clear_color_next_24_bits = job->clear_color[i][1] & 0xffffff;
@@ -594,7 +593,7 @@ v3dX(emit_rcl)(struct v3d_job *job)
                 };
 
                 if (surf->internal_bpp >= V3D_INTERNAL_BPP_64) {
-                        cl_emit(&job->rcl, TILE_RENDERING_MODE_CONFIGURATION_CLEAR_COLORS_PART2,
+                        cl_emit(&job->rcl, TILE_RENDERING_MODE_CFG_CLEAR_COLORS_PART2,
                                 clear) {
                                 clear.clear_color_mid_low_32_bits =
                                         ((job->clear_color[i][1] >> 24) |
@@ -607,7 +606,7 @@ v3dX(emit_rcl)(struct v3d_job *job)
                 }
 
                 if (surf->internal_bpp >= V3D_INTERNAL_BPP_128 || clear_pad) {
-                        cl_emit(&job->rcl, TILE_RENDERING_MODE_CONFIGURATION_CLEAR_COLORS_PART3,
+                        cl_emit(&job->rcl, TILE_RENDERING_MODE_CFG_CLEAR_COLORS_PART3,
                                 clear) {
                                 clear.uif_padded_height_in_uif_blocks = clear_pad;
                                 clear.clear_color_high_16_bits = job->clear_color[i][3] >> 16;
@@ -617,7 +616,7 @@ v3dX(emit_rcl)(struct v3d_job *job)
         }
 
 #if V3D_VERSION >= 40
-        cl_emit(&job->rcl, TILE_RENDERING_MODE_CONFIGURATION_RENDER_TARGET_CONFIG, rt) {
+        cl_emit(&job->rcl, TILE_RENDERING_MODE_CFG_COLOR, rt) {
                 v3d_setup_render_target(job, 0,
                                         &rt.render_target_0_internal_bpp,
                                         &rt.render_target_0_internal_type,
@@ -659,7 +658,7 @@ v3dX(emit_rcl)(struct v3d_job *job)
 #endif /* V3D_VERSION < 40 */
 
         /* Ends rendering mode config. */
-        cl_emit(&job->rcl, TILE_RENDERING_MODE_CONFIGURATION_Z_STENCIL_CLEAR_VALUES,
+        cl_emit(&job->rcl, TILE_RENDERING_MODE_CFG_ZS_CLEAR_VALUES,
                 clear) {
                 clear.z_clear_value = job->clear_z;
                 clear.stencil_clear_value = job->clear_s;
@@ -683,7 +682,7 @@ v3dX(emit_rcl)(struct v3d_job *job)
                 list.address = cl_address(job->tile_alloc, 0);
         }
 
-        cl_emit(&job->rcl, MULTICORE_RENDERING_SUPERTILE_CONFIGURATION, config) {
+        cl_emit(&job->rcl, MULTICORE_RENDERING_SUPERTILE_CFG, config) {
                 uint32_t frame_w_in_supertiles, frame_h_in_supertiles;
                 const uint32_t max_supertiles = 256;
 

diff --git a/src/gallium/drivers/v3d/v3dx_state.c b/src/gallium/drivers/v3d/v3dx_state.c
index a154936d048330b38de86c9d94e9ea65be29fc34..4bba8992c0072dd8fd975f8be30230ba5030d4b9 100644 (file)
--- a/src/gallium/drivers/v3d/v3dx_state.c
+++ b/src/gallium/drivers/v3d/v3dx_state.c
@@ -210,8 +210,8 @@ v3d_create_depth_stencil_alpha_state(struct pipe_context *pctx,
 
         if (front->enabled) {
                 STATIC_ASSERT(sizeof(so->stencil_front) >=
-                              cl_packet_length(STENCIL_CONFIG));
-                v3dx_pack(&so->stencil_front, STENCIL_CONFIG, config) {
+                              cl_packet_length(STENCIL_CFG));
+                v3dx_pack(&so->stencil_front, STENCIL_CFG, config) {
                         config.front_config = true;
                         /* If !back->enabled, then the front values should be
                          * used for both front and back-facing primitives.
@@ -232,8 +232,8 @@ v3d_create_depth_stencil_alpha_state(struct pipe_context *pctx,
         }
         if (back->enabled) {
                 STATIC_ASSERT(sizeof(so->stencil_back) >=
-                              cl_packet_length(STENCIL_CONFIG));
-                v3dx_pack(&so->stencil_back, STENCIL_CONFIG, config) {
+                              cl_packet_length(STENCIL_CFG));
+                v3dx_pack(&so->stencil_back, STENCIL_CFG, config) {
                         config.front_config = false;
                         config.back_config = true;