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AVX-512. Extend vcvtps2ph insn patterns.
authorAlexander Ivchenko <alexander.ivchenko@intel.com>
Mon, 15 Sep 2014 11:36:54 +0000 (11:36 +0000)
committerKirill Yukhin <kyukhin@gcc.gnu.org>
Mon, 15 Sep 2014 11:36:54 +0000 (11:36 +0000)
gcc/
* config/i386/sse.md
(define_insn "vcvtph2ps<mask_name>"): Add masking.
(define_insn "*vcvtph2ps_load<mask_name>"): Ditto.
(define_insn "vcvtph2ps256<mask_name>"): Ditto.
(define_expand "vcvtps2ph_mask"): New.
(define_insn "*vcvtps2ph<mask_name>"): Add masking.
(define_insn "*vcvtps2ph_store<mask_name>"): Ditto.
(define_insn "vcvtps2ph256<mask_name>"): Ditto.

Co-Authored-By: Andrey Turetskiy <andrey.turetskiy@intel.com>
Co-Authored-By: Anna Tikhonova <anna.tikhonova@intel.com>
Co-Authored-By: Ilya Tocar <ilya.tocar@intel.com>
Co-Authored-By: Ilya Verbin <ilya.verbin@intel.com>
Co-Authored-By: Kirill Yukhin <kirill.yukhin@intel.com>
Co-Authored-By: Maxim Kuznetsov <maxim.kuznetsov@intel.com>
Co-Authored-By: Michael Zolotukhin <michael.v.zolotukhin@intel.com>
From-SVN: r215263

gcc/ChangeLog patch | blob | history
gcc/config/i386/sse.md patch | blob | history

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 920e98f2b026c2aa946691f6450e464b55b76800..dfb70506e2c3de255819f07baacece7836bfcdaa 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,21 @@
+2014-09-15  Alexander Ivchenko  <alexander.ivchenko@intel.com>
+           Maxim Kuznetsov  <maxim.kuznetsov@intel.com>
+           Anna Tikhonova  <anna.tikhonova@intel.com>
+           Ilya Tocar  <ilya.tocar@intel.com>
+           Andrey Turetskiy  <andrey.turetskiy@intel.com>
+           Ilya Verbin  <ilya.verbin@intel.com>
+           Kirill Yukhin  <kirill.yukhin@intel.com>
+           Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
+
+       * config/i386/sse.md
+       (define_insn "vcvtph2ps<mask_name>"): Add masking.
+       (define_insn "*vcvtph2ps_load<mask_name>"): Ditto.
+       (define_insn "vcvtph2ps256<mask_name>"): Ditto.
+       (define_expand "vcvtps2ph_mask"): New.
+       (define_insn "*vcvtps2ph<mask_name>"): Add masking.
+       (define_insn "*vcvtps2ph_store<mask_name>"): Ditto.
+       (define_insn "vcvtps2ph256<mask_name>"): Ditto.
+
 2014-09-15  Alexander Ivchenko  <alexander.ivchenko@intel.com>
            Maxim Kuznetsov  <maxim.kuznetsov@intel.com>
            Anna Tikhonova  <anna.tikhonova@intel.com>
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index b5ded79a0e89a62098cf9e24d046dccaadc9c8b8..bd321fcefc063f331194b8e5ccd2a61e61eeefa0 100644 (file)
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -16423,35 +16423,35 @@
    (set_attr "prefix" "maybe_evex")
    (set_attr "mode" "<sseinsnmode>")])
 
-(define_insn "vcvtph2ps"
-  [(set (match_operand:V4SF 0 "register_operand" "=x")
+(define_insn "vcvtph2ps<mask_name>"
+  [(set (match_operand:V4SF 0 "register_operand" "=v")
        (vec_select:V4SF
-         (unspec:V8SF [(match_operand:V8HI 1 "register_operand" "x")]
+         (unspec:V8SF [(match_operand:V8HI 1 "register_operand" "v")]
                       UNSPEC_VCVTPH2PS)
          (parallel [(const_int 0) (const_int 1)
                     (const_int 2) (const_int 3)])))]
-  "TARGET_F16C"
-  "vcvtph2ps\t{%1, %0|%0, %1}"
+  "TARGET_F16C || TARGET_AVX512VL"
+  "vcvtph2ps\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
   [(set_attr "type" "ssecvt")
-   (set_attr "prefix" "vex")
+   (set_attr "prefix" "maybe_evex")
    (set_attr "mode" "V4SF")])
 
-(define_insn "*vcvtph2ps_load"
-  [(set (match_operand:V4SF 0 "register_operand" "=x")
+(define_insn "*vcvtph2ps_load<mask_name>"
+  [(set (match_operand:V4SF 0 "register_operand" "=v")
        (unspec:V4SF [(match_operand:V4HI 1 "memory_operand" "m")]
                     UNSPEC_VCVTPH2PS))]
-  "TARGET_F16C"
-  "vcvtph2ps\t{%1, %0|%0, %1}"
+  "TARGET_F16C || TARGET_AVX512VL"
+  "vcvtph2ps\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
   [(set_attr "type" "ssecvt")
    (set_attr "prefix" "vex")
    (set_attr "mode" "V8SF")])
 
-(define_insn "vcvtph2ps256"
-  [(set (match_operand:V8SF 0 "register_operand" "=x")
-       (unspec:V8SF [(match_operand:V8HI 1 "nonimmediate_operand" "xm")]
+(define_insn "vcvtph2ps256<mask_name>"
+  [(set (match_operand:V8SF 0 "register_operand" "=v")
+       (unspec:V8SF [(match_operand:V8HI 1 "nonimmediate_operand" "vm")]
                     UNSPEC_VCVTPH2PS))]
-  "TARGET_F16C"
-  "vcvtph2ps\t{%1, %0|%0, %1}"
+  "TARGET_F16C || TARGET_AVX512VL"
+  "vcvtph2ps\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
   [(set_attr "type" "ssecvt")
    (set_attr "prefix" "vex")
    (set_attr "btver2_decode" "double")
@@ -16468,6 +16468,19 @@
    (set_attr "prefix" "evex")
    (set_attr "mode" "V16SF")])
 
+(define_expand "vcvtps2ph_mask"
+  [(set (match_operand:V8HI 0 "register_operand")
+       (vec_merge:V8HI
+         (vec_concat:V8HI
+           (unspec:V4HI [(match_operand:V4SF 1 "register_operand")
+                         (match_operand:SI 2 "const_0_to_255_operand")]
+                         UNSPEC_VCVTPS2PH)
+           (match_dup 5))
+          (match_operand:V8HI 3 "vector_move_operand")
+          (match_operand:QI 4 "register_operand")))]
+  "TARGET_AVX512VL"
+  "operands[5] = CONST0_RTX (V4HImode);")
+
 (define_expand "vcvtps2ph"
   [(set (match_operand:V8HI 0 "register_operand")
        (vec_concat:V8HI
@@ -16478,39 +16491,39 @@
   "TARGET_F16C"
   "operands[3] = CONST0_RTX (V4HImode);")
 
-(define_insn "*vcvtps2ph"
-  [(set (match_operand:V8HI 0 "register_operand" "=x")
+(define_insn "*vcvtps2ph<mask_name>"
+  [(set (match_operand:V8HI 0 "register_operand" "=v")
        (vec_concat:V8HI
-         (unspec:V4HI [(match_operand:V4SF 1 "register_operand" "x")
+         (unspec:V4HI [(match_operand:V4SF 1 "register_operand" "v")
                        (match_operand:SI 2 "const_0_to_255_operand" "N")]
                       UNSPEC_VCVTPS2PH)
          (match_operand:V4HI 3 "const0_operand")))]
-  "TARGET_F16C"
-  "vcvtps2ph\t{%2, %1, %0|%0, %1, %2}"
+  "TARGET_F16C && <mask_avx512vl_condition>"
+  "vcvtps2ph\t{%2, %1, %0<mask_operand4>|%0<mask_operand4>, %1, %2}"
   [(set_attr "type" "ssecvt")
-   (set_attr "prefix" "vex")
+   (set_attr "prefix" "maybe_evex")
    (set_attr "mode" "V4SF")])
 
-(define_insn "*vcvtps2ph_store"
+(define_insn "*vcvtps2ph_store<mask_name>"
   [(set (match_operand:V4HI 0 "memory_operand" "=m")
        (unspec:V4HI [(match_operand:V4SF 1 "register_operand" "x")
                      (match_operand:SI 2 "const_0_to_255_operand" "N")]
                     UNSPEC_VCVTPS2PH))]
-  "TARGET_F16C"
-  "vcvtps2ph\t{%2, %1, %0|%0, %1, %2}"
+  "TARGET_F16C || TARGET_AVX512VL"
+  "vcvtps2ph\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
   [(set_attr "type" "ssecvt")
-   (set_attr "prefix" "vex")
+   (set_attr "prefix" "maybe_evex")
    (set_attr "mode" "V4SF")])
 
-(define_insn "vcvtps2ph256"
+(define_insn "vcvtps2ph256<mask_name>"
   [(set (match_operand:V8HI 0 "nonimmediate_operand" "=xm")
        (unspec:V8HI [(match_operand:V8SF 1 "register_operand" "x")
                      (match_operand:SI 2 "const_0_to_255_operand" "N")]
                     UNSPEC_VCVTPS2PH))]
-  "TARGET_F16C"
-  "vcvtps2ph\t{%2, %1, %0|%0, %1, %2}"
+  "TARGET_F16C || TARGET_AVX512VL"
+  "vcvtps2ph\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
   [(set_attr "type" "ssecvt")
-   (set_attr "prefix" "vex")
+   (set_attr "prefix" "maybe_evex")
    (set_attr "btver2_decode" "vector")
    (set_attr "mode" "V8SF")])