system.cpu0.iew.iewIQFullEvents 24728 # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents 127466 # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents 18891 # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect 275684 # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedTakenIncorrect 275682 # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect 374727 # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts 650411 # Number of branch mispredicts detected at execute
+system.cpu0.iew.branchMispredicts 650409 # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts 126563046 # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts 22955767 # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts 966765 # Number of squashed instructions skipped in execute
system.physmem_0.readEnergy 362653200 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 256666320 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 178852415040 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 68967490005 # Energy for active background per rank (pJ)
+system.physmem_0.actBackEnergy 68967548145 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 1611945575250 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 1860586561230 # Total energy per rank (pJ)
-system.physmem_0.averagePower 667.497599 # Core power per rank (mW)
+system.physmem_0.totalEnergy 1860586619370 # Total energy per rank (pJ)
+system.physmem_0.averagePower 667.497600 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 2632498894488 # Time in different power states
system.physmem_0.memoryStateTime::REF 91437840000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
---------- Begin Simulation Statistics ----------
+sim_seconds 51.111153 # Number of seconds simulated
+sim_ticks 51111152682000 # Number of ticks simulated
final_tick 51111152682000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-host_inst_rate 904753 # Simulator instruction rate (inst/s)
-host_mem_usage 665260 # Number of bytes of host memory used
-host_op_rate 1063233 # Simulator op (including micro ops) rate (op/s)
-host_seconds 1088.22 # Real time elapsed on the host
-host_tick_rate 46967646801 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 929959 # Simulator instruction rate (inst/s)
+host_op_rate 1092854 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 48276126697 # Simulator tick rate (ticks/s)
+host_mem_usage 712572 # Number of bytes of host memory used
+host_seconds 1058.73 # Real time elapsed on the host
sim_insts 984570519 # Number of instructions simulated
sim_ops 1157031967 # Number of ops (including micro ops) simulated
-sim_seconds 51.111153 # Number of seconds simulated
-sim_ticks 51111152682000 # Number of ticks simulated
-system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
+system.voltage_domain.voltage 1 # Voltage in Volts
+system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.bytes_read::cpu.dtb.walker 412352 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.itb.walker 376512 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst 5562740 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 74833672 # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide 441792 # Number of bytes read from this memory
+system.physmem.bytes_read::total 81627068 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 5562740 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 5562740 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 103042944 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory
+system.physmem.bytes_written::total 103063524 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.dtb.walker 6443 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.itb.walker 5883 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst 127325 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 1169289 # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide 6903 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 1315843 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 1610046 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 1612619 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.dtb.walker 8068 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker 7367 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 108836 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 1464136 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide 8644 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 1597050 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 108836 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 108836 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 2016056 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data 403 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 2016459 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 2016056 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker 8068 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.itb.walker 7367 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 108836 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 1464539 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide 8644 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 3613509 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bytes_read::cpu.inst 96 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu.inst 96 # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total 96 # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu.inst 24 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::cpu.data 5 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total 29 # Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu.inst 2 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::cpu.data 1 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total 3 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu.inst 2 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total 2 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu.inst 2 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total 3 # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
+system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
-system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes.
+system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 1669 # Number of DMA write transactions.
-system.clk_domain.clock 1000 # Clock period in ticks
-system.cpu.Branches 220088562 # Number of branches fetched
-system.cpu.committedInsts 984570519 # Number of instructions committed
-system.cpu.committedOps 1157031967 # Number of ops (including micro ops) committed
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4564266 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 4564266 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 4310545 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 4310545 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.055589 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total 0.055589 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data 253721 # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total 253721 # number of LoadLockedReq misses
-system.cpu.dcache.ReadReq_accesses::cpu.data 177577339 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 177577339 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_hits::cpu.data 171567259 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 171567259 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.033845 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.033845 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses::cpu.data 6010080 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 6010080 # number of ReadReq misses
-system.cpu.dcache.SoftPFReq_accesses::cpu.data 2008417 # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total 2008417 # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_hits::cpu.data 424020 # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total 424020 # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.788879 # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total 0.788879 # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_misses::cpu.data 1584397 # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total 1584397 # number of SoftPFReq misses
-system.cpu.dcache.StoreCondReq_accesses::cpu.data 4562465 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total 4562465 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_hits::cpu.data 4562464 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 4562464 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000000 # miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::total 0.000000 # miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_misses::cpu.data 1 # number of StoreCondReq misses
-system.cpu.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses
-system.cpu.dcache.WriteInvalidateReq_accesses::cpu.data 1583058 # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu.dcache.WriteInvalidateReq_accesses::total 1583058 # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu.dcache.WriteInvalidateReq_hits::cpu.data 337709 # number of WriteInvalidateReq hits
-system.cpu.dcache.WriteInvalidateReq_hits::total 337709 # number of WriteInvalidateReq hits
-system.cpu.dcache.WriteInvalidateReq_miss_rate::cpu.data 0.786673 # miss rate for WriteInvalidateReq accesses
-system.cpu.dcache.WriteInvalidateReq_miss_rate::total 0.786673 # miss rate for WriteInvalidateReq accesses
-system.cpu.dcache.WriteInvalidateReq_misses::cpu.data 1245349 # number of WriteInvalidateReq misses
-system.cpu.dcache.WriteInvalidateReq_misses::total 1245349 # number of WriteInvalidateReq misses
-system.cpu.dcache.WriteReq_accesses::cpu.data 162093127 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 162093127 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_hits::cpu.data 159522870 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 159522870 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015857 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.015857 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses::cpu.data 2570257 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 2570257 # number of WriteReq misses
-system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses::cpu.data 339670466 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 339670466 # number of demand (read+write) accesses
-system.cpu.dcache.demand_hits::cpu.data 331090129 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 331090129 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_rate::cpu.data 0.025261 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.025261 # miss rate for demand accesses
-system.cpu.dcache.demand_misses::cpu.data 8580337 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 8580337 # number of demand (read+write) misses
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses::cpu.data 341678883 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 341678883 # number of overall (read+write) accesses
-system.cpu.dcache.overall_hits::cpu.data 331514149 # number of overall hits
-system.cpu.dcache.overall_hits::total 331514149 # number of overall hits
-system.cpu.dcache.overall_miss_rate::cpu.data 0.029749 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.029749 # miss rate for overall accesses
-system.cpu.dcache.overall_misses::cpu.data 10164734 # number of overall misses
-system.cpu.dcache.overall_misses::total 10164734 # number of overall misses
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 198 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 299 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2 15 # Occupied blocks per task id
-system.cpu.dcache.tags.avg_refs 29.345233 # Average number of references to valid blocks.
-system.cpu.dcache.tags.data_accesses 1421167352 # Number of data accesses
-system.cpu.dcache.tags.occ_blocks::cpu.data 511.999719 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.replacements 11612141 # number of replacements
-system.cpu.dcache.tags.sampled_refs 11612653 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.tag_accesses 1421167352 # Number of tag accesses
-system.cpu.dcache.tags.tagsinuse 511.999719 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 340776008 # Total number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle 33050500 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks::writebacks 8921315 # number of writebacks
-system.cpu.dcache.writebacks::total 8921315 # number of writebacks
-system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
-system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
-system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
-system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
-system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
-system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
-system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
-system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
+system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
-system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
+system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
+system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
+system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
+system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
-system.cpu.dtb.accesses 352512518 # DTB accesses
-system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.flush_entries 82353 # Number of entries that have been flushed from TLB
-system.cpu.dtb.flush_tlb 11 # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_asid 1139 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid 49771 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.hits 352246803 # DTB hits
-system.cpu.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.dtb.inst_hits 0 # ITB inst hits
-system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.misses 265715 # DTB misses
-system.cpu.dtb.perms_faults 21651 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.prefetch_faults 9303 # Number of TLB faults due to prefetch
-system.cpu.dtb.read_accesses 184208233 # DTB read accesses
-system.cpu.dtb.read_hits 184014035 # DTB read hits
-system.cpu.dtb.read_misses 194198 # DTB read misses
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
+system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
+system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
+system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
+system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
+system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.dtb.walker.walks 265715 # Table walker walks requested
+system.cpu.dtb.walker.walksLong 265715 # Table walker walks initiated with long descriptors
+system.cpu.dtb.walker.walkWaitTime::samples 265715 # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::0 265715 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::total 265715 # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walksPending::samples 22846000 # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::0 22846000 100.00% 100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::total 22846000 # Table walker pending requests distribution
system.cpu.dtb.walker.walkPageSizes::4K 204282 89.47% 89.47% # Table walker page sizes translated
system.cpu.dtb.walker.walkPageSizes::2M 24037 10.53% 100.00% # Table walker page sizes translated
system.cpu.dtb.walker.walkPageSizes::total 228319 # Table walker page sizes translated
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 228319 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total 494034 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkWaitTime::samples 265715 # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::0 265715 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::total 265715 # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walks 265715 # Table walker walks requested
-system.cpu.dtb.walker.walksLong 265715 # Table walker walks initiated with long descriptors
-system.cpu.dtb.walker.walksPending::samples 22846000 # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::0 22846000 100.00% 100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::total 22846000 # Table walker pending requests distribution
-system.cpu.dtb.write_accesses 168304285 # DTB write accesses
+system.cpu.dtb.inst_hits 0 # ITB inst hits
+system.cpu.dtb.inst_misses 0 # ITB inst misses
+system.cpu.dtb.read_hits 184014035 # DTB read hits
+system.cpu.dtb.read_misses 194198 # DTB read misses
system.cpu.dtb.write_hits 168232768 # DTB write hits
system.cpu.dtb.write_misses 71517 # DTB write misses
-system.cpu.icache.ReadReq_accesses::cpu.inst 985162020 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 985162020 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_hits::cpu.inst 970865862 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 970865862 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014511 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.014511 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses::cpu.inst 14296158 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 14296158 # number of ReadReq misses
-system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses::cpu.inst 985162020 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 985162020 # number of demand (read+write) accesses
-system.cpu.icache.demand_hits::cpu.inst 970865862 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 970865862 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_rate::cpu.inst 0.014511 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.014511 # miss rate for demand accesses
-system.cpu.icache.demand_misses::cpu.inst 14296158 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 14296158 # number of demand (read+write) misses
-system.cpu.icache.fast_writes 0 # number of fast writes performed
-system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses::cpu.inst 985162020 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 985162020 # number of overall (read+write) accesses
-system.cpu.icache.overall_hits::cpu.inst 970865862 # number of overall hits
-system.cpu.icache.overall_hits::total 970865862 # number of overall hits
-system.cpu.icache.overall_miss_rate::cpu.inst 0.014511 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.014511 # miss rate for overall accesses
-system.cpu.icache.overall_misses::cpu.inst 14296158 # number of overall misses
-system.cpu.icache.overall_misses::total 14296158 # number of overall misses
-system.cpu.icache.tags.age_task_id_blocks_1024::0 169 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1 255 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2 88 # Occupied blocks per task id
-system.cpu.icache.tags.avg_refs 67.910987 # Average number of references to valid blocks.
-system.cpu.icache.tags.data_accesses 999458178 # Number of data accesses
-system.cpu.icache.tags.occ_blocks::cpu.inst 511.984599 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.999970 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.999970 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu.icache.tags.replacements 14295641 # number of replacements
-system.cpu.icache.tags.sampled_refs 14296153 # Sample count of references to valid blocks.
-system.cpu.icache.tags.tag_accesses 999458178 # Number of tag accesses
-system.cpu.icache.tags.tagsinuse 511.984599 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 970865862 # Total number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle 6061930000 # Cycle when the warmup percentage was hit.
-system.cpu.idle_fraction 0.988675 # Percentage of idle cycles
-system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
-system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
-system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
-system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
-system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
-system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
-system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
-system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
+system.cpu.dtb.flush_tlb 11 # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid 49771 # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid 1139 # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries 82353 # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults 9303 # Number of TLB faults due to prefetch
+system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.dtb.perms_faults 21651 # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses 184208233 # DTB read accesses
+system.cpu.dtb.write_accesses 168304285 # DTB write accesses
+system.cpu.dtb.inst_accesses 0 # ITB inst accesses
+system.cpu.dtb.hits 352246803 # DTB hits
+system.cpu.dtb.misses 265715 # DTB misses
+system.cpu.dtb.accesses 352512518 # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
-system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
+system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
+system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
+system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
+system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
-system.cpu.itb.accesses 985174158 # DTB accesses
-system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.flush_entries 58174 # Number of entries that have been flushed from TLB
-system.cpu.itb.flush_tlb 11 # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_asid 1139 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid 49771 # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.hits 985047321 # DTB hits
-system.cpu.itb.inst_accesses 985174158 # ITB inst accesses
-system.cpu.itb.inst_hits 985047321 # ITB inst hits
-system.cpu.itb.inst_misses 126837 # ITB inst misses
-system.cpu.itb.misses 126837 # DTB misses
-system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.itb.read_accesses 0 # DTB read accesses
-system.cpu.itb.read_hits 0 # DTB read hits
-system.cpu.itb.read_misses 0 # DTB read misses
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
+system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
+system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
+system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
+system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
+system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.itb.walker.walks 126837 # Table walker walks requested
+system.cpu.itb.walker.walksLong 126837 # Table walker walks initiated with long descriptors
+system.cpu.itb.walker.walkWaitTime::samples 126837 # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::0 126837 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::total 126837 # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walksPending::samples 22844500 # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::0 22844500 100.00% 100.00% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::total 22844500 # Table walker pending requests distribution
system.cpu.itb.walker.walkPageSizes::4K 113576 99.02% 99.02% # Table walker page sizes translated
system.cpu.itb.walker.walkPageSizes::2M 1123 0.98% 100.00% # Table walker page sizes translated
system.cpu.itb.walker.walkPageSizes::total 114699 # Table walker page sizes translated
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 114699 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total 114699 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total 241536 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkWaitTime::samples 126837 # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::0 126837 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::total 126837 # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walks 126837 # Table walker walks requested
-system.cpu.itb.walker.walksLong 126837 # Table walker walks initiated with long descriptors
-system.cpu.itb.walker.walksPending::samples 22844500 # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::0 22844500 100.00% 100.00% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::total 22844500 # Table walker pending requests distribution
-system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.inst_hits 985047321 # ITB inst hits
+system.cpu.itb.inst_misses 126837 # ITB inst misses
+system.cpu.itb.read_hits 0 # DTB read hits
+system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
+system.cpu.itb.flush_tlb 11 # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid 49771 # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid 1139 # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries 58174 # Number of entries that have been flushed from TLB
+system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.itb.read_accesses 0 # DTB read accesses
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.inst_accesses 985174158 # ITB inst accesses
+system.cpu.itb.hits 985047321 # DTB hits
+system.cpu.itb.misses 126837 # DTB misses
+system.cpu.itb.accesses 985174158 # DTB accesses
+system.cpu.numCycles 102222322140 # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.committedInsts 984570519 # Number of instructions committed
+system.cpu.committedOps 1157031967 # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses 1060455466 # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses 880805 # Number of float alu accesses
+system.cpu.num_func_calls 57056367 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 151940834 # number of instructions that are conditional controls
+system.cpu.num_int_insts 1060455466 # number of integer instructions
+system.cpu.num_fp_insts 880805 # number of float instructions
+system.cpu.num_int_register_reads 1564002170 # number of times the integer registers were read
+system.cpu.num_int_register_writes 842444791 # number of times the integer registers were written
+system.cpu.num_fp_register_reads 1418999 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 747920 # number of times the floating registers were written
+system.cpu.num_cc_register_reads 264407058 # number of times the CC registers were read
+system.cpu.num_cc_register_writes 263829403 # number of times the CC registers were written
+system.cpu.num_mem_refs 352465606 # number of memory refs
+system.cpu.num_load_insts 184180431 # Number of load instructions
+system.cpu.num_store_insts 168285175 # Number of store instructions
+system.cpu.num_idle_cycles 101064643603.520065 # Number of idle cycles
+system.cpu.num_busy_cycles 1157678536.479939 # Number of busy cycles
+system.cpu.not_idle_fraction 0.011325 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0.988675 # Percentage of idle cycles
+system.cpu.Branches 220088562 # Number of branches fetched
+system.cpu.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction
+system.cpu.op_class::IntAlu 802636616 69.33% 69.33% # Class of executed instruction
+system.cpu.op_class::IntMult 2354747 0.20% 69.54% # Class of executed instruction
+system.cpu.op_class::IntDiv 101759 0.01% 69.54% # Class of executed instruction
+system.cpu.op_class::FloatAdd 0 0.00% 69.54% # Class of executed instruction
+system.cpu.op_class::FloatCmp 0 0.00% 69.54% # Class of executed instruction
+system.cpu.op_class::FloatCvt 0 0.00% 69.54% # Class of executed instruction
+system.cpu.op_class::FloatMult 0 0.00% 69.54% # Class of executed instruction
+system.cpu.op_class::FloatDiv 0 0.00% 69.54% # Class of executed instruction
+system.cpu.op_class::FloatSqrt 0 0.00% 69.54% # Class of executed instruction
+system.cpu.op_class::SimdAdd 0 0.00% 69.54% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc 0 0.00% 69.54% # Class of executed instruction
+system.cpu.op_class::SimdAlu 0 0.00% 69.54% # Class of executed instruction
+system.cpu.op_class::SimdCmp 0 0.00% 69.54% # Class of executed instruction
+system.cpu.op_class::SimdCvt 0 0.00% 69.54% # Class of executed instruction
+system.cpu.op_class::SimdMisc 0 0.00% 69.54% # Class of executed instruction
+system.cpu.op_class::SimdMult 0 0.00% 69.54% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc 0 0.00% 69.54% # Class of executed instruction
+system.cpu.op_class::SimdShift 0 0.00% 69.54% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc 0 0.00% 69.54% # Class of executed instruction
+system.cpu.op_class::SimdSqrt 0 0.00% 69.54% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd 8 0.00% 69.54% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu 0 0.00% 69.54% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp 13 0.00% 69.54% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt 21 0.00% 69.54% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv 0 0.00% 69.54% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc 107822 0.01% 69.55% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult 0 0.00% 69.55% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc 0 0.00% 69.55% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt 0 0.00% 69.55% # Class of executed instruction
+system.cpu.op_class::MemRead 184180431 15.91% 85.46% # Class of executed instruction
+system.cpu.op_class::MemWrite 168285175 14.54% 100.00% # Class of executed instruction
+system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
+system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
+system.cpu.op_class::total 1157666593 # Class of executed instruction
system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.kern.inst.quiesce 16775 # number of quiesce instructions executed
-system.cpu.l2cache.ReadExReq_accesses::cpu.data 2519117 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total 2519117 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_hits::cpu.data 1692610 # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total 1692610 # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.328094 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total 0.328094 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses::cpu.data 826507 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total 826507 # number of ReadExReq misses
-system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 513055 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 261506 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.inst 14296158 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data 7848198 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total 22918917 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.tags.replacements 11612141 # number of replacements
+system.cpu.dcache.tags.tagsinuse 511.999719 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 340776008 # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs 11612653 # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 29.345233 # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle 33050500 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data 511.999719 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0 198 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1 299 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2 15 # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses 1421167352 # Number of tag accesses
+system.cpu.dcache.tags.data_accesses 1421167352 # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data 171567259 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 171567259 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 159522870 # number of WriteReq hits
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-system.cpu.l2cache.demand_misses::cpu.data 1170473 # number of demand (read+write) misses
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-system.cpu.l2cache.fast_writes 0 # number of fast writes performed
-system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.overall_accesses::cpu.dtb.walker 513055 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker 261506 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 14296158 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 10367315 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 25438034 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_hits::cpu.dtb.walker 506612 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.itb.walker 255623 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.inst 14211921 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data 9196842 # number of overall hits
-system.cpu.l2cache.overall_hits::total 24170998 # number of overall hits
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+system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.022497 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.005892 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.043827 # miss rate for ReadReq accesses
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+system.cpu.l2cache.WriteInvalidateReq_miss_rate::total 0.442459 # miss rate for WriteInvalidateReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.780544 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total 0.780544 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.328094 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total 0.328094 # miss rate for ReadExReq accesses
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system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.012558 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.022497 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005892 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.112900 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.049809 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses::cpu.dtb.walker 6443 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.itb.walker 5883 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.inst 84237 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data 1170473 # number of overall misses
-system.cpu.l2cache.overall_misses::total 1267036 # number of overall misses
-system.cpu.l2cache.tags.age_task_id_blocks_1023::4 278 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0 136 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1 588 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2715 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4911 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54669 # Occupied blocks per task id
-system.cpu.l2cache.tags.avg_refs 16.788135 # Average number of references to valid blocks.
-system.cpu.l2cache.tags.data_accesses 290307620 # Number of data accesses
-system.cpu.l2cache.tags.occ_blocks::writebacks 37141.715219 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 310.196824 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 443.735041 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 6261.263092 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 21184.952326 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks 0.566738 # Average percentage of cache occupancy
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-system.cpu.l2cache.tags.occ_task_id_blocks::1024 63019 # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1023 0.004242 # Percentage of cache occupancy per task id
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-system.cpu.l2cache.tags.replacements 1722692 # number of replacements
-system.cpu.l2cache.tags.sampled_refs 1785989 # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.tag_accesses 290307620 # Number of tag accesses
-system.cpu.l2cache.tags.tagsinuse 65341.862502 # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs 29983424 # Total number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle 395986000 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
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system.cpu.l2cache.writebacks::writebacks 1503415 # number of writebacks
system.cpu.l2cache.writebacks::total 1503415 # number of writebacks
-system.cpu.not_idle_fraction 0.011325 # Percentage of non-idle cycles
-system.cpu.numCycles 102222322140 # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.num_busy_cycles 1157678536.479939 # Number of busy cycles
-system.cpu.num_cc_register_reads 264407058 # number of times the CC registers were read
-system.cpu.num_cc_register_writes 263829403 # number of times the CC registers were written
-system.cpu.num_conditional_control_insts 151940834 # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses 880805 # Number of float alu accesses
-system.cpu.num_fp_insts 880805 # number of float instructions
-system.cpu.num_fp_register_reads 1418999 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 747920 # number of times the floating registers were written
-system.cpu.num_func_calls 57056367 # number of times a function call or return occured
-system.cpu.num_idle_cycles 101064643603.520065 # Number of idle cycles
-system.cpu.num_int_alu_accesses 1060455466 # Number of integer alu accesses
-system.cpu.num_int_insts 1060455466 # number of integer instructions
-system.cpu.num_int_register_reads 1564002170 # number of times the integer registers were read
-system.cpu.num_int_register_writes 842444791 # number of times the integer registers were written
-system.cpu.num_load_insts 184180431 # Number of load instructions
-system.cpu.num_mem_refs 352465606 # number of memory refs
-system.cpu.num_store_insts 168285175 # Number of store instructions
-system.cpu.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction
-system.cpu.op_class::IntAlu 802636616 69.33% 69.33% # Class of executed instruction
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-system.cpu.op_class::IntDiv 101759 0.01% 69.54% # Class of executed instruction
-system.cpu.op_class::FloatAdd 0 0.00% 69.54% # Class of executed instruction
-system.cpu.op_class::FloatCmp 0 0.00% 69.54% # Class of executed instruction
-system.cpu.op_class::FloatCvt 0 0.00% 69.54% # Class of executed instruction
-system.cpu.op_class::FloatMult 0 0.00% 69.54% # Class of executed instruction
-system.cpu.op_class::FloatDiv 0 0.00% 69.54% # Class of executed instruction
-system.cpu.op_class::FloatSqrt 0 0.00% 69.54% # Class of executed instruction
-system.cpu.op_class::SimdAdd 0 0.00% 69.54% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc 0 0.00% 69.54% # Class of executed instruction
-system.cpu.op_class::SimdAlu 0 0.00% 69.54% # Class of executed instruction
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-system.cpu.op_class::SimdMisc 0 0.00% 69.54% # Class of executed instruction
-system.cpu.op_class::SimdMult 0 0.00% 69.54% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc 0 0.00% 69.54% # Class of executed instruction
-system.cpu.op_class::SimdShift 0 0.00% 69.54% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc 0 0.00% 69.54% # Class of executed instruction
-system.cpu.op_class::SimdSqrt 0 0.00% 69.54% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd 8 0.00% 69.54% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu 0 0.00% 69.54% # Class of executed instruction
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-system.cpu.op_class::SimdFloatCvt 21 0.00% 69.54% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv 0 0.00% 69.54% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc 107822 0.01% 69.55% # Class of executed instruction
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-system.cpu.op_class::SimdFloatSqrt 0 0.00% 69.55% # Class of executed instruction
-system.cpu.op_class::MemRead 184180431 15.91% 85.46% # Class of executed instruction
-system.cpu.op_class::MemWrite 168285175 14.54% 100.00% # Class of executed instruction
-system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::total 1157666593 # Class of executed instruction
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.toL2Bus.trans_dist::ReadReq 23372119 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 23372119 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteReq 33606 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteResp 33606 # Transaction distribution
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+system.cpu.toL2Bus.trans_dist::UpgradeResp 51141 # Transaction distribution
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+system.cpu.toL2Bus.trans_dist::ReadExResp 2519117 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 28678566 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 32383245 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 758224 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 3032896 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6175776 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 2238699610 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 116338 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 36147883 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 3.003196 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.056441 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::3 36032362 99.68% 99.68% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::4 115521 0.32% 100.00% # Request fanout histogram
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-system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
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-system.cpu.toL2Bus.snoop_fanout::total 36147883 # Request fanout histogram
-system.cpu.toL2Bus.snoops 116338 # Total snoops (count)
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-system.cpu.toL2Bus.trans_dist::ReadResp 23372119 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteReq 33606 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteResp 33606 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback 8921315 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 1245349 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteInvalidateResp 1245349 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq 51140 # Transaction distribution
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-system.cpu.toL2Bus.trans_dist::UpgradeResp 51141 # Transaction distribution
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-system.cpu.toL2Bus.trans_dist::ReadExResp 2519117 # Transaction distribution
-system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu.toL2Bus.snoop_fanout::4 115521 0.32% 100.00% # Request fanout histogram
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+system.cpu.toL2Bus.snoop_fanout::total 36147883 # Request fanout histogram
+system.iobus.trans_dist::ReadReq 40246 # Transaction distribution
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system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47598 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total 7491976 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.trans_dist::ReadReq 40246 # Transaction distribution
-system.iobus.trans_dist::ReadResp 40246 # Transaction distribution
-system.iobus.trans_dist::WriteReq 136515 # Transaction distribution
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-system.iobus.trans_dist::WriteInvalidateResp 106664 # Transaction distribution
-system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
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system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
system.iocache.ReadReq_misses::realview.ide 8817 # number of ReadReq misses
system.iocache.ReadReq_misses::total 8854 # number of ReadReq misses
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system.iocache.WriteInvalidateReq_misses::realview.ide 106664 # number of WriteInvalidateReq misses
system.iocache.WriteInvalidateReq_misses::total 106664 # number of WriteInvalidateReq misses
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system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
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-system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
-system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
-system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
-system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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-system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
system.iocache.demand_accesses::realview.ide 8817 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 8857 # number of demand (read+write) accesses
-system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
-system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
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-system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
-system.iocache.demand_misses::realview.ide 8817 # number of demand (read+write) misses
-system.iocache.demand_misses::total 8857 # number of demand (read+write) misses
-system.iocache.fast_writes 0 # number of fast writes performed
-system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
system.iocache.overall_accesses::realview.ide 8817 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 8857 # number of overall (read+write) accesses
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+system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
+system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
+system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
+system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
+system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses
+system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
+system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
+system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
-system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
-system.iocache.overall_misses::realview.ide 8817 # number of overall misses
-system.iocache.overall_misses::total 8857 # number of overall misses
-system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
-system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
-system.iocache.tags.data_accesses 1039686 # Number of data accesses
-system.iocache.tags.occ_blocks::realview.ethernet 3.554599 # Average occupied blocks per requestor
-system.iocache.tags.occ_blocks::realview.ide 6.852510 # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ethernet 0.222162 # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::realview.ide 0.428282 # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total 0.650444 # Average percentage of cache occupancy
-system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
-system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
-system.iocache.tags.replacements 115463 # number of replacements
-system.iocache.tags.sampled_refs 115479 # Sample count of references to valid blocks.
-system.iocache.tags.tag_accesses 1039686 # Number of tag accesses
-system.iocache.tags.tagsinuse 10.407109 # Cycle average of tags in use
-system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
-system.iocache.tags.warmup_cycle 13082113302009 # Cycle when the warmup percentage was hit.
+system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.iocache.blocked::no_targets 0 # number of cycles access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.iocache.fast_writes 0 # number of fast writes performed
+system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.writebacks::writebacks 106631 # number of writebacks
system.iocache.writebacks::total 106631 # number of writebacks
+system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.membus.trans_dist::ReadReq 526062 # Transaction distribution
+system.membus.trans_dist::ReadResp 526062 # Transaction distribution
+system.membus.trans_dist::WriteReq 33606 # Transaction distribution
+system.membus.trans_dist::WriteResp 33606 # Transaction distribution
+system.membus.trans_dist::Writeback 1610046 # Transaction distribution
+system.membus.trans_dist::WriteInvalidateReq 657675 # Transaction distribution
+system.membus.trans_dist::WriteInvalidateResp 657675 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 40484 # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 40485 # Transaction distribution
+system.membus.trans_dist::ReadExReq 825948 # Transaction distribution
+system.membus.trans_dist::ReadExResp 825948 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122480 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6654 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14217536 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 14217536 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 227117498 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 3583537 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
system.membus.snoop_fanout::total 3583537 # Request fanout histogram
-system.membus.snoops 0 # Total snoops (count)
-system.membus.trans_dist::ReadReq 526062 # Transaction distribution
-system.membus.trans_dist::ReadResp 526062 # Transaction distribution
-system.membus.trans_dist::WriteReq 33606 # Transaction distribution
-system.membus.trans_dist::WriteResp 33606 # Transaction distribution
-system.membus.trans_dist::Writeback 1610046 # Transaction distribution
-system.membus.trans_dist::WriteInvalidateReq 657675 # Transaction distribution
-system.membus.trans_dist::WriteInvalidateResp 657675 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 40484 # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 40485 # Transaction distribution
-system.membus.trans_dist::ReadExReq 825948 # Transaction distribution
-system.membus.trans_dist::ReadExResp 825948 # Transaction distribution
-system.physmem.bw_inst_read::cpu.inst 108836 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 108836 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.dtb.walker 8068 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker 7367 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst 108836 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 1464136 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide 8644 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 1597050 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 2016056 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker 8068 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker 7367 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 108836 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 1464539 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide 8644 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 3613509 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_write::writebacks 2016056 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data 403 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 2016459 # Write bandwidth from this memory (bytes/s)
-system.physmem.bytes_inst_read::cpu.inst 5562740 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 5562740 # Number of instructions bytes read from this memory
-system.physmem.bytes_read::cpu.dtb.walker 412352 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.itb.walker 376512 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst 5562740 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 74833672 # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide 441792 # Number of bytes read from this memory
-system.physmem.bytes_read::total 81627068 # Number of bytes read from this memory
-system.physmem.bytes_written::writebacks 103042944 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory
-system.physmem.bytes_written::total 103063524 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.dtb.walker 6443 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.itb.walker 5883 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst 127325 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 1169289 # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide 6903 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 1315843 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 1610046 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 1612619 # Number of write requests responded to by this memory
-system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
-system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
-system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
-system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
-system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
-system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
-system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
-system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post
-system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
+system.realview.ethernet.txBytes 966 # Bytes Transmitted
+system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
+system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
+system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
+system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
-system.realview.ethernet.droppedPackets 0 # number of packets dropped
-system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
-system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
-system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
-system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
-system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
-system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
-system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
-system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
-system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
system.realview.ethernet.totBandwidth 151 # Total Bandwidth (bits/s)
+system.realview.ethernet.totPackets 3 # Total Packets
system.realview.ethernet.totBytes 966 # Total Bytes
system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s)
-system.realview.ethernet.totPackets 3 # Total Packets
-system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
+system.realview.ethernet.txBandwidth 151 # Transmit Bandwidth (bits/s)
+system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s)
+system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
+system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
+system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
+system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
+system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
+system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
+system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
-system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
-system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
-system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
-system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
+system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
+system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
+system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
+system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
-system.realview.ethernet.txBandwidth 151 # Transmit Bandwidth (bits/s)
-system.realview.ethernet.txBytes 966 # Bytes Transmitted
-system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
-system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s)
-system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
-system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
-system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
-system.realview.nvmem.bw_inst_read::cpu.inst 2 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total 2 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::cpu.inst 2 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::cpu.data 1 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total 3 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu.inst 2 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total 3 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bytes_inst_read::cpu.inst 96 # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total 96 # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_read::cpu.inst 96 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory
-system.realview.nvmem.num_reads::cpu.inst 24 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::cpu.data 5 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total 29 # Number of read requests responded to by this memory
-system.voltage_domain.voltage 1 # Voltage in Volts
+system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
+system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post
+system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
+system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
+system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
+system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
+system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
+system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
+system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
+system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
+system.realview.ethernet.droppedPackets 0 # number of packets dropped
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 5.154240 # Number of seconds simulated
-sim_ticks 5154239928000 # Number of ticks simulated
-final_tick 5154239928000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 5.162227 # Number of seconds simulated
+sim_ticks 5162226977000 # Number of ticks simulated
+final_tick 5162226977000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 177928 # Simulator instruction rate (inst/s)
-host_op_rate 351699 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2247974259 # Simulator tick rate (ticks/s)
-host_mem_usage 809460 # Number of bytes of host memory used
-host_seconds 2292.84 # Real time elapsed on the host
-sim_insts 407959851 # Number of instructions simulated
-sim_ops 806389826 # Number of ops (including micro ops) simulated
+host_inst_rate 127909 # Simulator instruction rate (inst/s)
+host_op_rate 252832 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1618521974 # Simulator tick rate (ticks/s)
+host_mem_usage 804704 # Number of bytes of host memory used
+host_seconds 3189.47 # Real time elapsed on the host
+sim_insts 407963408 # Number of instructions simulated
+sim_ops 806401326 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.dtb.walker 4224 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst 1048832 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 10760128 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.dtb.walker 4608 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.itb.walker 384 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst 1045376 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 10748480 # Number of bytes read from this memory
system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory
-system.physmem.bytes_read::total 11841856 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 1048832 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 1048832 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 9579968 # Number of bytes written to this memory
-system.physmem.bytes_written::total 9579968 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.dtb.walker 66 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst 16388 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 168127 # Number of read requests responded to by this memory
+system.physmem.bytes_read::total 11827200 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 1045376 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 1045376 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 9574464 # Number of bytes written to this memory
+system.physmem.bytes_written::total 9574464 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.dtb.walker 72 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.itb.walker 6 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst 16334 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 167945 # Number of read requests responded to by this memory
system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 185029 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 149687 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 149687 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.dtb.walker 820 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst 203489 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 2087627 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::pc.south_bridge.ide 5501 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 2297498 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 203489 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 203489 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1858658 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 1858658 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1858658 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker 820 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 203489 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 2087627 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::pc.south_bridge.ide 5501 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 4156156 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 185029 # Number of read requests accepted
-system.physmem.writeReqs 196407 # Number of write requests accepted
-system.physmem.readBursts 185029 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 196407 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 11835328 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 6528 # Total number of bytes read from write queue
-system.physmem.bytesWritten 10911872 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 11841856 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 12570048 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 102 # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts 25884 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 1735 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 11576 # Per bank write bursts
-system.physmem.perBankRdBursts::1 11057 # Per bank write bursts
-system.physmem.perBankRdBursts::2 12153 # Per bank write bursts
-system.physmem.perBankRdBursts::3 11198 # Per bank write bursts
-system.physmem.perBankRdBursts::4 11802 # Per bank write bursts
-system.physmem.perBankRdBursts::5 11348 # Per bank write bursts
-system.physmem.perBankRdBursts::6 11143 # Per bank write bursts
-system.physmem.perBankRdBursts::7 11153 # Per bank write bursts
-system.physmem.perBankRdBursts::8 11425 # Per bank write bursts
-system.physmem.perBankRdBursts::9 11213 # Per bank write bursts
-system.physmem.perBankRdBursts::10 11332 # Per bank write bursts
-system.physmem.perBankRdBursts::11 11504 # Per bank write bursts
-system.physmem.perBankRdBursts::12 11762 # Per bank write bursts
-system.physmem.perBankRdBursts::13 12902 # Per bank write bursts
-system.physmem.perBankRdBursts::14 11974 # Per bank write bursts
-system.physmem.perBankRdBursts::15 11385 # Per bank write bursts
-system.physmem.perBankWrBursts::0 11439 # Per bank write bursts
-system.physmem.perBankWrBursts::1 10429 # Per bank write bursts
-system.physmem.perBankWrBursts::2 10485 # Per bank write bursts
-system.physmem.perBankWrBursts::3 9453 # Per bank write bursts
-system.physmem.perBankWrBursts::4 11713 # Per bank write bursts
-system.physmem.perBankWrBursts::5 11103 # Per bank write bursts
-system.physmem.perBankWrBursts::6 10277 # Per bank write bursts
-system.physmem.perBankWrBursts::7 10587 # Per bank write bursts
-system.physmem.perBankWrBursts::8 10639 # Per bank write bursts
-system.physmem.perBankWrBursts::9 10347 # Per bank write bursts
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+system.physmem.bw_inst_read::cpu.inst 202505 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 202505 # Instruction read bandwidth from this memory (bytes/s)
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+system.physmem.bw_write::total 1854716 # Write bandwidth from this memory (bytes/s)
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
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-system.physmem.totGap 5154239876000 # Total gap between requests
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system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
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-system.physmem.bytesPerActivate::mean 309.148356 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 181.632665 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 329.613307 # Bytes accessed per row activation
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-system.physmem.bytesPerActivate::512-639 2982 4.05% 81.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 2040 2.77% 84.19% # Bytes accessed per row activation
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-system.physmem.bytesPerActivate::1024-1151 8911 12.11% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 73580 # Bytes accessed per row activation
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-system.physmem.rdPerTurnAround::mean 27.326437 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 584.974446 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047 6766 99.99% 99.99% # Reads before turning the bus around for writes
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-system.physmem.wrPerTurnAround::528-543 1 0.01% 99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::544-559 3 0.04% 99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::560-575 2 0.03% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 6767 # Writes before turning the bus around for reads
-system.physmem.totQLat 2002245948 # Total ticks spent queuing
-system.physmem.totMemAccLat 5469627198 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 924635000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 10827.22 # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total 6763 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 6763 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 25.198137 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 18.714181 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 42.096027 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-31 6327 93.55% 93.55% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-47 89 1.32% 94.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-63 13 0.19% 95.06% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-79 16 0.24% 95.30% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-95 24 0.35% 95.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-111 14 0.21% 95.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-127 33 0.49% 96.35% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-143 33 0.49% 96.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-159 38 0.56% 97.40% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-175 13 0.19% 97.59% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-191 44 0.65% 98.24% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::192-207 51 0.75% 98.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::208-223 15 0.22% 99.22% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::224-239 4 0.06% 99.28% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::240-255 1 0.01% 99.29% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::272-287 4 0.06% 99.35% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::288-303 2 0.03% 99.38% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::304-319 1 0.01% 99.39% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::320-335 1 0.01% 99.41% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::336-351 5 0.07% 99.48% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::352-367 22 0.33% 99.81% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::368-383 4 0.06% 99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::384-399 2 0.03% 99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::480-495 1 0.01% 99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::512-527 1 0.01% 99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::544-559 1 0.01% 99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::560-575 3 0.04% 99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::656-671 1 0.01% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 6763 # Writes before turning the bus around for reads
+system.physmem.totQLat 2002108102 # Total ticks spent queuing
+system.physmem.totMemAccLat 5465439352 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 923555000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 10839.14 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 29577.22 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 2.30 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 2.12 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 2.30 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 2.44 # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat 29589.14 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 2.29 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 2.11 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 2.29 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 2.43 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.03 # Data bus utilization in percentage
system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 23.30 # Average write queue length when enqueuing
-system.physmem.readRowHits 151945 # Number of row buffer hits during reads
-system.physmem.writeRowHits 129899 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 82.16 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 76.18 # Row buffer hit rate for writes
-system.physmem.avgGap 13512725.27 # Average gap between requests
-system.physmem.pageHitRate 79.29 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 271547640 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 148165875 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 713146200 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 553949280 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 336649428960 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 130302295830 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 2978239548750 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 3446878082535 # Total energy per rank (pJ)
-system.physmem_0.averagePower 668.747042 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 4954509635136 # Time in different power states
-system.physmem_0.memoryStateTime::REF 172111160000 # Time in different power states
+system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing
+system.physmem.avgWrQLen 24.03 # Average write queue length when enqueuing
+system.physmem.readRowHits 151806 # Number of row buffer hits during reads
+system.physmem.writeRowHits 129898 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 82.19 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 76.22 # Row buffer hit rate for writes
+system.physmem.avgGap 13544850.39 # Average gap between requests
+system.physmem.pageHitRate 79.32 # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy 269075520 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 146817000 # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy 709885800 # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy 550534320 # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy 337171211520 # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy 130425108030 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 2982925034250 # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy 3452197666440 # Total energy per rank (pJ)
+system.physmem_0.averagePower 668.742620 # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE 4962301533714 # Time in different power states
+system.physmem_0.memoryStateTime::REF 172377920000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 27619022864 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 27547412786 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem_1.actEnergy 284717160 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 155351625 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 729276600 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 550877760 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 336649428960 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 130834885590 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 2977772364750 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 3446976902445 # Total energy per rank (pJ)
-system.physmem_1.averagePower 668.766215 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 4953723422640 # Time in different power states
-system.physmem_1.memoryStateTime::REF 172111160000 # Time in different power states
+system.physmem_1.actEnergy 285987240 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 156044625 # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy 730852200 # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy 553754880 # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy 337171211520 # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy 131048206380 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 2982378456750 # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy 3452324513595 # Total energy per rank (pJ)
+system.physmem_1.averagePower 668.767192 # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE 4961386282222 # Time in different power states
+system.physmem_1.memoryStateTime::REF 172377920000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 28398444860 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 28457517778 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.cpu.branchPred.lookups 86886659 # Number of BP lookups
-system.cpu.branchPred.condPredicted 86886659 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 896606 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 80012064 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 78173158 # Number of BTB hits
+system.cpu.branchPred.lookups 86892140 # Number of BP lookups
+system.cpu.branchPred.condPredicted 86892140 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 896476 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 79993842 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 78175387 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 97.701714 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 1555790 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 180979 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 97.726756 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 1559595 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 180975 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
-system.cpu.numCycles 452015949 # number of cpu cycles simulated
+system.cpu.numCycles 451961239 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 27708415 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 429123541 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 86886659 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 79728948 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 420284778 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 1879978 # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles 144708 # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.MiscStallCycles 58405 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 207121 # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles 57 # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles 651 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 9181144 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 450119 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes 5089 # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples 449344124 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 1.884391 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.047300 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 27669643 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 429138859 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 86892140 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 79734982 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 420292054 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 1880326 # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles 139799 # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.MiscStallCycles 59635 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 206134 # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles 79 # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles 545 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 9182224 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 451305 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes 4827 # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples 449308052 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 1.884669 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.047434 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 283935319 63.19% 63.19% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 2153229 0.48% 63.67% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 72170843 16.06% 79.73% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 1584001 0.35% 80.08% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 2141625 0.48% 80.56% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 2336888 0.52% 81.08% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 1524270 0.34% 81.42% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 1887238 0.42% 81.84% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 81610711 18.16% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 283889001 63.18% 63.18% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 2152335 0.48% 63.66% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 72174656 16.06% 79.73% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 1583547 0.35% 80.08% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 2143406 0.48% 80.56% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 2336945 0.52% 81.08% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 1526578 0.34% 81.42% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 1885904 0.42% 81.84% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 81615680 18.16% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 449344124 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.192220 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.949355 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 23005123 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 267198709 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 150742142 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 7458161 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 939989 # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts 838443104 # Number of instructions handled by decode
-system.cpu.rename.SquashCycles 939989 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 25847202 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 224345308 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 13466568 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 154654216 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 30090841 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 834933758 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 459142 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 12335285 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents 199811 # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents 14823013 # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands 997303578 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 1813575837 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 1114848675 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 334 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 964352232 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 32951344 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 467055 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 470880 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 38821668 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 17323479 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 10180206 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 1295686 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 1069829 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 829469634 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 1196558 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 824230120 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 243416 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 23349289 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 36028466 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 151024 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 449344124 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 1.834296 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 2.415438 # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total 449308052 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.192256 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.949504 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 22960534 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 267201307 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 150748201 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 7457847 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 940163 # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts 838480362 # Number of instructions handled by decode
+system.cpu.rename.SquashCycles 940163 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 25806835 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 224389855 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 13453779 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 154655676 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 30061744 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 834963010 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 457566 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 12341140 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents 186586 # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents 14798192 # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands 997326822 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 1813638756 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 1114908706 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 291 # Number of floating rename lookups
+system.cpu.rename.CommittedMaps 964358255 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 32968562 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 467477 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 471287 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 38845539 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 17334604 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 10181445 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 1298649 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 1067040 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 829488885 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 1196680 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 824229235 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 243657 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 23357015 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 36101946 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 150898 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 449308052 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 1.834441 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 2.415481 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 265024726 58.98% 58.98% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 14037592 3.12% 62.10% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 9914300 2.21% 64.31% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 7059540 1.57% 65.88% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 74309398 16.54% 82.42% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 4399488 0.98% 83.40% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 72817937 16.21% 99.60% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 1206490 0.27% 99.87% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 574653 0.13% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 264987396 58.98% 58.98% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 14037441 3.12% 62.10% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 9917964 2.21% 64.31% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 7059297 1.57% 65.88% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 74310664 16.54% 82.42% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 4394298 0.98% 83.40% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 72818105 16.21% 99.60% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 1207897 0.27% 99.87% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 574990 0.13% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 449344124 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 449308052 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 1987162 71.98% 71.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 137 0.00% 71.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 645 0.02% 72.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 72.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 72.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 72.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 72.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 72.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 72.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 72.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 72.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 72.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 72.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 72.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 72.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 72.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 72.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 72.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 72.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 72.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 72.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 72.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 72.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 72.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 72.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 72.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 72.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 72.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 72.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 611861 22.16% 94.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 160804 5.82% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 1986642 71.94% 71.94% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 137 0.00% 71.95% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 673 0.02% 71.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 71.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 71.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 71.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 71.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 71.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 71.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 71.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 71.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 71.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 71.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 71.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 71.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 71.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 71.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 71.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 71.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 71.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 71.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 71.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 71.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 71.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 71.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 71.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 71.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 71.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 71.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 612859 22.19% 94.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 161094 5.83% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass 290308 0.04% 0.04% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 795868269 96.56% 96.59% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 150766 0.02% 96.61% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 125160 0.02% 96.63% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass 292031 0.04% 0.04% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 795863777 96.56% 96.59% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 150844 0.02% 96.61% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 125129 0.02% 96.63% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.63% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.63% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 92 0.00% 96.63% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 78 0.00% 96.63% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.63% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.63% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.63% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.63% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.63% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.63% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 18401922 2.23% 98.86% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 9393603 1.14% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 18406058 2.23% 98.86% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 9391318 1.14% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 824230120 # Type of FU issued
-system.cpu.iq.rate 1.823454 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 2760609 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.003349 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 2100807897 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 854027763 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 819692227 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 491 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 488 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 172 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 826700185 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 236 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 1868049 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 824229235 # Type of FU issued
+system.cpu.iq.rate 1.823672 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 2761405 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.003350 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 2100771128 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 854054980 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 819688520 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 455 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 442 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 164 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 826698389 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 220 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 1868749 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 3330814 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 14803 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 14207 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 1754572 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 3338025 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 14795 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 14329 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 1756067 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 2207477 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 74768 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 2207525 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 74436 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 939989 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 205903045 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 10169335 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 830666192 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 152285 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 17323479 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 10180206 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 703380 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 416558 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 8857895 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 14207 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 510302 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 537060 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 1047362 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 822616274 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 18004247 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 1478799 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 940163 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 205965159 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 10145461 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 830685565 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 152778 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 17334627 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 10181445 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 703446 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 417328 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 8832506 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 14329 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 509833 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 537197 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 1047030 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 822615157 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 18006824 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 1479252 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
-system.cpu.iew.exec_refs 27174393 # number of memory reference insts executed
-system.cpu.iew.exec_branches 83301836 # Number of branches executed
-system.cpu.iew.exec_stores 9170146 # Number of stores executed
-system.cpu.iew.exec_rate 1.819883 # Inst execution rate
-system.cpu.iew.wb_sent 822114086 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 819692399 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 640992347 # num instructions producing a value
-system.cpu.iew.wb_consumers 1050518142 # num instructions consuming a value
+system.cpu.iew.exec_refs 27175476 # number of memory reference insts executed
+system.cpu.iew.exec_branches 83299971 # Number of branches executed
+system.cpu.iew.exec_stores 9168652 # Number of stores executed
+system.cpu.iew.exec_rate 1.820101 # Inst execution rate
+system.cpu.iew.wb_sent 822110525 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 819688684 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 640992243 # num instructions producing a value
+system.cpu.iew.wb_consumers 1050515204 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 1.813415 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.610168 # average fanout of values written-back
+system.cpu.iew.wb_rate 1.813626 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.610169 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 24149765 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 1045534 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 907960 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 445713409 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 1.809212 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.671420 # Number of insts commited each cycle
+system.cpu.commit.commitSquashedInsts 24158442 # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls 1045781 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts 908032 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 445675381 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 1.809392 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.671516 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 274913705 61.68% 61.68% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 11179565 2.51% 64.19% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 3571950 0.80% 64.99% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 74564778 16.73% 81.72% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 2421074 0.54% 82.26% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 1628213 0.37% 82.63% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 937027 0.21% 82.84% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 71052272 15.94% 98.78% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 5444825 1.22% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 274876482 61.68% 61.68% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 11176587 2.51% 64.18% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 3572419 0.80% 64.99% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 74567842 16.73% 81.72% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 2417950 0.54% 82.26% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 1626837 0.37% 82.62% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 937685 0.21% 82.84% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 71052352 15.94% 98.78% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 5447227 1.22% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 445713409 # Number of insts commited each cycle
-system.cpu.commit.committedInsts 407959851 # Number of instructions committed
-system.cpu.commit.committedOps 806389826 # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total 445675381 # Number of insts commited each cycle
+system.cpu.commit.committedInsts 407963408 # Number of instructions committed
+system.cpu.commit.committedOps 806401326 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.refs 22418298 # Number of memory references committed
-system.cpu.commit.loads 13992664 # Number of loads committed
-system.cpu.commit.membars 471797 # Number of memory barriers committed
-system.cpu.commit.branches 82198639 # Number of branches committed
+system.cpu.commit.refs 22421978 # Number of memory references committed
+system.cpu.commit.loads 13996600 # Number of loads committed
+system.cpu.commit.membars 471855 # Number of memory barriers committed
+system.cpu.commit.branches 82197677 # Number of branches committed
system.cpu.commit.fp_insts 48 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 735203522 # Number of committed integer instructions.
-system.cpu.commit.function_calls 1155963 # Number of function calls committed.
-system.cpu.commit.op_class_0::No_OpClass 171777 0.02% 0.02% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu 783535872 97.17% 97.19% # Class of committed instruction
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-system.cpu.committedOps 806389826 # Number of Ops (including micro ops) Simulated
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-system.cpu.cpi_total 1.107991 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.902534 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.902534 # IPC: Total IPC of All Threads
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
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system.cpu.dtb_walker_cache.tags.warmup_cycle 194860088500 # Cycle when the warmup percentage was hit.
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system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed
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-system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11589.589273 # average overall miss latency
-system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11589.589273 # average overall miss latency
-system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11589.589273 # average overall miss latency
-system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11589.589273 # average overall miss latency
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+system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11440.088184 # average overall miss latency
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system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed
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-system.cpu.itb_walker_cache.writebacks::total 3310 # number of writebacks
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-system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 15811 # number of ReadReq MSHR misses
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-system.cpu.itb_walker_cache.overall_mshr_misses::total 15811 # number of overall MSHR misses
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-system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 159511522 # number of demand (read+write) MSHR miss cycles
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-system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 159511522 # number of overall MSHR miss cycles
-system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 159511522 # number of overall MSHR miss cycles
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+system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9938.771048 # average overall mshr miss latency
+system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9938.771048 # average overall mshr miss latency
system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
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-system.cpu.l2cache.tags.tagsinuse 64825.802499 # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs 3846196 # Total number of references to valid blocks.
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+system.cpu.l2cache.tags.avg_refs 21.737728 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 50361.141250 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 15.517179 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.137228 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 3161.997282 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 11287.009561 # Average occupied blocks per requestor
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-system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000237 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::writebacks 50334.465140 # Average occupied blocks per requestor
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+system.cpu.l2cache.tags.occ_blocks::cpu.inst 3177.784987 # Average occupied blocks per requestor
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system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy
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-system.cpu.l2cache.tags.age_task_id_blocks_1024::1 558 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3484 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5616 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54343 # Occupied blocks per task id
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-system.cpu.l2cache.Writeback_hits::total 1585305 # number of Writeback hits
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-system.cpu.l2cache.UpgradeReq_hits::total 326 # number of UpgradeReq hits
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-system.cpu.l2cache.overall_miss_latency::cpu.inst 1375483774 # number of overall miss cycles
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-system.cpu.l2cache.Writeback_accesses::writebacks 1585305 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total 1585305 # number of Writeback accesses(hits+misses)
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-system.cpu.l2cache.UpgradeReq_accesses::total 1799 # number of UpgradeReq accesses(hits+misses)
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system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq 3070183 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 3069642 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteReq 13919 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteResp 13919 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback 1585305 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 46754 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq 2280 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp 2280 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 287814 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 287814 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::BadAddressError 8 # Transaction distribution
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-system.cpu.toL2Bus.snoops 59545 # Total snoops (count)
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-system.cpu.toL2Bus.snoop_fanout::stdev 0.103666 # Request fanout histogram
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+system.cpu.toL2Bus.snoops 59218 # Total snoops (count)
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system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::3 4339973 98.91% 98.91% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::4 47670 1.09% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::3 4338264 98.91% 98.91% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::4 47681 1.09% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 4387643 # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy 4071571970 # Layer occupancy (ticks)
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system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu.toL2Bus.snoopLayer0.occupancy 574500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoopLayer0.occupancy 573000 # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 1506228195 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy 1503118459 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 3139390437 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy 3140913916 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer2.occupancy 23723987 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.occupancy 22173731 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy 112471118 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.occupancy 111517380 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.trans_dist::ReadReq 223900 # Transaction distribution
-system.iobus.trans_dist::ReadResp 223900 # Transaction distribution
-system.iobus.trans_dist::WriteReq 57738 # Transaction distribution
-system.iobus.trans_dist::WriteResp 11018 # Transaction distribution
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+system.iobus.trans_dist::ReadResp 223909 # Transaction distribution
+system.iobus.trans_dist::WriteReq 57755 # Transaction distribution
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system.iobus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution
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-system.iobus.trans_dist::MessageResp 1650 # Transaction distribution
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+system.iobus.trans_dist::MessageResp 1653 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11134 # Packet count per connected master and slave (bytes)
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system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 78 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 423734 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1218 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist1.pio 170 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27824 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 468004 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95272 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95272 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3300 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3300 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 566576 # Packet count per connected master and slave (bytes)
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+system.iobus.pkt_count::total 566634 # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes)
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system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 39 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 211867 # Cumulative packet size per connected master and slave (bytes)
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system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist1.pio 85 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13912 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes)
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-system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027872 # Cumulative packet size per connected master and slave (bytes)
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-system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6600 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total 3274757 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy 3933000 # Layer occupancy (ticks)
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system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer3.occupancy 8851000 # Layer occupancy (ticks)
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system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer4.occupancy 122000 # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer9.occupancy 211868000 # Layer occupancy (ticks)
system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer10.occupancy 1014000 # Layer occupancy (ticks)
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system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer11.occupancy 170000 # Layer occupancy (ticks)
system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer19.occupancy 257352407 # Layer occupancy (ticks)
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system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer20.occupancy 1064000 # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer0.occupancy 456986000 # Layer occupancy (ticks)
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system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer1.occupancy 50389253 # Layer occupancy (ticks)
+system.iobus.respLayer1.occupancy 50384761 # Layer occupancy (ticks)
system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer2.occupancy 1650000 # Layer occupancy (ticks)
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system.iobus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.iocache.tags.replacements 47582 # number of replacements
-system.iocache.tags.tagsinuse 0.177916 # Cycle average of tags in use
+system.iocache.tags.replacements 47580 # number of replacements
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system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs 47598 # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs 47596 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle 4993302485000 # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.177916 # Average occupied blocks per requestor
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system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses 428724 # Number of tag accesses
-system.iocache.tags.data_accesses 428724 # Number of data accesses
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-system.iocache.ReadReq_misses::total 916 # number of ReadReq misses
+system.iocache.tags.tag_accesses 428715 # Number of tag accesses
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+system.iocache.ReadReq_misses::total 915 # number of ReadReq misses
system.iocache.WriteInvalidateReq_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq misses
system.iocache.WriteInvalidateReq_misses::total 46720 # number of WriteInvalidateReq misses
-system.iocache.demand_misses::pc.south_bridge.ide 916 # number of demand (read+write) misses
-system.iocache.demand_misses::total 916 # number of demand (read+write) misses
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-system.iocache.overall_misses::total 916 # number of overall misses
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-system.iocache.ReadReq_miss_latency::total 144791938 # number of ReadReq miss cycles
-system.iocache.WriteInvalidateReq_miss_latency::pc.south_bridge.ide 8565273216 # number of WriteInvalidateReq miss cycles
-system.iocache.WriteInvalidateReq_miss_latency::total 8565273216 # number of WriteInvalidateReq miss cycles
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-system.iocache.demand_miss_latency::total 144791938 # number of demand (read+write) miss cycles
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-system.iocache.overall_miss_latency::total 144791938 # number of overall miss cycles
-system.iocache.ReadReq_accesses::pc.south_bridge.ide 916 # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total 916 # number of ReadReq accesses(hits+misses)
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+system.iocache.ReadReq_miss_latency::total 146193424 # number of ReadReq miss cycles
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+system.iocache.WriteInvalidateReq_miss_latency::total 8577113961 # number of WriteInvalidateReq miss cycles
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+system.iocache.overall_miss_latency::total 146193424 # number of overall miss cycles
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system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::total 46720 # number of WriteInvalidateReq accesses(hits+misses)
-system.iocache.demand_accesses::pc.south_bridge.ide 916 # number of demand (read+write) accesses
-system.iocache.demand_accesses::total 916 # number of demand (read+write) accesses
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-system.iocache.overall_accesses::total 916 # number of overall (read+write) accesses
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+system.iocache.demand_accesses::total 915 # number of demand (read+write) accesses
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+system.iocache.overall_accesses::total 915 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteInvalidateReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteInvalidateReq accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 158069.801310 # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 158069.801310 # average ReadReq miss latency
-system.iocache.WriteInvalidateReq_avg_miss_latency::pc.south_bridge.ide 183332.046575 # average WriteInvalidateReq miss latency
-system.iocache.WriteInvalidateReq_avg_miss_latency::total 183332.046575 # average WriteInvalidateReq miss latency
-system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 158069.801310 # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 158069.801310 # average overall miss latency
-system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 158069.801310 # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 158069.801310 # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs 29224 # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 159774.233880 # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 159774.233880 # average ReadReq miss latency
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+system.iocache.WriteInvalidateReq_avg_miss_latency::total 183585.487179 # average WriteInvalidateReq miss latency
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+system.iocache.demand_avg_miss_latency::total 159774.233880 # average overall miss latency
+system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 159774.233880 # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 159774.233880 # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs 29604 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.iocache.blocked::no_mshrs 4409 # number of cycles access was blocked
+system.iocache.blocked::no_mshrs 4403 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs 6.628260 # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs 6.723598 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.writebacks::writebacks 46668 # number of writebacks
-system.iocache.writebacks::total 46668 # number of writebacks
-system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 916 # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total 916 # number of ReadReq MSHR misses
+system.iocache.writebacks::writebacks 46667 # number of writebacks
+system.iocache.writebacks::total 46667 # number of writebacks
+system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 915 # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total 915 # number of ReadReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::total 46720 # number of WriteInvalidateReq MSHR misses
-system.iocache.demand_mshr_misses::pc.south_bridge.ide 916 # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total 916 # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::pc.south_bridge.ide 916 # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total 916 # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 96734432 # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total 96734432 # number of ReadReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 6135821228 # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::total 6135821228 # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 96734432 # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total 96734432 # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 96734432 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total 96734432 # number of overall MSHR miss cycles
+system.iocache.demand_mshr_misses::pc.south_bridge.ide 915 # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total 915 # number of demand (read+write) MSHR misses
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+system.iocache.overall_mshr_misses::total 915 # number of overall MSHR misses
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+system.iocache.ReadReq_mshr_miss_latency::total 98194936 # number of ReadReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 6147663971 # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::total 6147663971 # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 98194936 # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total 98194936 # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 98194936 # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total 98194936 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteInvalidateReq accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 105605.275109 # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 105605.275109 # average ReadReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 131331.789983 # average WriteInvalidateReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 131331.789983 # average WriteInvalidateReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 105605.275109 # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 105605.275109 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 105605.275109 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 105605.275109 # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 107316.869945 # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 107316.869945 # average ReadReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 131585.273352 # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 131585.273352 # average WriteInvalidateReq mshr miss latency
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+system.iocache.demand_avg_mshr_miss_latency::total 107316.869945 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 107316.869945 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 107316.869945 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq 657690 # Transaction distribution
-system.membus.trans_dist::ReadResp 657682 # Transaction distribution
-system.membus.trans_dist::WriteReq 13919 # Transaction distribution
-system.membus.trans_dist::WriteResp 13919 # Transaction distribution
-system.membus.trans_dist::Writeback 149687 # Transaction distribution
+system.membus.trans_dist::ReadReq 657723 # Transaction distribution
+system.membus.trans_dist::ReadResp 657716 # Transaction distribution
+system.membus.trans_dist::WriteReq 13939 # Transaction distribution
+system.membus.trans_dist::WriteResp 13939 # Transaction distribution
+system.membus.trans_dist::Writeback 149601 # Transaction distribution
system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 2233 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 1752 # Transaction distribution
-system.membus.trans_dist::ReadExReq 133182 # Transaction distribution
-system.membus.trans_dist::ReadExResp 133180 # Transaction distribution
-system.membus.trans_dist::MessageReq 1650 # Transaction distribution
-system.membus.trans_dist::MessageResp 1650 # Transaction distribution
-system.membus.trans_dist::BadAddressError 8 # Transaction distribution
-system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3300 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.apicbridge.master::total 3300 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 468004 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 769220 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 476828 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 16 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1714068 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141467 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total 141467 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 1858835 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6600 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.apicbridge.master::total 6600 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 240285 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1538437 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18406720 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total 20185442 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 6005184 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total 6005184 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 26197226 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 1640 # Total snoops (count)
-system.membus.snoop_fanout::samples 384867 # Request fanout histogram
+system.membus.trans_dist::UpgradeReq 2217 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 1736 # Transaction distribution
+system.membus.trans_dist::ReadExReq 132934 # Transaction distribution
+system.membus.trans_dist::ReadExResp 132932 # Transaction distribution
+system.membus.trans_dist::MessageReq 1653 # Transaction distribution
+system.membus.trans_dist::MessageResp 1653 # Transaction distribution
+system.membus.trans_dist::BadAddressError 7 # Transaction distribution
+system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3306 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.apicbridge.master::total 3306 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 468058 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 769226 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 476258 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 14 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1713556 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141465 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total 141465 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 1858327 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6612 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.apicbridge.master::total 6612 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 240327 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1538449 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18386624 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total 20165400 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 6005120 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total 6005120 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 26177132 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 1646 # Total snoops (count)
+system.membus.snoop_fanout::samples 384552 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 384867 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 384552 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 384867 # Request fanout histogram
-system.membus.reqLayer0.occupancy 357799000 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 384552 # Request fanout histogram
+system.membus.reqLayer0.occupancy 357825500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer1.occupancy 388520500 # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy 388164500 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 3300000 # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy 3306000 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer3.occupancy 1203232654 # Layer occupancy (ticks)
+system.membus.reqLayer3.occupancy 1202618637 # Layer occupancy (ticks)
system.membus.reqLayer3.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer4.occupancy 10500 # Layer occupancy (ticks)
+system.membus.reqLayer4.occupancy 8500 # Layer occupancy (ticks)
system.membus.reqLayer4.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer0.occupancy 1650000 # Layer occupancy (ticks)
+system.membus.respLayer0.occupancy 1653000 # Layer occupancy (ticks)
system.membus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer2.occupancy 2208381292 # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy 2206854286 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer4.occupancy 51518747 # Layer occupancy (ticks)
+system.membus.respLayer4.occupancy 51509239 # Layer occupancy (ticks)
system.membus.respLayer4.utilization 0.0 # Layer utilization (%)
system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
---------- Begin Simulation Statistics ----------
+sim_seconds 2.783867 # Number of seconds simulated
+sim_ticks 2783867052000 # Number of ticks simulated
final_tick 2783867052000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-host_inst_rate 976886 # Simulator instruction rate (inst/s)
-host_mem_usage 567972 # Number of bytes of host memory used
-host_op_rate 1189202 # Simulator op (including micro ops) rate (op/s)
-host_seconds 146.15 # Real time elapsed on the host
-host_tick_rate 19047880334 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 903946 # Simulator instruction rate (inst/s)
+host_op_rate 1100409 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 17625645989 # Simulator tick rate (ticks/s)
+host_mem_usage 615176 # Number of bytes of host memory used
+host_seconds 157.94 # Real time elapsed on the host
sim_insts 142772879 # Number of instructions simulated
sim_ops 173803124 # Number of ops (including micro ops) simulated
-sim_seconds 2.783867 # Number of seconds simulated
-sim_ticks 2783867052000 # Number of ticks simulated
-system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
+system.voltage_domain.voltage 1 # Voltage in Volts
+system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst 1210788 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 10328292 # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
+system.physmem.bytes_read::total 11540616 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 1210788 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 1210788 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 8837568 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory
+system.physmem.bytes_written::total 8855092 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.dtb.walker 7 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst 27372 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 161899 # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 189295 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 138087 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 142468 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.dtb.walker 161 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker 46 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 434930 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 3710052 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide 345 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 4145534 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 434930 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 434930 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 3174565 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data 6295 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 3180860 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 3174565 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker 161 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.itb.walker 46 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 434930 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 3716347 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide 345 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 7326394 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu.inst 7 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total 7 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu.inst 7 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu.inst 7 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total 7 # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
+system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
-system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
+system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 631 # Number of DMA write transactions.
-system.clk_domain.clock 1000 # Clock period in ticks
-system.cpu.Branches 36396981 # Number of branches fetched
-system.cpu.committedInsts 142772879 # Number of instructions committed
-system.cpu.committedOps 173803124 # Number of ops (including micro ops) committed
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465959 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 465959 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 457347 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 457347 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.018482 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total 0.018482 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data 8612 # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total 8612 # number of LoadLockedReq misses
-system.cpu.dcache.ReadReq_accesses::cpu.data 30525328 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 30525328 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_hits::cpu.data 30129052 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 30129052 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012982 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.012982 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses::cpu.data 396276 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 396276 # number of ReadReq misses
-system.cpu.dcache.SoftPFReq_accesses::cpu.data 511200 # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total 511200 # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_hits::cpu.data 395080 # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total 395080 # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.227152 # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total 0.227152 # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_misses::cpu.data 116120 # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total 116120 # number of SoftPFReq misses
-system.cpu.dcache.StoreCondReq_accesses::cpu.data 460138 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total 460138 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_hits::cpu.data 460136 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 460136 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004 # miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses
-system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses
-system.cpu.dcache.WriteReq_accesses::cpu.data 22641788 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 22641788 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_hits::cpu.data 22340110 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 22340110 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013324 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.013324 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses::cpu.data 301678 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 301678 # number of WriteReq misses
-system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses::cpu.data 53167116 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 53167116 # number of demand (read+write) accesses
-system.cpu.dcache.demand_hits::cpu.data 52469162 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 52469162 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_rate::cpu.data 0.013128 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.013128 # miss rate for demand accesses
-system.cpu.dcache.demand_misses::cpu.data 697954 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 697954 # number of demand (read+write) misses
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses::cpu.data 53678316 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 53678316 # number of overall (read+write) accesses
-system.cpu.dcache.overall_hits::cpu.data 52864242 # number of overall hits
-system.cpu.dcache.overall_hits::total 52864242 # number of overall hits
-system.cpu.dcache.overall_miss_rate::cpu.data 0.015166 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.015166 # miss rate for overall accesses
-system.cpu.dcache.overall_misses::cpu.data 814074 # number of overall misses
-system.cpu.dcache.overall_misses::total 814074 # number of overall misses
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 286 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 196 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id
-system.cpu.dcache.tags.avg_refs 65.597713 # Average number of references to valid blocks.
-system.cpu.dcache.tags.data_accesses 219237582 # Number of data accesses
-system.cpu.dcache.tags.occ_blocks::cpu.data 511.997174 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.replacements 819402 # number of replacements
-system.cpu.dcache.tags.sampled_refs 819914 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.tag_accesses 219237582 # Number of tag accesses
-system.cpu.dcache.tags.tagsinuse 511.997174 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 53784483 # Total number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks::writebacks 682059 # number of writebacks
-system.cpu.dcache.writebacks::total 682059 # number of writebacks
-system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
-system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
-system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
-system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
-system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
-system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
-system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
-system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
+system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
-system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
+system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
+system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
+system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
+system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
-system.cpu.dtb.accesses 54660704 # DTB accesses
-system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.flush_entries 4349 # Number of entries that have been flushed from TLB
-system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.hits 54650675 # DTB hits
-system.cpu.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.dtb.inst_hits 0 # ITB inst hits
-system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.misses 10029 # DTB misses
-system.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.prefetch_faults 1613 # Number of TLB faults due to prefetch
-system.cpu.dtb.read_accesses 31534804 # DTB read accesses
-system.cpu.dtb.read_hits 31526223 # DTB read hits
-system.cpu.dtb.read_misses 8581 # DTB read misses
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
+system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
+system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
+system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
+system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
+system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.dtb.walker.walks 10029 # Table walker walks requested
+system.cpu.dtb.walker.walksShort 10029 # Table walker walks initiated with short descriptors
+system.cpu.dtb.walker.walkWaitTime::samples 10029 # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::0 10029 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::total 10029 # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walksPending::samples 6705500 # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::0 6705500 100.00% 100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::total 6705500 # Table walker pending requests distribution
system.cpu.dtb.walker.walkPageSizes::4K 6354 80.79% 80.79% # Table walker page sizes translated
system.cpu.dtb.walker.walkPageSizes::1M 1511 19.21% 100.00% # Table walker page sizes translated
system.cpu.dtb.walker.walkPageSizes::total 7865 # Table walker page sizes translated
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7865 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total 17894 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkWaitTime::samples 10029 # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::0 10029 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::total 10029 # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walks 10029 # Table walker walks requested
-system.cpu.dtb.walker.walksPending::samples 6705500 # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::0 6705500 100.00% 100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::total 6705500 # Table walker pending requests distribution
-system.cpu.dtb.walker.walksShort 10029 # Table walker walks initiated with short descriptors
-system.cpu.dtb.write_accesses 23125900 # DTB write accesses
+system.cpu.dtb.inst_hits 0 # ITB inst hits
+system.cpu.dtb.inst_misses 0 # ITB inst misses
+system.cpu.dtb.read_hits 31526223 # DTB read hits
+system.cpu.dtb.read_misses 8581 # DTB read misses
system.cpu.dtb.write_hits 23124452 # DTB write hits
system.cpu.dtb.write_misses 1448 # DTB write misses
-system.cpu.icache.ReadReq_accesses::cpu.inst 147042453 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 147042453 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_hits::cpu.inst 145342721 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 145342721 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.011559 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.011559 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses::cpu.inst 1699732 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 1699732 # number of ReadReq misses
-system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses::cpu.inst 147042453 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 147042453 # number of demand (read+write) accesses
-system.cpu.icache.demand_hits::cpu.inst 145342721 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 145342721 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_rate::cpu.inst 0.011559 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.011559 # miss rate for demand accesses
-system.cpu.icache.demand_misses::cpu.inst 1699732 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 1699732 # number of demand (read+write) misses
-system.cpu.icache.fast_writes 0 # number of fast writes performed
-system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses::cpu.inst 147042453 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 147042453 # number of overall (read+write) accesses
-system.cpu.icache.overall_hits::cpu.inst 145342721 # number of overall hits
-system.cpu.icache.overall_hits::total 145342721 # number of overall hits
-system.cpu.icache.overall_miss_rate::cpu.inst 0.011559 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.011559 # miss rate for overall accesses
-system.cpu.icache.overall_misses::cpu.inst 1699732 # number of overall misses
-system.cpu.icache.overall_misses::total 1699732 # number of overall misses
-system.cpu.icache.tags.age_task_id_blocks_1024::0 197 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1 77 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2 233 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id
-system.cpu.icache.tags.avg_refs 85.509500 # Average number of references to valid blocks.
-system.cpu.icache.tags.data_accesses 148742185 # Number of data accesses
-system.cpu.icache.tags.occ_blocks::cpu.inst 511.663681 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.999343 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.999343 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu.icache.tags.replacements 1699214 # number of replacements
-system.cpu.icache.tags.sampled_refs 1699726 # Sample count of references to valid blocks.
-system.cpu.icache.tags.tag_accesses 148742185 # Number of tag accesses
-system.cpu.icache.tags.tagsinuse 511.663681 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 145342721 # Total number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle 7831491500 # Cycle when the warmup percentage was hit.
-system.cpu.idle_fraction 0.968015 # Percentage of idle cycles
-system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
-system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
-system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
-system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
-system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
-system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
-system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
-system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
+system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries 4349 # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults 1613 # Number of TLB faults due to prefetch
+system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses 31534804 # DTB read accesses
+system.cpu.dtb.write_accesses 23125900 # DTB write accesses
+system.cpu.dtb.inst_accesses 0 # ITB inst accesses
+system.cpu.dtb.hits 54650675 # DTB hits
+system.cpu.dtb.misses 10029 # DTB misses
+system.cpu.dtb.accesses 54660704 # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
-system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
+system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
+system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
+system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
+system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
-system.cpu.itb.accesses 147044108 # DTB accesses
-system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.flush_entries 2913 # Number of entries that have been flushed from TLB
-system.cpu.itb.flush_tlb 64 # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.hits 147039346 # DTB hits
-system.cpu.itb.inst_accesses 147044108 # ITB inst accesses
-system.cpu.itb.inst_hits 147039346 # ITB inst hits
-system.cpu.itb.inst_misses 4762 # ITB inst misses
-system.cpu.itb.misses 4762 # DTB misses
-system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.itb.read_accesses 0 # DTB read accesses
-system.cpu.itb.read_hits 0 # DTB read hits
-system.cpu.itb.read_misses 0 # DTB read misses
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
+system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
+system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
+system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
+system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
+system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.itb.walker.walks 4762 # Table walker walks requested
+system.cpu.itb.walker.walksShort 4762 # Table walker walks initiated with short descriptors
+system.cpu.itb.walker.walkWaitTime::samples 4762 # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::0 4762 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::total 4762 # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walksPending::samples 6702500 # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::0 6702500 100.00% 100.00% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::total 6702500 # Table walker pending requests distribution
system.cpu.itb.walker.walkPageSizes::4K 2798 90.05% 90.05% # Table walker page sizes translated
system.cpu.itb.walker.walkPageSizes::1M 309 9.95% 100.00% # Table walker page sizes translated
system.cpu.itb.walker.walkPageSizes::total 3107 # Table walker page sizes translated
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3107 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total 3107 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total 7869 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkWaitTime::samples 4762 # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::0 4762 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::total 4762 # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walks 4762 # Table walker walks requested
-system.cpu.itb.walker.walksPending::samples 6702500 # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::0 6702500 100.00% 100.00% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::total 6702500 # Table walker pending requests distribution
-system.cpu.itb.walker.walksShort 4762 # Table walker walks initiated with short descriptors
-system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.inst_hits 147039346 # ITB inst hits
+system.cpu.itb.inst_misses 4762 # ITB inst misses
+system.cpu.itb.read_hits 0 # DTB read hits
+system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.kern.inst.arm 0 # number of arm instructions executed
-system.cpu.kern.inst.quiesce 3083 # number of quiesce instructions executed
-system.cpu.l2cache.ReadExReq_accesses::cpu.data 298922 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total 298922 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_hits::cpu.data 151058 # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total 151058 # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.494657 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total 0.494657 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses::cpu.data 147864 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total 147864 # number of ReadExReq misses
-system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7608 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3623 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.inst 1699714 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data 521008 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total 2231953 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7601 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3621 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.inst 1681357 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data 505474 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total 2198053 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000920 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000552 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.010800 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.029815 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total 0.015188 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 7 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.inst 18357 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data 15534 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total 33900 # number of ReadReq misses
-system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses)
-system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses)
-system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses
-system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2756 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total 2756 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_hits::cpu.data 28 # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total 28 # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.989840 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total 0.989840 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data 2728 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total 2728 # number of UpgradeReq misses
-system.cpu.l2cache.Writeback_accesses::writebacks 682059 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total 682059 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits::writebacks 682059 # number of Writeback hits
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-system.cpu.l2cache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1 180 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3716 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3 10700 # Occupied blocks per task id
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-system.cpu.l2cache.tags.data_accesses 26204344 # Number of data accesses
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-system.cpu.l2cache.tags.occ_blocks::cpu.inst 9064.654943 # Average occupied blocks per requestor
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system.cpu.num_fp_alu_accesses 11484 # Number of float alu accesses
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system.cpu.num_func_calls 16873899 # number of times a function call or return occured
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system.cpu.num_int_insts 153162683 # number of integer instructions
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system.cpu.num_int_register_writes 107179480 # number of times the integer registers were written
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system.cpu.num_mem_refs 55939276 # number of memory refs
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system.cpu.num_store_insts 24083392 # Number of store instructions
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system.cpu.op_class::No_OpClass 2337 0.00% 0.00% # Class of executed instruction
system.cpu.op_class::IntAlu 121152838 68.36% 68.36% # Class of executed instruction
system.cpu.op_class::IntMult 116892 0.07% 68.43% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 177219912 # Class of executed instruction
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system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2444657 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 18430 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 36860 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 74000 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 205239845 # Cumulative packet size per connected master and slave (bytes)
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system.cpu.toL2Bus.snoop_fanout::mean 3.011156 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.105030 # Request fanout histogram
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system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 3268658 # Request fanout histogram
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-system.cpu.toL2Bus.trans_dist::ReadExResp 298922 # Transaction distribution
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system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321152 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total 2321152 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total 2480213 # Cumulative packet size per connected master and slave (bytes)
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system.iocache.ReadReq_misses::realview.ide 240 # number of ReadReq misses
system.iocache.ReadReq_misses::total 240 # number of ReadReq misses
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system.iocache.WriteInvalidateReq_misses::realview.ide 36224 # number of WriteInvalidateReq misses
system.iocache.WriteInvalidateReq_misses::total 36224 # number of WriteInvalidateReq misses
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system.iocache.demand_misses::realview.ide 240 # number of demand (read+write) misses
system.iocache.demand_misses::total 240 # number of demand (read+write) misses
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system.iocache.overall_accesses::total 240 # number of overall (read+write) accesses
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system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
-system.iocache.overall_misses::realview.ide 240 # number of overall misses
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-system.iocache.tags.replacements 36430 # number of replacements
-system.iocache.tags.sampled_refs 36446 # Sample count of references to valid blocks.
-system.iocache.tags.tag_accesses 328176 # Number of tag accesses
-system.iocache.tags.tagsinuse 0.909961 # Cycle average of tags in use
-system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
-system.iocache.tags.warmup_cycle 227409731009 # Cycle when the warmup percentage was hit.
+system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.iocache.writebacks::writebacks 36190 # number of writebacks
system.iocache.writebacks::total 36190 # number of writebacks
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+system.membus.trans_dist::ReadReq 74227 # Transaction distribution
+system.membus.trans_dist::ReadResp 74227 # Transaction distribution
+system.membus.trans_dist::WriteReq 27546 # Transaction distribution
+system.membus.trans_dist::WriteResp 27546 # Transaction distribution
+system.membus.trans_dist::Writeback 138087 # Transaction distribution
+system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution
+system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
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+system.membus.trans_dist::ReadExReq 146085 # Transaction distribution
+system.membus.trans_dist::ReadExResp 146085 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105404 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 1946 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4649856 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 4649856 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 22909145 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 359045 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
system.membus.snoop_fanout::total 359045 # Request fanout histogram
-system.membus.snoops 0 # Total snoops (count)
-system.membus.trans_dist::ReadReq 74227 # Transaction distribution
-system.membus.trans_dist::ReadResp 74227 # Transaction distribution
-system.membus.trans_dist::WriteReq 27546 # Transaction distribution
-system.membus.trans_dist::WriteResp 27546 # Transaction distribution
-system.membus.trans_dist::Writeback 138087 # Transaction distribution
-system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution
-system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 4507 # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 4509 # Transaction distribution
-system.membus.trans_dist::ReadExReq 146085 # Transaction distribution
-system.membus.trans_dist::ReadExResp 146085 # Transaction distribution
-system.physmem.bw_inst_read::cpu.inst 434930 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 434930 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.dtb.walker 161 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker 46 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst 434930 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 3710052 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide 345 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 4145534 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 3174565 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker 161 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker 46 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 434930 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 3716347 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide 345 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 7326394 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_write::writebacks 3174565 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data 6295 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 3180860 # Write bandwidth from this memory (bytes/s)
-system.physmem.bytes_inst_read::cpu.inst 1210788 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 1210788 # Number of instructions bytes read from this memory
-system.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst 1210788 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 10328292 # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
-system.physmem.bytes_read::total 11540616 # Number of bytes read from this memory
-system.physmem.bytes_written::writebacks 8837568 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory
-system.physmem.bytes_written::total 8855092 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.dtb.walker 7 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst 27372 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 161899 # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 189295 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 138087 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 142468 # Number of write requests responded to by this memory
-system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
-system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
-system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
-system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
-system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
-system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
-system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
-system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
-system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
-system.realview.ethernet.droppedPackets 0 # number of packets dropped
-system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
-system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
-system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
-system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
-system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
-system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
-system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
-system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
-system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
+system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
+system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
+system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
+system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
+system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
+system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
-system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
-system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
-system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
-system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
+system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
+system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
+system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
+system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
-system.realview.nvmem.bw_inst_read::cpu.inst 7 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::cpu.inst 7 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total 7 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu.inst 7 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total 7 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
-system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
-system.voltage_domain.voltage 1 # Voltage in Volts
+system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
+system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
+system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
+system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
+system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
+system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
+system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
+system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
+system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
+system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
+system.realview.ethernet.droppedPackets 0 # number of packets dropped
---------- End Simulation Statistics ----------
sim_ticks 200409271000 # Number of ticks simulated
final_tick 4321213476000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 15445218 # Simulator instruction rate (inst/s)
-host_op_rate 15445213 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 5909651303 # Simulator tick rate (ticks/s)
-host_mem_usage 534848 # Number of bytes of host memory used
-host_seconds 33.91 # Real time elapsed on the host
+host_inst_rate 10268281 # Simulator instruction rate (inst/s)
+host_op_rate 10268278 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 3928851236 # Simulator tick rate (ticks/s)
+host_mem_usage 533084 # Number of bytes of host memory used
+host_seconds 51.01 # Real time elapsed on the host
sim_insts 523780905 # Number of instructions simulated
sim_ops 523780905 # Number of ops (including micro ops) simulated
-testsys.voltage_domain.voltage 1 # Voltage in Volts
-testsys.clk_domain.clock 1000 # Clock period in ticks
-testsys.physmem.bytes_read::cpu.inst 81044080 # Number of bytes read from this memory
-testsys.physmem.bytes_read::cpu.data 27825116 # Number of bytes read from this memory
-testsys.physmem.bytes_read::tsunami.ethernet 57260496 # Number of bytes read from this memory
-testsys.physmem.bytes_read::total 166129692 # Number of bytes read from this memory
-testsys.physmem.bytes_inst_read::cpu.inst 81044080 # Number of instructions bytes read from this memory
-testsys.physmem.bytes_inst_read::total 81044080 # Number of instructions bytes read from this memory
-testsys.physmem.bytes_written::cpu.data 16605404 # Number of bytes written to this memory
-testsys.physmem.bytes_written::tsunami.ethernet 902 # Number of bytes written to this memory
-testsys.physmem.bytes_written::total 16606306 # Number of bytes written to this memory
-testsys.physmem.num_reads::cpu.inst 20261020 # Number of read requests responded to by this memory
-testsys.physmem.num_reads::cpu.data 3842409 # Number of read requests responded to by this memory
-testsys.physmem.num_reads::tsunami.ethernet 2385836 # Number of read requests responded to by this memory
-testsys.physmem.num_reads::total 26489265 # Number of read requests responded to by this memory
-testsys.physmem.num_writes::cpu.data 2258228 # Number of write requests responded to by this memory
-testsys.physmem.num_writes::tsunami.ethernet 31 # Number of write requests responded to by this memory
-testsys.physmem.num_writes::total 2258259 # Number of write requests responded to by this memory
-testsys.physmem.bw_read::cpu.inst 404392869 # Total read bandwidth from this memory (bytes/s)
-testsys.physmem.bw_read::cpu.data 138841461 # Total read bandwidth from this memory (bytes/s)
-testsys.physmem.bw_read::tsunami.ethernet 285717800 # Total read bandwidth from this memory (bytes/s)
-testsys.physmem.bw_read::total 828952130 # Total read bandwidth from this memory (bytes/s)
-testsys.physmem.bw_inst_read::cpu.inst 404392869 # Instruction read bandwidth from this memory (bytes/s)
-testsys.physmem.bw_inst_read::total 404392869 # Instruction read bandwidth from this memory (bytes/s)
-testsys.physmem.bw_write::cpu.data 82857464 # Write bandwidth from this memory (bytes/s)
-testsys.physmem.bw_write::tsunami.ethernet 4501 # Write bandwidth from this memory (bytes/s)
-testsys.physmem.bw_write::total 82861965 # Write bandwidth from this memory (bytes/s)
-testsys.physmem.bw_total::cpu.inst 404392869 # Total bandwidth to/from this memory (bytes/s)
-testsys.physmem.bw_total::cpu.data 221698925 # Total bandwidth to/from this memory (bytes/s)
-testsys.physmem.bw_total::tsunami.ethernet 285722301 # Total bandwidth to/from this memory (bytes/s)
-testsys.physmem.bw_total::total 911814095 # Total bandwidth to/from this memory (bytes/s)
-testsys.membus.trans_dist::ReadReq 26478762 # Transaction distribution
-testsys.membus.trans_dist::ReadResp 26587372 # Transaction distribution
-testsys.membus.trans_dist::WriteReq 2189273 # Transaction distribution
-testsys.membus.trans_dist::WriteResp 2189273 # Transaction distribution
-testsys.membus.trans_dist::LoadLockedReq 108610 # Transaction distribution
-testsys.membus.trans_dist::StoreCondReq 108528 # Transaction distribution
-testsys.membus.trans_dist::StoreCondResp 108528 # Transaction distribution
-testsys.membus.pkt_count_testsys.cpu.icache_port::testsys.physmem.port 40522040 # Packet count per connected master and slave (bytes)
-testsys.membus.pkt_count_testsys.cpu.icache_port::total 40522040 # Packet count per connected master and slave (bytes)
-testsys.membus.pkt_count_testsys.cpu.dcache_port::testsys.bridge.slave 275298 # Packet count per connected master and slave (bytes)
-testsys.membus.pkt_count_testsys.cpu.dcache_port::testsys.physmem.port 12201274 # Packet count per connected master and slave (bytes)
-testsys.membus.pkt_count_testsys.cpu.dcache_port::total 12476572 # Packet count per connected master and slave (bytes)
-testsys.membus.pkt_count_testsys.iobridge.master::testsys.physmem.port 4771734 # Packet count per connected master and slave (bytes)
-testsys.membus.pkt_count_testsys.iobridge.master::total 4771734 # Packet count per connected master and slave (bytes)
-testsys.membus.pkt_count::total 57770346 # Packet count per connected master and slave (bytes)
-testsys.membus.pkt_size_testsys.cpu.icache_port::testsys.physmem.port 81044080 # Cumulative packet size per connected master and slave (bytes)
-testsys.membus.pkt_size_testsys.cpu.icache_port::total 81044080 # Cumulative packet size per connected master and slave (bytes)
-testsys.membus.pkt_size_testsys.cpu.dcache_port::testsys.bridge.slave 942152 # Cumulative packet size per connected master and slave (bytes)
-testsys.membus.pkt_size_testsys.cpu.dcache_port::testsys.physmem.port 44430520 # Cumulative packet size per connected master and slave (bytes)
-testsys.membus.pkt_size_testsys.cpu.dcache_port::total 45372672 # Cumulative packet size per connected master and slave (bytes)
-testsys.membus.pkt_size_testsys.iobridge.master::testsys.physmem.port 57261398 # Cumulative packet size per connected master and slave (bytes)
-testsys.membus.pkt_size_testsys.iobridge.master::total 57261398 # Cumulative packet size per connected master and slave (bytes)
-testsys.membus.pkt_size::total 183678150 # Cumulative packet size per connected master and slave (bytes)
-testsys.membus.snoops 0 # Total snoops (count)
-testsys.membus.snoop_fanout::samples 28747524 # Request fanout histogram
-testsys.membus.snoop_fanout::mean 0.787786 # Request fanout histogram
-testsys.membus.snoop_fanout::stdev 0.408876 # Request fanout histogram
-testsys.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-testsys.membus.snoop_fanout::0 6100637 21.22% 21.22% # Request fanout histogram
-testsys.membus.snoop_fanout::1 22646887 78.78% 100.00% # Request fanout histogram
-testsys.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-testsys.membus.snoop_fanout::min_value 0 # Request fanout histogram
-testsys.membus.snoop_fanout::max_value 1 # Request fanout histogram
-testsys.membus.snoop_fanout::total 28747524 # Request fanout histogram
-testsys.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
-testsys.disk0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
-testsys.disk0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
-testsys.disk0.dma_write_full_pages 0 # Number of full page size DMA writes.
-testsys.disk0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
-testsys.disk0.dma_write_txs 0 # Number of DMA write transactions.
-testsys.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
-testsys.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
-testsys.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
-testsys.disk2.dma_write_full_pages 0 # Number of full page size DMA writes.
-testsys.disk2.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
-testsys.disk2.dma_write_txs 0 # Number of DMA write transactions.
-testsys.cpu.clk_domain.clock 500 # Clock period in ticks
-testsys.cpu.dtb.fetch_hits 0 # ITB hits
-testsys.cpu.dtb.fetch_misses 0 # ITB misses
-testsys.cpu.dtb.fetch_acv 0 # ITB acv
-testsys.cpu.dtb.fetch_accesses 0 # ITB accesses
-testsys.cpu.dtb.read_hits 3916768 # DTB read hits
-testsys.cpu.dtb.read_misses 3287 # DTB read misses
-testsys.cpu.dtb.read_acv 80 # DTB read access violations
-testsys.cpu.dtb.read_accesses 225414 # DTB read accesses
-testsys.cpu.dtb.write_hits 2316721 # DTB write hits
-testsys.cpu.dtb.write_misses 528 # DTB write misses
-testsys.cpu.dtb.write_acv 81 # DTB write access violations
-testsys.cpu.dtb.write_accesses 109988 # DTB write accesses
-testsys.cpu.dtb.data_hits 6233489 # DTB hits
-testsys.cpu.dtb.data_misses 3815 # DTB misses
-testsys.cpu.dtb.data_acv 161 # DTB access violations
-testsys.cpu.dtb.data_accesses 335402 # DTB accesses
-testsys.cpu.itb.fetch_hits 4052237 # ITB hits
-testsys.cpu.itb.fetch_misses 1497 # ITB misses
-testsys.cpu.itb.fetch_acv 69 # ITB acv
-testsys.cpu.itb.fetch_accesses 4053734 # ITB accesses
-testsys.cpu.itb.read_hits 0 # DTB read hits
-testsys.cpu.itb.read_misses 0 # DTB read misses
-testsys.cpu.itb.read_acv 0 # DTB read access violations
-testsys.cpu.itb.read_accesses 0 # DTB read accesses
-testsys.cpu.itb.write_hits 0 # DTB write hits
-testsys.cpu.itb.write_misses 0 # DTB write misses
-testsys.cpu.itb.write_acv 0 # DTB write access violations
-testsys.cpu.itb.write_accesses 0 # DTB write accesses
-testsys.cpu.itb.data_hits 0 # DTB hits
-testsys.cpu.itb.data_misses 0 # DTB misses
-testsys.cpu.itb.data_acv 0 # DTB access violations
-testsys.cpu.itb.data_accesses 0 # DTB accesses
-testsys.cpu.numCycles 400825859 # number of cpu cycles simulated
-testsys.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-testsys.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-testsys.cpu.committedInsts 20257044 # Number of instructions committed
-testsys.cpu.committedOps 20257044 # Number of ops (including micro ops) committed
-testsys.cpu.num_int_alu_accesses 18836392 # Number of integer alu accesses
-testsys.cpu.num_fp_alu_accesses 17380 # Number of float alu accesses
-testsys.cpu.num_func_calls 1221158 # number of times a function call or return occured
-testsys.cpu.num_conditional_control_insts 1442105 # number of instructions that are conditional controls
-testsys.cpu.num_int_insts 18836392 # number of integer instructions
-testsys.cpu.num_fp_insts 17380 # number of float instructions
-testsys.cpu.num_int_register_reads 24786330 # number of times the integer registers were read
-testsys.cpu.num_int_register_writes 14693469 # number of times the integer registers were written
-testsys.cpu.num_fp_register_reads 11166 # number of times the floating registers were read
-testsys.cpu.num_fp_register_writes 10823 # number of times the floating registers were written
-testsys.cpu.num_mem_refs 6262732 # number of memory refs
-testsys.cpu.num_load_insts 3943883 # Number of load instructions
-testsys.cpu.num_store_insts 2318849 # Number of store instructions
-testsys.cpu.num_idle_cycles 380582482.461103 # Number of idle cycles
-testsys.cpu.num_busy_cycles 20243376.538897 # Number of busy cycles
-testsys.cpu.not_idle_fraction 0.050504 # Percentage of non-idle cycles
-testsys.cpu.idle_fraction 0.949496 # Percentage of idle cycles
-testsys.cpu.Branches 2929782 # Number of branches fetched
-testsys.cpu.op_class::No_OpClass 712785 3.52% 3.52% # Class of executed instruction
-testsys.cpu.op_class::IntAlu 12147004 59.95% 63.47% # Class of executed instruction
-testsys.cpu.op_class::IntMult 21654 0.11% 63.58% # Class of executed instruction
-testsys.cpu.op_class::IntDiv 0 0.00% 63.58% # Class of executed instruction
-testsys.cpu.op_class::FloatAdd 4655 0.02% 63.60% # Class of executed instruction
-testsys.cpu.op_class::FloatCmp 1 0.00% 63.60% # Class of executed instruction
-testsys.cpu.op_class::FloatCvt 0 0.00% 63.60% # Class of executed instruction
-testsys.cpu.op_class::FloatMult 0 0.00% 63.60% # Class of executed instruction
-testsys.cpu.op_class::FloatDiv 922 0.00% 63.60% # Class of executed instruction
-testsys.cpu.op_class::FloatSqrt 0 0.00% 63.60% # Class of executed instruction
-testsys.cpu.op_class::SimdAdd 0 0.00% 63.60% # Class of executed instruction
-testsys.cpu.op_class::SimdAddAcc 0 0.00% 63.60% # Class of executed instruction
-testsys.cpu.op_class::SimdAlu 0 0.00% 63.60% # Class of executed instruction
-testsys.cpu.op_class::SimdCmp 0 0.00% 63.60% # Class of executed instruction
-testsys.cpu.op_class::SimdCvt 0 0.00% 63.60% # Class of executed instruction
-testsys.cpu.op_class::SimdMisc 0 0.00% 63.60% # Class of executed instruction
-testsys.cpu.op_class::SimdMult 0 0.00% 63.60% # Class of executed instruction
-testsys.cpu.op_class::SimdMultAcc 0 0.00% 63.60% # Class of executed instruction
-testsys.cpu.op_class::SimdShift 0 0.00% 63.60% # Class of executed instruction
-testsys.cpu.op_class::SimdShiftAcc 0 0.00% 63.60% # Class of executed instruction
-testsys.cpu.op_class::SimdSqrt 0 0.00% 63.60% # Class of executed instruction
-testsys.cpu.op_class::SimdFloatAdd 0 0.00% 63.60% # Class of executed instruction
-testsys.cpu.op_class::SimdFloatAlu 0 0.00% 63.60% # Class of executed instruction
-testsys.cpu.op_class::SimdFloatCmp 0 0.00% 63.60% # Class of executed instruction
-testsys.cpu.op_class::SimdFloatCvt 0 0.00% 63.60% # Class of executed instruction
-testsys.cpu.op_class::SimdFloatDiv 0 0.00% 63.60% # Class of executed instruction
-testsys.cpu.op_class::SimdFloatMisc 0 0.00% 63.60% # Class of executed instruction
-testsys.cpu.op_class::SimdFloatMult 0 0.00% 63.60% # Class of executed instruction
-testsys.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.60% # Class of executed instruction
-testsys.cpu.op_class::SimdFloatSqrt 0 0.00% 63.60% # Class of executed instruction
-testsys.cpu.op_class::MemRead 4230485 20.88% 84.48% # Class of executed instruction
-testsys.cpu.op_class::MemWrite 2319388 11.45% 95.93% # Class of executed instruction
-testsys.cpu.op_class::IprAccess 824126 4.07% 100.00% # Class of executed instruction
-testsys.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-testsys.cpu.op_class::total 20261020 # Class of executed instruction
-testsys.cpu.kern.inst.arm 0 # number of arm instructions executed
-testsys.cpu.kern.inst.quiesce 19580 # number of quiesce instructions executed
-testsys.cpu.kern.inst.hwrei 153669 # number of hwrei instructions executed
-testsys.cpu.kern.ipl_count::0 62779 42.67% 42.67% # number of times we switched to this ipl
-testsys.cpu.kern.ipl_count::21 19625 13.34% 56.01% # number of times we switched to this ipl
-testsys.cpu.kern.ipl_count::22 205 0.14% 56.15% # number of times we switched to this ipl
-testsys.cpu.kern.ipl_count::31 64511 43.85% 100.00% # number of times we switched to this ipl
-testsys.cpu.kern.ipl_count::total 147120 # number of times we switched to this ipl
-testsys.cpu.kern.ipl_good::0 62773 43.18% 43.18% # number of times we switched to this ipl from a different ipl
-testsys.cpu.kern.ipl_good::21 19625 13.50% 56.67% # number of times we switched to this ipl from a different ipl
-testsys.cpu.kern.ipl_good::22 205 0.14% 56.82% # number of times we switched to this ipl from a different ipl
-testsys.cpu.kern.ipl_good::31 62785 43.18% 100.00% # number of times we switched to this ipl from a different ipl
-testsys.cpu.kern.ipl_good::total 145388 # number of times we switched to this ipl from a different ipl
-testsys.cpu.kern.ipl_ticks::0 194347611000 96.98% 96.98% # number of cycles we spent at this ipl
-testsys.cpu.kern.ipl_ticks::21 1588986000 0.79% 97.77% # number of cycles we spent at this ipl
-testsys.cpu.kern.ipl_ticks::22 8815000 0.00% 97.78% # number of cycles we spent at this ipl
-testsys.cpu.kern.ipl_ticks::31 4457946500 2.22% 100.00% # number of cycles we spent at this ipl
-testsys.cpu.kern.ipl_ticks::total 200403358500 # number of cycles we spent at this ipl
-testsys.cpu.kern.ipl_used::0 0.999904 # fraction of swpipl calls that actually changed the ipl
-testsys.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
-testsys.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
-testsys.cpu.kern.ipl_used::31 0.973245 # fraction of swpipl calls that actually changed the ipl
-testsys.cpu.kern.ipl_used::total 0.988227 # fraction of swpipl calls that actually changed the ipl
-testsys.cpu.kern.syscall::2 3 3.61% 3.61% # number of syscalls executed
-testsys.cpu.kern.syscall::3 7 8.43% 12.05% # number of syscalls executed
-testsys.cpu.kern.syscall::4 1 1.20% 13.25% # number of syscalls executed
-testsys.cpu.kern.syscall::6 7 8.43% 21.69% # number of syscalls executed
-testsys.cpu.kern.syscall::17 7 8.43% 30.12% # number of syscalls executed
-testsys.cpu.kern.syscall::19 2 2.41% 32.53% # number of syscalls executed
-testsys.cpu.kern.syscall::20 1 1.20% 33.73% # number of syscalls executed
-testsys.cpu.kern.syscall::33 3 3.61% 37.35% # number of syscalls executed
-testsys.cpu.kern.syscall::45 10 12.05% 49.40% # number of syscalls executed
-testsys.cpu.kern.syscall::48 5 6.02% 55.42% # number of syscalls executed
-testsys.cpu.kern.syscall::54 1 1.20% 56.63% # number of syscalls executed
-testsys.cpu.kern.syscall::59 3 3.61% 60.24% # number of syscalls executed
-testsys.cpu.kern.syscall::71 15 18.07% 78.31% # number of syscalls executed
-testsys.cpu.kern.syscall::74 4 4.82% 83.13% # number of syscalls executed
-testsys.cpu.kern.syscall::97 2 2.41% 85.54% # number of syscalls executed
-testsys.cpu.kern.syscall::98 2 2.41% 87.95% # number of syscalls executed
-testsys.cpu.kern.syscall::101 2 2.41% 90.36% # number of syscalls executed
-testsys.cpu.kern.syscall::102 2 2.41% 92.77% # number of syscalls executed
-testsys.cpu.kern.syscall::104 1 1.20% 93.98% # number of syscalls executed
-testsys.cpu.kern.syscall::105 3 3.61% 97.59% # number of syscalls executed
-testsys.cpu.kern.syscall::118 2 2.41% 100.00% # number of syscalls executed
-testsys.cpu.kern.syscall::total 83 # number of syscalls executed
-testsys.cpu.kern.callpal::swpctx 438 0.34% 0.34% # number of callpals executed
-testsys.cpu.kern.callpal::tbi 20 0.02% 0.36% # number of callpals executed
-testsys.cpu.kern.callpal::swpipl 106832 83.26% 83.62% # number of callpals executed
-testsys.cpu.kern.callpal::rdps 359 0.28% 83.90% # number of callpals executed
-testsys.cpu.kern.callpal::wrusp 3 0.00% 83.90% # number of callpals executed
-testsys.cpu.kern.callpal::rdusp 3 0.00% 83.90% # number of callpals executed
-testsys.cpu.kern.callpal::rti 20470 15.95% 99.86% # number of callpals executed
-testsys.cpu.kern.callpal::callsys 140 0.11% 99.97% # number of callpals executed
-testsys.cpu.kern.callpal::imb 44 0.03% 100.00% # number of callpals executed
-testsys.cpu.kern.callpal::total 128309 # number of callpals executed
-testsys.cpu.kern.mode_switch::kernel 1280 # number of protection mode switches
-testsys.cpu.kern.mode_switch::user 706 # number of protection mode switches
-testsys.cpu.kern.mode_switch::idle 19629 # number of protection mode switches
-testsys.cpu.kern.mode_good::kernel 711
-testsys.cpu.kern.mode_good::user 706
-testsys.cpu.kern.mode_good::idle 5
-testsys.cpu.kern.mode_switch_good::kernel 0.555469 # fraction of useful protection mode switches
-testsys.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
-testsys.cpu.kern.mode_switch_good::idle 0.000255 # fraction of useful protection mode switches
-testsys.cpu.kern.mode_switch_good::total 0.065788 # fraction of useful protection mode switches
-testsys.cpu.kern.mode_ticks::kernel 994253000 59.96% 59.96% # number of ticks spent at the given mode
-testsys.cpu.kern.mode_ticks::user 533088000 32.15% 92.11% # number of ticks spent at the given mode
-testsys.cpu.kern.mode_ticks::idle 130749000 7.89% 100.00% # number of ticks spent at the given mode
-testsys.cpu.kern.swap_context 438 # number of times the context was actually changed
-testsys.tsunami.ethernet.clk_domain.clock 2000 # Clock period in ticks
-testsys.tsunami.ethernet.txBytes 960 # Bytes Transmitted
-testsys.tsunami.ethernet.rxBytes 798 # Bytes Received
-testsys.tsunami.ethernet.txPackets 8 # Number of Packets Transmitted
-testsys.tsunami.ethernet.rxPackets 5 # Number of Packets Received
-testsys.tsunami.ethernet.txIpChecksums 2 # Number of tx IP Checksums done by device
-testsys.tsunami.ethernet.rxIpChecksums 5 # Number of rx IP Checksums done by device
-testsys.tsunami.ethernet.txTcpChecksums 2 # Number of tx TCP Checksums done by device
-testsys.tsunami.ethernet.rxTcpChecksums 5 # Number of rx TCP Checksums done by device
-testsys.tsunami.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
-testsys.tsunami.ethernet.rxUdpChecksums 0 # Number of rx UDP Checksums done by device
-testsys.tsunami.ethernet.descDMAReads 2385801 # Number of descriptors the device read w/ DMA
-testsys.tsunami.ethernet.descDMAWrites 13 # Number of descriptors the device wrote w/ DMA
-testsys.tsunami.ethernet.descDmaReadBytes 57259224 # number of descriptor bytes read w/ DMA
-testsys.tsunami.ethernet.descDmaWriteBytes 104 # number of descriptor bytes write w/ DMA
-testsys.tsunami.ethernet.totBandwidth 70176 # Total Bandwidth (bits/s)
-testsys.tsunami.ethernet.totPackets 13 # Total Packets
-testsys.tsunami.ethernet.totBytes 1758 # Total Bytes
-testsys.tsunami.ethernet.totPPS 65 # Total Tranmission Rate (packets/s)
-testsys.tsunami.ethernet.txBandwidth 38322 # Transmit Bandwidth (bits/s)
-testsys.tsunami.ethernet.rxBandwidth 31855 # Receive Bandwidth (bits/s)
-testsys.tsunami.ethernet.txPPS 40 # Packet Tranmission Rate (packets/s)
-testsys.tsunami.ethernet.rxPPS 25 # Packet Reception Rate (packets/s)
-testsys.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
-testsys.tsunami.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
-testsys.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
-testsys.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
-testsys.tsunami.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
-testsys.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
-testsys.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
-testsys.tsunami.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
-testsys.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
-testsys.tsunami.ethernet.postedRxDesc 5 # number of RxDesc interrupts posted to CPU
-testsys.tsunami.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
-testsys.tsunami.ethernet.totalRxDesc 5 # total number of RxDesc written to ISR
-testsys.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
-testsys.tsunami.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
-testsys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
-testsys.tsunami.ethernet.postedTxIdle 19571 # number of TxIdle interrupts posted to CPU
-testsys.tsunami.ethernet.coalescedTxIdle 1 # average number of TxIdle's coalesced into each post
-testsys.tsunami.ethernet.totalTxIdle 2385801 # total number of TxIdle written to ISR
-testsys.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
-testsys.tsunami.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
-testsys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
-testsys.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
-testsys.tsunami.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
-testsys.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
-testsys.tsunami.ethernet.coalescedTotal 1 # average number of interrupts coalesced into each post
-testsys.tsunami.ethernet.postedInterrupts 2385819 # number of posts to CPU
-testsys.tsunami.ethernet.droppedPackets 0 # number of packets dropped
-testsys.iobus.trans_dist::ReadReq 2483943 # Transaction distribution
-testsys.iobus.trans_dist::ReadResp 2483943 # Transaction distribution
-testsys.iobus.trans_dist::WriteReq 39573 # Transaction distribution
-testsys.iobus.trans_dist::WriteResp 39573 # Transaction distribution
-testsys.iobus.pkt_count_testsys.bridge.master::testsys.tsunami.cchip.pio 196204 # Packet count per connected master and slave (bytes)
-testsys.iobus.pkt_count_testsys.bridge.master::testsys.tsunami.io.pio 336 # Packet count per connected master and slave (bytes)
-testsys.iobus.pkt_count_testsys.bridge.master::testsys.tsunami.uart.pio 428 # Packet count per connected master and slave (bytes)
-testsys.iobus.pkt_count_testsys.bridge.master::testsys.tsunami.ethernet.pio 78330 # Packet count per connected master and slave (bytes)
-testsys.iobus.pkt_count_testsys.bridge.master::total 275298 # Packet count per connected master and slave (bytes)
-testsys.iobus.pkt_count_testsys.tsunami.ethernet.dma::testsys.iobridge.slave 4771734 # Packet count per connected master and slave (bytes)
-testsys.iobus.pkt_count_testsys.tsunami.ethernet.dma::total 4771734 # Packet count per connected master and slave (bytes)
-testsys.iobus.pkt_count::total 5047032 # Packet count per connected master and slave (bytes)
-testsys.iobus.pkt_size_testsys.bridge.master::testsys.tsunami.cchip.pio 784816 # Cumulative packet size per connected master and slave (bytes)
-testsys.iobus.pkt_size_testsys.bridge.master::testsys.tsunami.io.pio 462 # Cumulative packet size per connected master and slave (bytes)
-testsys.iobus.pkt_size_testsys.bridge.master::testsys.tsunami.uart.pio 214 # Cumulative packet size per connected master and slave (bytes)
-testsys.iobus.pkt_size_testsys.bridge.master::testsys.tsunami.ethernet.pio 156660 # Cumulative packet size per connected master and slave (bytes)
-testsys.iobus.pkt_size_testsys.bridge.master::total 942152 # Cumulative packet size per connected master and slave (bytes)
-testsys.iobus.pkt_size_testsys.tsunami.ethernet.dma::testsys.iobridge.slave 57261398 # Cumulative packet size per connected master and slave (bytes)
-testsys.iobus.pkt_size_testsys.tsunami.ethernet.dma::total 57261398 # Cumulative packet size per connected master and slave (bytes)
-testsys.iobus.pkt_size::total 58203550 # Cumulative packet size per connected master and slave (bytes)
drivesys.voltage_domain.voltage 1 # Voltage in Volts
drivesys.clk_domain.clock 1000 # Clock period in ticks
drivesys.physmem.bytes_read::cpu.inst 76205572 # Number of bytes read from this memory
drivesys.physmem.bw_total::cpu.data 204101955 # Total bandwidth to/from this memory (bytes/s)
drivesys.physmem.bw_total::tsunami.ethernet 285723379 # Total bandwidth to/from this memory (bytes/s)
drivesys.physmem.bw_total::total 870075068 # Total bandwidth to/from this memory (bytes/s)
-drivesys.membus.trans_dist::ReadReq 25081955 # Transaction distribution
-drivesys.membus.trans_dist::ReadResp 25182911 # Transaction distribution
-drivesys.membus.trans_dist::WriteReq 1963575 # Transaction distribution
-drivesys.membus.trans_dist::WriteResp 1963575 # Transaction distribution
-drivesys.membus.trans_dist::LoadLockedReq 100956 # Transaction distribution
-drivesys.membus.trans_dist::StoreCondReq 100924 # Transaction distribution
-drivesys.membus.trans_dist::StoreCondResp 100924 # Transaction distribution
-drivesys.membus.pkt_count_drivesys.cpu.icache_port::drivesys.physmem.port 38102786 # Packet count per connected master and slave (bytes)
-drivesys.membus.pkt_count_drivesys.cpu.icache_port::total 38102786 # Packet count per connected master and slave (bytes)
-drivesys.membus.pkt_count_drivesys.cpu.dcache_port::drivesys.bridge.slave 276632 # Packet count per connected master and slave (bytes)
-drivesys.membus.pkt_count_drivesys.cpu.dcache_port::drivesys.physmem.port 11343650 # Packet count per connected master and slave (bytes)
-drivesys.membus.pkt_count_drivesys.cpu.dcache_port::total 11620282 # Packet count per connected master and slave (bytes)
-drivesys.membus.pkt_count_drivesys.iobridge.master::drivesys.physmem.port 4771752 # Packet count per connected master and slave (bytes)
-drivesys.membus.pkt_count_drivesys.iobridge.master::total 4771752 # Packet count per connected master and slave (bytes)
-drivesys.membus.pkt_count::total 54494820 # Packet count per connected master and slave (bytes)
-drivesys.membus.pkt_size_drivesys.cpu.icache_port::drivesys.physmem.port 76205572 # Cumulative packet size per connected master and slave (bytes)
-drivesys.membus.pkt_size_drivesys.cpu.icache_port::total 76205572 # Cumulative packet size per connected master and slave (bytes)
-drivesys.membus.pkt_size_drivesys.cpu.dcache_port::drivesys.bridge.slave 948604 # Cumulative packet size per connected master and slave (bytes)
-drivesys.membus.pkt_size_drivesys.cpu.dcache_port::drivesys.physmem.port 40903924 # Cumulative packet size per connected master and slave (bytes)
-drivesys.membus.pkt_size_drivesys.cpu.dcache_port::total 41852528 # Cumulative packet size per connected master and slave (bytes)
-drivesys.membus.pkt_size_drivesys.iobridge.master::drivesys.physmem.port 57261614 # Cumulative packet size per connected master and slave (bytes)
-drivesys.membus.pkt_size_drivesys.iobridge.master::total 57261614 # Cumulative packet size per connected master and slave (bytes)
-drivesys.membus.pkt_size::total 175319714 # Cumulative packet size per connected master and slave (bytes)
-drivesys.membus.snoops 0 # Total snoops (count)
-drivesys.membus.snoop_fanout::samples 27109094 # Request fanout histogram
-drivesys.membus.snoop_fanout::mean 0.790778 # Request fanout histogram
-drivesys.membus.snoop_fanout::stdev 0.406753 # Request fanout histogram
-drivesys.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-drivesys.membus.snoop_fanout::0 5671825 20.92% 20.92% # Request fanout histogram
-drivesys.membus.snoop_fanout::1 21437269 79.08% 100.00% # Request fanout histogram
-drivesys.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-drivesys.membus.snoop_fanout::min_value 0 # Request fanout histogram
-drivesys.membus.snoop_fanout::max_value 1 # Request fanout histogram
-drivesys.membus.snoop_fanout::total 27109094 # Request fanout histogram
-drivesys.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
-drivesys.disk0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
-drivesys.disk0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
-drivesys.disk0.dma_write_full_pages 0 # Number of full page size DMA writes.
-drivesys.disk0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
-drivesys.disk0.dma_write_txs 0 # Number of DMA write transactions.
-drivesys.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
-drivesys.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
-drivesys.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
-drivesys.disk2.dma_write_full_pages 0 # Number of full page size DMA writes.
-drivesys.disk2.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
-drivesys.disk2.dma_write_txs 0 # Number of DMA write transactions.
drivesys.cpu.clk_domain.clock 250 # Clock period in ticks
drivesys.cpu.dtb.fetch_hits 0 # ITB hits
drivesys.cpu.dtb.fetch_misses 0 # ITB misses
drivesys.cpu.kern.mode_ticks::user 319668250 10.78% 13.41% # number of ticks spent at the given mode
drivesys.cpu.kern.mode_ticks::idle 2567942000 86.59% 100.00% # number of ticks spent at the given mode
drivesys.cpu.kern.swap_context 72 # number of times the context was actually changed
+drivesys.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
+drivesys.disk0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
+drivesys.disk0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
+drivesys.disk0.dma_write_full_pages 0 # Number of full page size DMA writes.
+drivesys.disk0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
+drivesys.disk0.dma_write_txs 0 # Number of DMA write transactions.
+drivesys.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
+drivesys.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
+drivesys.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
+drivesys.disk2.dma_write_full_pages 0 # Number of full page size DMA writes.
+drivesys.disk2.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
+drivesys.disk2.dma_write_txs 0 # Number of DMA write transactions.
+drivesys.iobus.trans_dist::ReadReq 2484469 # Transaction distribution
+drivesys.iobus.trans_dist::ReadResp 2484469 # Transaction distribution
+drivesys.iobus.trans_dist::WriteReq 39723 # Transaction distribution
+drivesys.iobus.trans_dist::WriteResp 39723 # Transaction distribution
+drivesys.iobus.pkt_count_drivesys.bridge.master::drivesys.tsunami.cchip.pio 197670 # Packet count per connected master and slave (bytes)
+drivesys.iobus.pkt_count_drivesys.bridge.master::drivesys.tsunami.ethernet.pio 78962 # Packet count per connected master and slave (bytes)
+drivesys.iobus.pkt_count_drivesys.bridge.master::total 276632 # Packet count per connected master and slave (bytes)
+drivesys.iobus.pkt_count_drivesys.tsunami.ethernet.dma::drivesys.iobridge.slave 4771752 # Packet count per connected master and slave (bytes)
+drivesys.iobus.pkt_count_drivesys.tsunami.ethernet.dma::total 4771752 # Packet count per connected master and slave (bytes)
+drivesys.iobus.pkt_count::total 5048384 # Packet count per connected master and slave (bytes)
+drivesys.iobus.pkt_size_drivesys.bridge.master::drivesys.tsunami.cchip.pio 790680 # Cumulative packet size per connected master and slave (bytes)
+drivesys.iobus.pkt_size_drivesys.bridge.master::drivesys.tsunami.ethernet.pio 157924 # Cumulative packet size per connected master and slave (bytes)
+drivesys.iobus.pkt_size_drivesys.bridge.master::total 948604 # Cumulative packet size per connected master and slave (bytes)
+drivesys.iobus.pkt_size_drivesys.tsunami.ethernet.dma::drivesys.iobridge.slave 57261614 # Cumulative packet size per connected master and slave (bytes)
+drivesys.iobus.pkt_size_drivesys.tsunami.ethernet.dma::total 57261614 # Cumulative packet size per connected master and slave (bytes)
+drivesys.iobus.pkt_size::total 58210218 # Cumulative packet size per connected master and slave (bytes)
+drivesys.membus.trans_dist::ReadReq 25081955 # Transaction distribution
+drivesys.membus.trans_dist::ReadResp 25182911 # Transaction distribution
+drivesys.membus.trans_dist::WriteReq 1963575 # Transaction distribution
+drivesys.membus.trans_dist::WriteResp 1963575 # Transaction distribution
+drivesys.membus.trans_dist::LoadLockedReq 100956 # Transaction distribution
+drivesys.membus.trans_dist::StoreCondReq 100924 # Transaction distribution
+drivesys.membus.trans_dist::StoreCondResp 100924 # Transaction distribution
+drivesys.membus.pkt_count_drivesys.cpu.icache_port::drivesys.physmem.port 38102786 # Packet count per connected master and slave (bytes)
+drivesys.membus.pkt_count_drivesys.cpu.icache_port::total 38102786 # Packet count per connected master and slave (bytes)
+drivesys.membus.pkt_count_drivesys.cpu.dcache_port::drivesys.bridge.slave 276632 # Packet count per connected master and slave (bytes)
+drivesys.membus.pkt_count_drivesys.cpu.dcache_port::drivesys.physmem.port 11343650 # Packet count per connected master and slave (bytes)
+drivesys.membus.pkt_count_drivesys.cpu.dcache_port::total 11620282 # Packet count per connected master and slave (bytes)
+drivesys.membus.pkt_count_drivesys.iobridge.master::drivesys.physmem.port 4771752 # Packet count per connected master and slave (bytes)
+drivesys.membus.pkt_count_drivesys.iobridge.master::total 4771752 # Packet count per connected master and slave (bytes)
+drivesys.membus.pkt_count::total 54494820 # Packet count per connected master and slave (bytes)
+drivesys.membus.pkt_size_drivesys.cpu.icache_port::drivesys.physmem.port 76205572 # Cumulative packet size per connected master and slave (bytes)
+drivesys.membus.pkt_size_drivesys.cpu.icache_port::total 76205572 # Cumulative packet size per connected master and slave (bytes)
+drivesys.membus.pkt_size_drivesys.cpu.dcache_port::drivesys.bridge.slave 948604 # Cumulative packet size per connected master and slave (bytes)
+drivesys.membus.pkt_size_drivesys.cpu.dcache_port::drivesys.physmem.port 40903924 # Cumulative packet size per connected master and slave (bytes)
+drivesys.membus.pkt_size_drivesys.cpu.dcache_port::total 41852528 # Cumulative packet size per connected master and slave (bytes)
+drivesys.membus.pkt_size_drivesys.iobridge.master::drivesys.physmem.port 57261614 # Cumulative packet size per connected master and slave (bytes)
+drivesys.membus.pkt_size_drivesys.iobridge.master::total 57261614 # Cumulative packet size per connected master and slave (bytes)
+drivesys.membus.pkt_size::total 175319714 # Cumulative packet size per connected master and slave (bytes)
+drivesys.membus.snoops 0 # Total snoops (count)
+drivesys.membus.snoop_fanout::samples 27109094 # Request fanout histogram
+drivesys.membus.snoop_fanout::mean 0.790778 # Request fanout histogram
+drivesys.membus.snoop_fanout::stdev 0.406753 # Request fanout histogram
+drivesys.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+drivesys.membus.snoop_fanout::0 5671825 20.92% 20.92% # Request fanout histogram
+drivesys.membus.snoop_fanout::1 21437269 79.08% 100.00% # Request fanout histogram
+drivesys.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+drivesys.membus.snoop_fanout::min_value 0 # Request fanout histogram
+drivesys.membus.snoop_fanout::max_value 1 # Request fanout histogram
+drivesys.membus.snoop_fanout::total 27109094 # Request fanout histogram
drivesys.tsunami.ethernet.clk_domain.clock 2000 # Clock period in ticks
drivesys.tsunami.ethernet.txBytes 798 # Bytes Transmitted
drivesys.tsunami.ethernet.rxBytes 960 # Bytes Received
drivesys.tsunami.ethernet.coalescedTotal 1 # average number of interrupts coalesced into each post
drivesys.tsunami.ethernet.postedInterrupts 2385831 # number of posts to CPU
drivesys.tsunami.ethernet.droppedPackets 0 # number of packets dropped
-drivesys.iobus.trans_dist::ReadReq 2484469 # Transaction distribution
-drivesys.iobus.trans_dist::ReadResp 2484469 # Transaction distribution
-drivesys.iobus.trans_dist::WriteReq 39723 # Transaction distribution
-drivesys.iobus.trans_dist::WriteResp 39723 # Transaction distribution
-drivesys.iobus.pkt_count_drivesys.bridge.master::drivesys.tsunami.cchip.pio 197670 # Packet count per connected master and slave (bytes)
-drivesys.iobus.pkt_count_drivesys.bridge.master::drivesys.tsunami.ethernet.pio 78962 # Packet count per connected master and slave (bytes)
-drivesys.iobus.pkt_count_drivesys.bridge.master::total 276632 # Packet count per connected master and slave (bytes)
-drivesys.iobus.pkt_count_drivesys.tsunami.ethernet.dma::drivesys.iobridge.slave 4771752 # Packet count per connected master and slave (bytes)
-drivesys.iobus.pkt_count_drivesys.tsunami.ethernet.dma::total 4771752 # Packet count per connected master and slave (bytes)
-drivesys.iobus.pkt_count::total 5048384 # Packet count per connected master and slave (bytes)
-drivesys.iobus.pkt_size_drivesys.bridge.master::drivesys.tsunami.cchip.pio 790680 # Cumulative packet size per connected master and slave (bytes)
-drivesys.iobus.pkt_size_drivesys.bridge.master::drivesys.tsunami.ethernet.pio 157924 # Cumulative packet size per connected master and slave (bytes)
-drivesys.iobus.pkt_size_drivesys.bridge.master::total 948604 # Cumulative packet size per connected master and slave (bytes)
-drivesys.iobus.pkt_size_drivesys.tsunami.ethernet.dma::drivesys.iobridge.slave 57261614 # Cumulative packet size per connected master and slave (bytes)
-drivesys.iobus.pkt_size_drivesys.tsunami.ethernet.dma::total 57261614 # Cumulative packet size per connected master and slave (bytes)
-drivesys.iobus.pkt_size::total 58210218 # Cumulative packet size per connected master and slave (bytes)
-
----------- End Simulation Statistics ----------
-
----------- Begin Simulation Statistics ----------
-sim_seconds 0.000407 # Number of seconds simulated
-sim_ticks 407341500 # Number of ticks simulated
-final_tick 4321620817500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 7893991697 # Simulator instruction rate (inst/s)
-host_op_rate 7892445581 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 6135954870 # Simulator tick rate (ticks/s)
-host_mem_usage 534848 # Number of bytes of host memory used
-host_seconds 0.07 # Real time elapsed on the host
-sim_insts 523853183 # Number of instructions simulated
-sim_ops 523853183 # Number of ops (including micro ops) simulated
testsys.voltage_domain.voltage 1 # Voltage in Volts
testsys.clk_domain.clock 1000 # Clock period in ticks
-testsys.physmem.bytes_read::cpu.inst 144504 # Number of bytes read from this memory
-testsys.physmem.bytes_read::cpu.data 49936 # Number of bytes read from this memory
-testsys.physmem.bytes_read::tsunami.ethernet 116376 # Number of bytes read from this memory
-testsys.physmem.bytes_read::total 310816 # Number of bytes read from this memory
-testsys.physmem.bytes_inst_read::cpu.inst 144504 # Number of instructions bytes read from this memory
-testsys.physmem.bytes_inst_read::total 144504 # Number of instructions bytes read from this memory
-testsys.physmem.bytes_written::cpu.data 27704 # Number of bytes written to this memory
-testsys.physmem.bytes_written::total 27704 # Number of bytes written to this memory
-testsys.physmem.num_reads::cpu.inst 36126 # Number of read requests responded to by this memory
-testsys.physmem.num_reads::cpu.data 6905 # Number of read requests responded to by this memory
-testsys.physmem.num_reads::tsunami.ethernet 4849 # Number of read requests responded to by this memory
-testsys.physmem.num_reads::total 47880 # Number of read requests responded to by this memory
-testsys.physmem.num_writes::cpu.data 3814 # Number of write requests responded to by this memory
-testsys.physmem.num_writes::total 3814 # Number of write requests responded to by this memory
-testsys.physmem.bw_read::cpu.inst 354749025 # Total read bandwidth from this memory (bytes/s)
-testsys.physmem.bw_read::cpu.data 122590014 # Total read bandwidth from this memory (bytes/s)
-testsys.physmem.bw_read::tsunami.ethernet 285696400 # Total read bandwidth from this memory (bytes/s)
-testsys.physmem.bw_read::total 763035438 # Total read bandwidth from this memory (bytes/s)
-testsys.physmem.bw_inst_read::cpu.inst 354749025 # Instruction read bandwidth from this memory (bytes/s)
-testsys.physmem.bw_inst_read::total 354749025 # Instruction read bandwidth from this memory (bytes/s)
-testsys.physmem.bw_write::cpu.data 68011730 # Write bandwidth from this memory (bytes/s)
-testsys.physmem.bw_write::total 68011730 # Write bandwidth from this memory (bytes/s)
-testsys.physmem.bw_total::cpu.inst 354749025 # Total bandwidth to/from this memory (bytes/s)
-testsys.physmem.bw_total::cpu.data 190601743 # Total bandwidth to/from this memory (bytes/s)
-testsys.physmem.bw_total::tsunami.ethernet 285696400 # Total bandwidth to/from this memory (bytes/s)
-testsys.physmem.bw_total::total 831047168 # Total bandwidth to/from this memory (bytes/s)
-testsys.membus.trans_dist::ReadReq 47876 # Transaction distribution
-testsys.membus.trans_dist::ReadResp 48080 # Transaction distribution
-testsys.membus.trans_dist::WriteReq 3691 # Transaction distribution
-testsys.membus.trans_dist::WriteResp 3691 # Transaction distribution
-testsys.membus.trans_dist::LoadLockedReq 204 # Transaction distribution
-testsys.membus.trans_dist::StoreCondReq 204 # Transaction distribution
-testsys.membus.trans_dist::StoreCondResp 204 # Transaction distribution
-testsys.membus.pkt_count_testsys.cpu.icache_port::testsys.physmem.port 72252 # Packet count per connected master and slave (bytes)
-testsys.membus.pkt_count_testsys.cpu.icache_port::total 72252 # Packet count per connected master and slave (bytes)
-testsys.membus.pkt_count_testsys.cpu.dcache_port::testsys.bridge.slave 562 # Packet count per connected master and slave (bytes)
-testsys.membus.pkt_count_testsys.cpu.dcache_port::testsys.physmem.port 21438 # Packet count per connected master and slave (bytes)
-testsys.membus.pkt_count_testsys.cpu.dcache_port::total 22000 # Packet count per connected master and slave (bytes)
-testsys.membus.pkt_count_testsys.iobridge.master::testsys.physmem.port 9698 # Packet count per connected master and slave (bytes)
-testsys.membus.pkt_count_testsys.iobridge.master::total 9698 # Packet count per connected master and slave (bytes)
-testsys.membus.pkt_count::total 103950 # Packet count per connected master and slave (bytes)
-testsys.membus.pkt_size_testsys.cpu.icache_port::testsys.physmem.port 144504 # Cumulative packet size per connected master and slave (bytes)
-testsys.membus.pkt_size_testsys.cpu.icache_port::total 144504 # Cumulative packet size per connected master and slave (bytes)
-testsys.membus.pkt_size_testsys.cpu.dcache_port::testsys.bridge.slave 1928 # Cumulative packet size per connected master and slave (bytes)
-testsys.membus.pkt_size_testsys.cpu.dcache_port::testsys.physmem.port 77640 # Cumulative packet size per connected master and slave (bytes)
-testsys.membus.pkt_size_testsys.cpu.dcache_port::total 79568 # Cumulative packet size per connected master and slave (bytes)
-testsys.membus.pkt_size_testsys.iobridge.master::testsys.physmem.port 116376 # Cumulative packet size per connected master and slave (bytes)
-testsys.membus.pkt_size_testsys.iobridge.master::total 116376 # Cumulative packet size per connected master and slave (bytes)
-testsys.membus.pkt_size::total 340448 # Cumulative packet size per connected master and slave (bytes)
-testsys.membus.snoops 0 # Total snoops (count)
-testsys.membus.snoop_fanout::samples 51694 # Request fanout histogram
-testsys.membus.snoop_fanout::mean 0.792645 # Request fanout histogram
-testsys.membus.snoop_fanout::stdev 0.405416 # Request fanout histogram
-testsys.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-testsys.membus.snoop_fanout::0 10719 20.74% 20.74% # Request fanout histogram
-testsys.membus.snoop_fanout::1 40975 79.26% 100.00% # Request fanout histogram
-testsys.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-testsys.membus.snoop_fanout::min_value 0 # Request fanout histogram
-testsys.membus.snoop_fanout::max_value 1 # Request fanout histogram
-testsys.membus.snoop_fanout::total 51694 # Request fanout histogram
-testsys.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
-testsys.disk0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
-testsys.disk0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
-testsys.disk0.dma_write_full_pages 0 # Number of full page size DMA writes.
-testsys.disk0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
-testsys.disk0.dma_write_txs 0 # Number of DMA write transactions.
-testsys.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
-testsys.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
-testsys.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
-testsys.disk2.dma_write_full_pages 0 # Number of full page size DMA writes.
-testsys.disk2.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
-testsys.disk2.dma_write_txs 0 # Number of DMA write transactions.
+testsys.physmem.bytes_read::cpu.inst 81044080 # Number of bytes read from this memory
+testsys.physmem.bytes_read::cpu.data 27825116 # Number of bytes read from this memory
+testsys.physmem.bytes_read::tsunami.ethernet 57260496 # Number of bytes read from this memory
+testsys.physmem.bytes_read::total 166129692 # Number of bytes read from this memory
+testsys.physmem.bytes_inst_read::cpu.inst 81044080 # Number of instructions bytes read from this memory
+testsys.physmem.bytes_inst_read::total 81044080 # Number of instructions bytes read from this memory
+testsys.physmem.bytes_written::cpu.data 16605404 # Number of bytes written to this memory
+testsys.physmem.bytes_written::tsunami.ethernet 902 # Number of bytes written to this memory
+testsys.physmem.bytes_written::total 16606306 # Number of bytes written to this memory
+testsys.physmem.num_reads::cpu.inst 20261020 # Number of read requests responded to by this memory
+testsys.physmem.num_reads::cpu.data 3842409 # Number of read requests responded to by this memory
+testsys.physmem.num_reads::tsunami.ethernet 2385836 # Number of read requests responded to by this memory
+testsys.physmem.num_reads::total 26489265 # Number of read requests responded to by this memory
+testsys.physmem.num_writes::cpu.data 2258228 # Number of write requests responded to by this memory
+testsys.physmem.num_writes::tsunami.ethernet 31 # Number of write requests responded to by this memory
+testsys.physmem.num_writes::total 2258259 # Number of write requests responded to by this memory
+testsys.physmem.bw_read::cpu.inst 404392869 # Total read bandwidth from this memory (bytes/s)
+testsys.physmem.bw_read::cpu.data 138841461 # Total read bandwidth from this memory (bytes/s)
+testsys.physmem.bw_read::tsunami.ethernet 285717800 # Total read bandwidth from this memory (bytes/s)
+testsys.physmem.bw_read::total 828952130 # Total read bandwidth from this memory (bytes/s)
+testsys.physmem.bw_inst_read::cpu.inst 404392869 # Instruction read bandwidth from this memory (bytes/s)
+testsys.physmem.bw_inst_read::total 404392869 # Instruction read bandwidth from this memory (bytes/s)
+testsys.physmem.bw_write::cpu.data 82857464 # Write bandwidth from this memory (bytes/s)
+testsys.physmem.bw_write::tsunami.ethernet 4501 # Write bandwidth from this memory (bytes/s)
+testsys.physmem.bw_write::total 82861965 # Write bandwidth from this memory (bytes/s)
+testsys.physmem.bw_total::cpu.inst 404392869 # Total bandwidth to/from this memory (bytes/s)
+testsys.physmem.bw_total::cpu.data 221698925 # Total bandwidth to/from this memory (bytes/s)
+testsys.physmem.bw_total::tsunami.ethernet 285722301 # Total bandwidth to/from this memory (bytes/s)
+testsys.physmem.bw_total::total 911814095 # Total bandwidth to/from this memory (bytes/s)
testsys.cpu.clk_domain.clock 500 # Clock period in ticks
testsys.cpu.dtb.fetch_hits 0 # ITB hits
testsys.cpu.dtb.fetch_misses 0 # ITB misses
testsys.cpu.dtb.fetch_acv 0 # ITB acv
testsys.cpu.dtb.fetch_accesses 0 # ITB accesses
-testsys.cpu.dtb.read_hits 7065 # DTB read hits
-testsys.cpu.dtb.read_misses 0 # DTB read misses
-testsys.cpu.dtb.read_acv 0 # DTB read access violations
-testsys.cpu.dtb.read_accesses 0 # DTB read accesses
-testsys.cpu.dtb.write_hits 3935 # DTB write hits
-testsys.cpu.dtb.write_misses 0 # DTB write misses
-testsys.cpu.dtb.write_acv 0 # DTB write access violations
-testsys.cpu.dtb.write_accesses 0 # DTB write accesses
-testsys.cpu.dtb.data_hits 11000 # DTB hits
-testsys.cpu.dtb.data_misses 0 # DTB misses
-testsys.cpu.dtb.data_acv 0 # DTB access violations
-testsys.cpu.dtb.data_accesses 0 # DTB accesses
-testsys.cpu.itb.fetch_hits 5992 # ITB hits
-testsys.cpu.itb.fetch_misses 0 # ITB misses
-testsys.cpu.itb.fetch_acv 0 # ITB acv
-testsys.cpu.itb.fetch_accesses 5992 # ITB accesses
+testsys.cpu.dtb.read_hits 3916768 # DTB read hits
+testsys.cpu.dtb.read_misses 3287 # DTB read misses
+testsys.cpu.dtb.read_acv 80 # DTB read access violations
+testsys.cpu.dtb.read_accesses 225414 # DTB read accesses
+testsys.cpu.dtb.write_hits 2316721 # DTB write hits
+testsys.cpu.dtb.write_misses 528 # DTB write misses
+testsys.cpu.dtb.write_acv 81 # DTB write access violations
+testsys.cpu.dtb.write_accesses 109988 # DTB write accesses
+testsys.cpu.dtb.data_hits 6233489 # DTB hits
+testsys.cpu.dtb.data_misses 3815 # DTB misses
+testsys.cpu.dtb.data_acv 161 # DTB access violations
+testsys.cpu.dtb.data_accesses 335402 # DTB accesses
+testsys.cpu.itb.fetch_hits 4052237 # ITB hits
+testsys.cpu.itb.fetch_misses 1497 # ITB misses
+testsys.cpu.itb.fetch_acv 69 # ITB acv
+testsys.cpu.itb.fetch_accesses 4053734 # ITB accesses
testsys.cpu.itb.read_hits 0 # DTB read hits
testsys.cpu.itb.read_misses 0 # DTB read misses
testsys.cpu.itb.read_acv 0 # DTB read access violations
testsys.cpu.itb.data_misses 0 # DTB misses
testsys.cpu.itb.data_acv 0 # DTB access violations
testsys.cpu.itb.data_accesses 0 # DTB accesses
-testsys.cpu.numCycles 821056 # number of cpu cycles simulated
+testsys.cpu.numCycles 400825859 # number of cpu cycles simulated
testsys.cpu.numWorkItemsStarted 0 # number of work items this cpu started
testsys.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-testsys.cpu.committedInsts 36126 # Number of instructions committed
-testsys.cpu.committedOps 36126 # Number of ops (including micro ops) committed
-testsys.cpu.num_int_alu_accesses 33492 # Number of integer alu accesses
-testsys.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
-testsys.cpu.num_func_calls 2384 # number of times a function call or return occured
-testsys.cpu.num_conditional_control_insts 2346 # number of instructions that are conditional controls
-testsys.cpu.num_int_insts 33492 # number of integer instructions
-testsys.cpu.num_fp_insts 0 # number of float instructions
-testsys.cpu.num_int_register_reads 43747 # number of times the integer registers were read
-testsys.cpu.num_int_register_writes 26476 # number of times the integer registers were written
-testsys.cpu.num_fp_register_reads 0 # number of times the floating registers were read
-testsys.cpu.num_fp_register_writes 0 # number of times the floating registers were written
-testsys.cpu.num_mem_refs 11041 # number of memory refs
-testsys.cpu.num_load_insts 7105 # Number of load instructions
-testsys.cpu.num_store_insts 3936 # Number of store instructions
-testsys.cpu.num_idle_cycles 784687.711054 # Number of idle cycles
-testsys.cpu.num_busy_cycles 36368.288946 # Number of busy cycles
-testsys.cpu.not_idle_fraction 0.044295 # Percentage of non-idle cycles
-testsys.cpu.idle_fraction 0.955705 # Percentage of idle cycles
-testsys.cpu.Branches 5238 # Number of branches fetched
-testsys.cpu.op_class::No_OpClass 1261 3.49% 3.49% # Class of executed instruction
-testsys.cpu.op_class::IntAlu 21664 59.97% 63.46% # Class of executed instruction
-testsys.cpu.op_class::IntMult 44 0.12% 63.58% # Class of executed instruction
+testsys.cpu.committedInsts 20257044 # Number of instructions committed
+testsys.cpu.committedOps 20257044 # Number of ops (including micro ops) committed
+testsys.cpu.num_int_alu_accesses 18836392 # Number of integer alu accesses
+testsys.cpu.num_fp_alu_accesses 17380 # Number of float alu accesses
+testsys.cpu.num_func_calls 1221158 # number of times a function call or return occured
+testsys.cpu.num_conditional_control_insts 1442105 # number of instructions that are conditional controls
+testsys.cpu.num_int_insts 18836392 # number of integer instructions
+testsys.cpu.num_fp_insts 17380 # number of float instructions
+testsys.cpu.num_int_register_reads 24786330 # number of times the integer registers were read
+testsys.cpu.num_int_register_writes 14693469 # number of times the integer registers were written
+testsys.cpu.num_fp_register_reads 11166 # number of times the floating registers were read
+testsys.cpu.num_fp_register_writes 10823 # number of times the floating registers were written
+testsys.cpu.num_mem_refs 6262732 # number of memory refs
+testsys.cpu.num_load_insts 3943883 # Number of load instructions
+testsys.cpu.num_store_insts 2318849 # Number of store instructions
+testsys.cpu.num_idle_cycles 380582482.461103 # Number of idle cycles
+testsys.cpu.num_busy_cycles 20243376.538897 # Number of busy cycles
+testsys.cpu.not_idle_fraction 0.050504 # Percentage of non-idle cycles
+testsys.cpu.idle_fraction 0.949496 # Percentage of idle cycles
+testsys.cpu.Branches 2929782 # Number of branches fetched
+testsys.cpu.op_class::No_OpClass 712785 3.52% 3.52% # Class of executed instruction
+testsys.cpu.op_class::IntAlu 12147004 59.95% 63.47% # Class of executed instruction
+testsys.cpu.op_class::IntMult 21654 0.11% 63.58% # Class of executed instruction
testsys.cpu.op_class::IntDiv 0 0.00% 63.58% # Class of executed instruction
-testsys.cpu.op_class::FloatAdd 0 0.00% 63.58% # Class of executed instruction
-testsys.cpu.op_class::FloatCmp 0 0.00% 63.58% # Class of executed instruction
-testsys.cpu.op_class::FloatCvt 0 0.00% 63.58% # Class of executed instruction
-testsys.cpu.op_class::FloatMult 0 0.00% 63.58% # Class of executed instruction
-testsys.cpu.op_class::FloatDiv 0 0.00% 63.58% # Class of executed instruction
-testsys.cpu.op_class::FloatSqrt 0 0.00% 63.58% # Class of executed instruction
-testsys.cpu.op_class::SimdAdd 0 0.00% 63.58% # Class of executed instruction
-testsys.cpu.op_class::SimdAddAcc 0 0.00% 63.58% # Class of executed instruction
-testsys.cpu.op_class::SimdAlu 0 0.00% 63.58% # Class of executed instruction
-testsys.cpu.op_class::SimdCmp 0 0.00% 63.58% # Class of executed instruction
-testsys.cpu.op_class::SimdCvt 0 0.00% 63.58% # Class of executed instruction
-testsys.cpu.op_class::SimdMisc 0 0.00% 63.58% # Class of executed instruction
-testsys.cpu.op_class::SimdMult 0 0.00% 63.58% # Class of executed instruction
-testsys.cpu.op_class::SimdMultAcc 0 0.00% 63.58% # Class of executed instruction
-testsys.cpu.op_class::SimdShift 0 0.00% 63.58% # Class of executed instruction
-testsys.cpu.op_class::SimdShiftAcc 0 0.00% 63.58% # Class of executed instruction
-testsys.cpu.op_class::SimdSqrt 0 0.00% 63.58% # Class of executed instruction
-testsys.cpu.op_class::SimdFloatAdd 0 0.00% 63.58% # Class of executed instruction
-testsys.cpu.op_class::SimdFloatAlu 0 0.00% 63.58% # Class of executed instruction
-testsys.cpu.op_class::SimdFloatCmp 0 0.00% 63.58% # Class of executed instruction
-testsys.cpu.op_class::SimdFloatCvt 0 0.00% 63.58% # Class of executed instruction
-testsys.cpu.op_class::SimdFloatDiv 0 0.00% 63.58% # Class of executed instruction
-testsys.cpu.op_class::SimdFloatMisc 0 0.00% 63.58% # Class of executed instruction
-testsys.cpu.op_class::SimdFloatMult 0 0.00% 63.58% # Class of executed instruction
-testsys.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.58% # Class of executed instruction
-testsys.cpu.op_class::SimdFloatSqrt 0 0.00% 63.58% # Class of executed instruction
-testsys.cpu.op_class::MemRead 7674 21.24% 84.82% # Class of executed instruction
-testsys.cpu.op_class::MemWrite 3938 10.90% 95.72% # Class of executed instruction
-testsys.cpu.op_class::IprAccess 1545 4.28% 100.00% # Class of executed instruction
+testsys.cpu.op_class::FloatAdd 4655 0.02% 63.60% # Class of executed instruction
+testsys.cpu.op_class::FloatCmp 1 0.00% 63.60% # Class of executed instruction
+testsys.cpu.op_class::FloatCvt 0 0.00% 63.60% # Class of executed instruction
+testsys.cpu.op_class::FloatMult 0 0.00% 63.60% # Class of executed instruction
+testsys.cpu.op_class::FloatDiv 922 0.00% 63.60% # Class of executed instruction
+testsys.cpu.op_class::FloatSqrt 0 0.00% 63.60% # Class of executed instruction
+testsys.cpu.op_class::SimdAdd 0 0.00% 63.60% # Class of executed instruction
+testsys.cpu.op_class::SimdAddAcc 0 0.00% 63.60% # Class of executed instruction
+testsys.cpu.op_class::SimdAlu 0 0.00% 63.60% # Class of executed instruction
+testsys.cpu.op_class::SimdCmp 0 0.00% 63.60% # Class of executed instruction
+testsys.cpu.op_class::SimdCvt 0 0.00% 63.60% # Class of executed instruction
+testsys.cpu.op_class::SimdMisc 0 0.00% 63.60% # Class of executed instruction
+testsys.cpu.op_class::SimdMult 0 0.00% 63.60% # Class of executed instruction
+testsys.cpu.op_class::SimdMultAcc 0 0.00% 63.60% # Class of executed instruction
+testsys.cpu.op_class::SimdShift 0 0.00% 63.60% # Class of executed instruction
+testsys.cpu.op_class::SimdShiftAcc 0 0.00% 63.60% # Class of executed instruction
+testsys.cpu.op_class::SimdSqrt 0 0.00% 63.60% # Class of executed instruction
+testsys.cpu.op_class::SimdFloatAdd 0 0.00% 63.60% # Class of executed instruction
+testsys.cpu.op_class::SimdFloatAlu 0 0.00% 63.60% # Class of executed instruction
+testsys.cpu.op_class::SimdFloatCmp 0 0.00% 63.60% # Class of executed instruction
+testsys.cpu.op_class::SimdFloatCvt 0 0.00% 63.60% # Class of executed instruction
+testsys.cpu.op_class::SimdFloatDiv 0 0.00% 63.60% # Class of executed instruction
+testsys.cpu.op_class::SimdFloatMisc 0 0.00% 63.60% # Class of executed instruction
+testsys.cpu.op_class::SimdFloatMult 0 0.00% 63.60% # Class of executed instruction
+testsys.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.60% # Class of executed instruction
+testsys.cpu.op_class::SimdFloatSqrt 0 0.00% 63.60% # Class of executed instruction
+testsys.cpu.op_class::MemRead 4230485 20.88% 84.48% # Class of executed instruction
+testsys.cpu.op_class::MemWrite 2319388 11.45% 95.93% # Class of executed instruction
+testsys.cpu.op_class::IprAccess 824126 4.07% 100.00% # Class of executed instruction
testsys.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-testsys.cpu.op_class::total 36126 # Class of executed instruction
+testsys.cpu.op_class::total 20261020 # Class of executed instruction
testsys.cpu.kern.inst.arm 0 # number of arm instructions executed
-testsys.cpu.kern.inst.quiesce 40 # number of quiesce instructions executed
-testsys.cpu.kern.inst.hwrei 295 # number of hwrei instructions executed
-testsys.cpu.kern.ipl_count::0 123 41.84% 41.84% # number of times we switched to this ipl
-testsys.cpu.kern.ipl_count::21 40 13.61% 55.44% # number of times we switched to this ipl
-testsys.cpu.kern.ipl_count::22 1 0.34% 55.78% # number of times we switched to this ipl
-testsys.cpu.kern.ipl_count::31 130 44.22% 100.00% # number of times we switched to this ipl
-testsys.cpu.kern.ipl_count::total 294 # number of times we switched to this ipl
-testsys.cpu.kern.ipl_good::0 123 42.86% 42.86% # number of times we switched to this ipl from a different ipl
-testsys.cpu.kern.ipl_good::21 40 13.94% 56.79% # number of times we switched to this ipl from a different ipl
-testsys.cpu.kern.ipl_good::22 1 0.35% 57.14% # number of times we switched to this ipl from a different ipl
-testsys.cpu.kern.ipl_good::31 123 42.86% 100.00% # number of times we switched to this ipl from a different ipl
-testsys.cpu.kern.ipl_good::total 287 # number of times we switched to this ipl from a different ipl
-testsys.cpu.kern.ipl_ticks::0 397967000 96.95% 96.95% # number of cycles we spent at this ipl
-testsys.cpu.kern.ipl_ticks::21 3240000 0.79% 97.73% # number of cycles we spent at this ipl
-testsys.cpu.kern.ipl_ticks::22 43000 0.01% 97.74% # number of cycles we spent at this ipl
-testsys.cpu.kern.ipl_ticks::31 9258000 2.26% 100.00% # number of cycles we spent at this ipl
-testsys.cpu.kern.ipl_ticks::total 410508000 # number of cycles we spent at this ipl
-testsys.cpu.kern.ipl_used::0 1 # fraction of swpipl calls that actually changed the ipl
+testsys.cpu.kern.inst.quiesce 19580 # number of quiesce instructions executed
+testsys.cpu.kern.inst.hwrei 153669 # number of hwrei instructions executed
+testsys.cpu.kern.ipl_count::0 62779 42.67% 42.67% # number of times we switched to this ipl
+testsys.cpu.kern.ipl_count::21 19625 13.34% 56.01% # number of times we switched to this ipl
+testsys.cpu.kern.ipl_count::22 205 0.14% 56.15% # number of times we switched to this ipl
+testsys.cpu.kern.ipl_count::31 64511 43.85% 100.00% # number of times we switched to this ipl
+testsys.cpu.kern.ipl_count::total 147120 # number of times we switched to this ipl
+testsys.cpu.kern.ipl_good::0 62773 43.18% 43.18% # number of times we switched to this ipl from a different ipl
+testsys.cpu.kern.ipl_good::21 19625 13.50% 56.67% # number of times we switched to this ipl from a different ipl
+testsys.cpu.kern.ipl_good::22 205 0.14% 56.82% # number of times we switched to this ipl from a different ipl
+testsys.cpu.kern.ipl_good::31 62785 43.18% 100.00% # number of times we switched to this ipl from a different ipl
+testsys.cpu.kern.ipl_good::total 145388 # number of times we switched to this ipl from a different ipl
+testsys.cpu.kern.ipl_ticks::0 194347611000 96.98% 96.98% # number of cycles we spent at this ipl
+testsys.cpu.kern.ipl_ticks::21 1588986000 0.79% 97.77% # number of cycles we spent at this ipl
+testsys.cpu.kern.ipl_ticks::22 8815000 0.00% 97.78% # number of cycles we spent at this ipl
+testsys.cpu.kern.ipl_ticks::31 4457946500 2.22% 100.00% # number of cycles we spent at this ipl
+testsys.cpu.kern.ipl_ticks::total 200403358500 # number of cycles we spent at this ipl
+testsys.cpu.kern.ipl_used::0 0.999904 # fraction of swpipl calls that actually changed the ipl
testsys.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
testsys.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
-testsys.cpu.kern.ipl_used::31 0.946154 # fraction of swpipl calls that actually changed the ipl
-testsys.cpu.kern.ipl_used::total 0.976190 # fraction of swpipl calls that actually changed the ipl
-testsys.cpu.kern.callpal::swpipl 212 83.46% 83.46% # number of callpals executed
-testsys.cpu.kern.callpal::rdps 1 0.39% 83.86% # number of callpals executed
-testsys.cpu.kern.callpal::rti 41 16.14% 100.00% # number of callpals executed
-testsys.cpu.kern.callpal::total 254 # number of callpals executed
-testsys.cpu.kern.mode_switch::kernel 0 # number of protection mode switches
-testsys.cpu.kern.mode_switch::user 0 # number of protection mode switches
-testsys.cpu.kern.mode_switch::idle 41 # number of protection mode switches
-testsys.cpu.kern.mode_good::kernel 0
-testsys.cpu.kern.mode_good::user 0
-testsys.cpu.kern.mode_good::idle 0
-testsys.cpu.kern.mode_switch_good::kernel nan # fraction of useful protection mode switches
-testsys.cpu.kern.mode_switch_good::user nan # fraction of useful protection mode switches
-testsys.cpu.kern.mode_switch_good::idle 0 # fraction of useful protection mode switches
-testsys.cpu.kern.mode_switch_good::total 0 # fraction of useful protection mode switches
-testsys.cpu.kern.mode_ticks::kernel 0 # number of ticks spent at the given mode
-testsys.cpu.kern.mode_ticks::user 0 # number of ticks spent at the given mode
-testsys.cpu.kern.mode_ticks::idle 0 # number of ticks spent at the given mode
-testsys.cpu.kern.swap_context 0 # number of times the context was actually changed
+testsys.cpu.kern.ipl_used::31 0.973245 # fraction of swpipl calls that actually changed the ipl
+testsys.cpu.kern.ipl_used::total 0.988227 # fraction of swpipl calls that actually changed the ipl
+testsys.cpu.kern.syscall::2 3 3.61% 3.61% # number of syscalls executed
+testsys.cpu.kern.syscall::3 7 8.43% 12.05% # number of syscalls executed
+testsys.cpu.kern.syscall::4 1 1.20% 13.25% # number of syscalls executed
+testsys.cpu.kern.syscall::6 7 8.43% 21.69% # number of syscalls executed
+testsys.cpu.kern.syscall::17 7 8.43% 30.12% # number of syscalls executed
+testsys.cpu.kern.syscall::19 2 2.41% 32.53% # number of syscalls executed
+testsys.cpu.kern.syscall::20 1 1.20% 33.73% # number of syscalls executed
+testsys.cpu.kern.syscall::33 3 3.61% 37.35% # number of syscalls executed
+testsys.cpu.kern.syscall::45 10 12.05% 49.40% # number of syscalls executed
+testsys.cpu.kern.syscall::48 5 6.02% 55.42% # number of syscalls executed
+testsys.cpu.kern.syscall::54 1 1.20% 56.63% # number of syscalls executed
+testsys.cpu.kern.syscall::59 3 3.61% 60.24% # number of syscalls executed
+testsys.cpu.kern.syscall::71 15 18.07% 78.31% # number of syscalls executed
+testsys.cpu.kern.syscall::74 4 4.82% 83.13% # number of syscalls executed
+testsys.cpu.kern.syscall::97 2 2.41% 85.54% # number of syscalls executed
+testsys.cpu.kern.syscall::98 2 2.41% 87.95% # number of syscalls executed
+testsys.cpu.kern.syscall::101 2 2.41% 90.36% # number of syscalls executed
+testsys.cpu.kern.syscall::102 2 2.41% 92.77% # number of syscalls executed
+testsys.cpu.kern.syscall::104 1 1.20% 93.98% # number of syscalls executed
+testsys.cpu.kern.syscall::105 3 3.61% 97.59% # number of syscalls executed
+testsys.cpu.kern.syscall::118 2 2.41% 100.00% # number of syscalls executed
+testsys.cpu.kern.syscall::total 83 # number of syscalls executed
+testsys.cpu.kern.callpal::swpctx 438 0.34% 0.34% # number of callpals executed
+testsys.cpu.kern.callpal::tbi 20 0.02% 0.36% # number of callpals executed
+testsys.cpu.kern.callpal::swpipl 106832 83.26% 83.62% # number of callpals executed
+testsys.cpu.kern.callpal::rdps 359 0.28% 83.90% # number of callpals executed
+testsys.cpu.kern.callpal::wrusp 3 0.00% 83.90% # number of callpals executed
+testsys.cpu.kern.callpal::rdusp 3 0.00% 83.90% # number of callpals executed
+testsys.cpu.kern.callpal::rti 20470 15.95% 99.86% # number of callpals executed
+testsys.cpu.kern.callpal::callsys 140 0.11% 99.97% # number of callpals executed
+testsys.cpu.kern.callpal::imb 44 0.03% 100.00% # number of callpals executed
+testsys.cpu.kern.callpal::total 128309 # number of callpals executed
+testsys.cpu.kern.mode_switch::kernel 1280 # number of protection mode switches
+testsys.cpu.kern.mode_switch::user 706 # number of protection mode switches
+testsys.cpu.kern.mode_switch::idle 19629 # number of protection mode switches
+testsys.cpu.kern.mode_good::kernel 711
+testsys.cpu.kern.mode_good::user 706
+testsys.cpu.kern.mode_good::idle 5
+testsys.cpu.kern.mode_switch_good::kernel 0.555469 # fraction of useful protection mode switches
+testsys.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
+testsys.cpu.kern.mode_switch_good::idle 0.000255 # fraction of useful protection mode switches
+testsys.cpu.kern.mode_switch_good::total 0.065788 # fraction of useful protection mode switches
+testsys.cpu.kern.mode_ticks::kernel 994253000 59.96% 59.96% # number of ticks spent at the given mode
+testsys.cpu.kern.mode_ticks::user 533088000 32.15% 92.11% # number of ticks spent at the given mode
+testsys.cpu.kern.mode_ticks::idle 130749000 7.89% 100.00% # number of ticks spent at the given mode
+testsys.cpu.kern.swap_context 438 # number of times the context was actually changed
+testsys.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
+testsys.disk0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
+testsys.disk0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
+testsys.disk0.dma_write_full_pages 0 # Number of full page size DMA writes.
+testsys.disk0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
+testsys.disk0.dma_write_txs 0 # Number of DMA write transactions.
+testsys.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
+testsys.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
+testsys.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
+testsys.disk2.dma_write_full_pages 0 # Number of full page size DMA writes.
+testsys.disk2.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
+testsys.disk2.dma_write_txs 0 # Number of DMA write transactions.
+testsys.iobus.trans_dist::ReadReq 2483943 # Transaction distribution
+testsys.iobus.trans_dist::ReadResp 2483943 # Transaction distribution
+testsys.iobus.trans_dist::WriteReq 39573 # Transaction distribution
+testsys.iobus.trans_dist::WriteResp 39573 # Transaction distribution
+testsys.iobus.pkt_count_testsys.bridge.master::testsys.tsunami.cchip.pio 196204 # Packet count per connected master and slave (bytes)
+testsys.iobus.pkt_count_testsys.bridge.master::testsys.tsunami.io.pio 336 # Packet count per connected master and slave (bytes)
+testsys.iobus.pkt_count_testsys.bridge.master::testsys.tsunami.uart.pio 428 # Packet count per connected master and slave (bytes)
+testsys.iobus.pkt_count_testsys.bridge.master::testsys.tsunami.ethernet.pio 78330 # Packet count per connected master and slave (bytes)
+testsys.iobus.pkt_count_testsys.bridge.master::total 275298 # Packet count per connected master and slave (bytes)
+testsys.iobus.pkt_count_testsys.tsunami.ethernet.dma::testsys.iobridge.slave 4771734 # Packet count per connected master and slave (bytes)
+testsys.iobus.pkt_count_testsys.tsunami.ethernet.dma::total 4771734 # Packet count per connected master and slave (bytes)
+testsys.iobus.pkt_count::total 5047032 # Packet count per connected master and slave (bytes)
+testsys.iobus.pkt_size_testsys.bridge.master::testsys.tsunami.cchip.pio 784816 # Cumulative packet size per connected master and slave (bytes)
+testsys.iobus.pkt_size_testsys.bridge.master::testsys.tsunami.io.pio 462 # Cumulative packet size per connected master and slave (bytes)
+testsys.iobus.pkt_size_testsys.bridge.master::testsys.tsunami.uart.pio 214 # Cumulative packet size per connected master and slave (bytes)
+testsys.iobus.pkt_size_testsys.bridge.master::testsys.tsunami.ethernet.pio 156660 # Cumulative packet size per connected master and slave (bytes)
+testsys.iobus.pkt_size_testsys.bridge.master::total 942152 # Cumulative packet size per connected master and slave (bytes)
+testsys.iobus.pkt_size_testsys.tsunami.ethernet.dma::testsys.iobridge.slave 57261398 # Cumulative packet size per connected master and slave (bytes)
+testsys.iobus.pkt_size_testsys.tsunami.ethernet.dma::total 57261398 # Cumulative packet size per connected master and slave (bytes)
+testsys.iobus.pkt_size::total 58203550 # Cumulative packet size per connected master and slave (bytes)
+testsys.membus.trans_dist::ReadReq 26478762 # Transaction distribution
+testsys.membus.trans_dist::ReadResp 26587372 # Transaction distribution
+testsys.membus.trans_dist::WriteReq 2189273 # Transaction distribution
+testsys.membus.trans_dist::WriteResp 2189273 # Transaction distribution
+testsys.membus.trans_dist::LoadLockedReq 108610 # Transaction distribution
+testsys.membus.trans_dist::StoreCondReq 108528 # Transaction distribution
+testsys.membus.trans_dist::StoreCondResp 108528 # Transaction distribution
+testsys.membus.pkt_count_testsys.cpu.icache_port::testsys.physmem.port 40522040 # Packet count per connected master and slave (bytes)
+testsys.membus.pkt_count_testsys.cpu.icache_port::total 40522040 # Packet count per connected master and slave (bytes)
+testsys.membus.pkt_count_testsys.cpu.dcache_port::testsys.bridge.slave 275298 # Packet count per connected master and slave (bytes)
+testsys.membus.pkt_count_testsys.cpu.dcache_port::testsys.physmem.port 12201274 # Packet count per connected master and slave (bytes)
+testsys.membus.pkt_count_testsys.cpu.dcache_port::total 12476572 # Packet count per connected master and slave (bytes)
+testsys.membus.pkt_count_testsys.iobridge.master::testsys.physmem.port 4771734 # Packet count per connected master and slave (bytes)
+testsys.membus.pkt_count_testsys.iobridge.master::total 4771734 # Packet count per connected master and slave (bytes)
+testsys.membus.pkt_count::total 57770346 # Packet count per connected master and slave (bytes)
+testsys.membus.pkt_size_testsys.cpu.icache_port::testsys.physmem.port 81044080 # Cumulative packet size per connected master and slave (bytes)
+testsys.membus.pkt_size_testsys.cpu.icache_port::total 81044080 # Cumulative packet size per connected master and slave (bytes)
+testsys.membus.pkt_size_testsys.cpu.dcache_port::testsys.bridge.slave 942152 # Cumulative packet size per connected master and slave (bytes)
+testsys.membus.pkt_size_testsys.cpu.dcache_port::testsys.physmem.port 44430520 # Cumulative packet size per connected master and slave (bytes)
+testsys.membus.pkt_size_testsys.cpu.dcache_port::total 45372672 # Cumulative packet size per connected master and slave (bytes)
+testsys.membus.pkt_size_testsys.iobridge.master::testsys.physmem.port 57261398 # Cumulative packet size per connected master and slave (bytes)
+testsys.membus.pkt_size_testsys.iobridge.master::total 57261398 # Cumulative packet size per connected master and slave (bytes)
+testsys.membus.pkt_size::total 183678150 # Cumulative packet size per connected master and slave (bytes)
+testsys.membus.snoops 0 # Total snoops (count)
+testsys.membus.snoop_fanout::samples 28747524 # Request fanout histogram
+testsys.membus.snoop_fanout::mean 0.787786 # Request fanout histogram
+testsys.membus.snoop_fanout::stdev 0.408876 # Request fanout histogram
+testsys.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+testsys.membus.snoop_fanout::0 6100637 21.22% 21.22% # Request fanout histogram
+testsys.membus.snoop_fanout::1 22646887 78.78% 100.00% # Request fanout histogram
+testsys.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+testsys.membus.snoop_fanout::min_value 0 # Request fanout histogram
+testsys.membus.snoop_fanout::max_value 1 # Request fanout histogram
+testsys.membus.snoop_fanout::total 28747524 # Request fanout histogram
testsys.tsunami.ethernet.clk_domain.clock 2000 # Clock period in ticks
-testsys.tsunami.ethernet.descDMAReads 4849 # Number of descriptors the device read w/ DMA
-testsys.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
-testsys.tsunami.ethernet.descDmaReadBytes 116376 # number of descriptor bytes read w/ DMA
-testsys.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
+testsys.tsunami.ethernet.txBytes 960 # Bytes Transmitted
+testsys.tsunami.ethernet.rxBytes 798 # Bytes Received
+testsys.tsunami.ethernet.txPackets 8 # Number of Packets Transmitted
+testsys.tsunami.ethernet.rxPackets 5 # Number of Packets Received
+testsys.tsunami.ethernet.txIpChecksums 2 # Number of tx IP Checksums done by device
+testsys.tsunami.ethernet.rxIpChecksums 5 # Number of rx IP Checksums done by device
+testsys.tsunami.ethernet.txTcpChecksums 2 # Number of tx TCP Checksums done by device
+testsys.tsunami.ethernet.rxTcpChecksums 5 # Number of rx TCP Checksums done by device
+testsys.tsunami.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
+testsys.tsunami.ethernet.rxUdpChecksums 0 # Number of rx UDP Checksums done by device
+testsys.tsunami.ethernet.descDMAReads 2385801 # Number of descriptors the device read w/ DMA
+testsys.tsunami.ethernet.descDMAWrites 13 # Number of descriptors the device wrote w/ DMA
+testsys.tsunami.ethernet.descDmaReadBytes 57259224 # number of descriptor bytes read w/ DMA
+testsys.tsunami.ethernet.descDmaWriteBytes 104 # number of descriptor bytes write w/ DMA
+testsys.tsunami.ethernet.totBandwidth 70176 # Total Bandwidth (bits/s)
+testsys.tsunami.ethernet.totPackets 13 # Total Packets
+testsys.tsunami.ethernet.totBytes 1758 # Total Bytes
+testsys.tsunami.ethernet.totPPS 65 # Total Tranmission Rate (packets/s)
+testsys.tsunami.ethernet.txBandwidth 38322 # Transmit Bandwidth (bits/s)
+testsys.tsunami.ethernet.rxBandwidth 31855 # Receive Bandwidth (bits/s)
+testsys.tsunami.ethernet.txPPS 40 # Packet Tranmission Rate (packets/s)
+testsys.tsunami.ethernet.rxPPS 25 # Packet Reception Rate (packets/s)
testsys.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
testsys.tsunami.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
testsys.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
testsys.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
testsys.tsunami.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
testsys.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
-testsys.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
+testsys.tsunami.ethernet.postedRxDesc 5 # number of RxDesc interrupts posted to CPU
testsys.tsunami.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
-testsys.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
+testsys.tsunami.ethernet.totalRxDesc 5 # total number of RxDesc written to ISR
testsys.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
testsys.tsunami.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
testsys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
-testsys.tsunami.ethernet.postedTxIdle 40 # number of TxIdle interrupts posted to CPU
+testsys.tsunami.ethernet.postedTxIdle 19571 # number of TxIdle interrupts posted to CPU
testsys.tsunami.ethernet.coalescedTxIdle 1 # average number of TxIdle's coalesced into each post
-testsys.tsunami.ethernet.totalTxIdle 4849 # total number of TxIdle written to ISR
+testsys.tsunami.ethernet.totalTxIdle 2385801 # total number of TxIdle written to ISR
testsys.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
testsys.tsunami.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
testsys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
testsys.tsunami.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
testsys.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
testsys.tsunami.ethernet.coalescedTotal 1 # average number of interrupts coalesced into each post
-testsys.tsunami.ethernet.postedInterrupts 4849 # number of posts to CPU
+testsys.tsunami.ethernet.postedInterrupts 2385819 # number of posts to CPU
testsys.tsunami.ethernet.droppedPackets 0 # number of packets dropped
-testsys.iobus.trans_dist::ReadReq 5049 # Transaction distribution
-testsys.iobus.trans_dist::ReadResp 5049 # Transaction distribution
-testsys.iobus.trans_dist::WriteReq 81 # Transaction distribution
-testsys.iobus.trans_dist::WriteResp 81 # Transaction distribution
-testsys.iobus.pkt_count_testsys.bridge.master::testsys.tsunami.cchip.pio 402 # Packet count per connected master and slave (bytes)
-testsys.iobus.pkt_count_testsys.bridge.master::testsys.tsunami.ethernet.pio 160 # Packet count per connected master and slave (bytes)
-testsys.iobus.pkt_count_testsys.bridge.master::total 562 # Packet count per connected master and slave (bytes)
-testsys.iobus.pkt_count_testsys.tsunami.ethernet.dma::testsys.iobridge.slave 9698 # Packet count per connected master and slave (bytes)
-testsys.iobus.pkt_count_testsys.tsunami.ethernet.dma::total 9698 # Packet count per connected master and slave (bytes)
-testsys.iobus.pkt_count::total 10260 # Packet count per connected master and slave (bytes)
-testsys.iobus.pkt_size_testsys.bridge.master::testsys.tsunami.cchip.pio 1608 # Cumulative packet size per connected master and slave (bytes)
-testsys.iobus.pkt_size_testsys.bridge.master::testsys.tsunami.ethernet.pio 320 # Cumulative packet size per connected master and slave (bytes)
-testsys.iobus.pkt_size_testsys.bridge.master::total 1928 # Cumulative packet size per connected master and slave (bytes)
-testsys.iobus.pkt_size_testsys.tsunami.ethernet.dma::testsys.iobridge.slave 116376 # Cumulative packet size per connected master and slave (bytes)
-testsys.iobus.pkt_size_testsys.tsunami.ethernet.dma::total 116376 # Cumulative packet size per connected master and slave (bytes)
-testsys.iobus.pkt_size::total 118304 # Cumulative packet size per connected master and slave (bytes)
+
+---------- End Simulation Statistics ----------
+
+---------- Begin Simulation Statistics ----------
+sim_seconds 0.000407 # Number of seconds simulated
+sim_ticks 407341500 # Number of ticks simulated
+final_tick 4321620817500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 5226750004 # Simulator instruction rate (inst/s)
+host_op_rate 5225740576 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 4062718512 # Simulator tick rate (ticks/s)
+host_mem_usage 533084 # Number of bytes of host memory used
+host_seconds 0.10 # Real time elapsed on the host
+sim_insts 523853183 # Number of instructions simulated
+sim_ops 523853183 # Number of ops (including micro ops) simulated
drivesys.voltage_domain.voltage 1 # Voltage in Volts
drivesys.clk_domain.clock 1000 # Clock period in ticks
drivesys.physmem.bytes_read::cpu.inst 144608 # Number of bytes read from this memory
drivesys.physmem.bw_total::cpu.data 190601743 # Total bandwidth to/from this memory (bytes/s)
drivesys.physmem.bw_total::tsunami.ethernet 285755318 # Total bandwidth to/from this memory (bytes/s)
drivesys.physmem.bw_total::total 831361401 # Total bandwidth to/from this memory (bytes/s)
-drivesys.membus.trans_dist::ReadReq 47907 # Transaction distribution
-drivesys.membus.trans_dist::ReadResp 48111 # Transaction distribution
-drivesys.membus.trans_dist::WriteReq 3689 # Transaction distribution
-drivesys.membus.trans_dist::WriteResp 3689 # Transaction distribution
-drivesys.membus.trans_dist::LoadLockedReq 204 # Transaction distribution
-drivesys.membus.trans_dist::StoreCondReq 204 # Transaction distribution
-drivesys.membus.trans_dist::StoreCondResp 204 # Transaction distribution
-drivesys.membus.pkt_count_drivesys.cpu.icache_port::drivesys.physmem.port 72304 # Packet count per connected master and slave (bytes)
-drivesys.membus.pkt_count_drivesys.cpu.icache_port::total 72304 # Packet count per connected master and slave (bytes)
-drivesys.membus.pkt_count_drivesys.cpu.dcache_port::drivesys.bridge.slave 562 # Packet count per connected master and slave (bytes)
-drivesys.membus.pkt_count_drivesys.cpu.dcache_port::drivesys.physmem.port 21442 # Packet count per connected master and slave (bytes)
-drivesys.membus.pkt_count_drivesys.cpu.dcache_port::total 22004 # Packet count per connected master and slave (bytes)
-drivesys.membus.pkt_count_drivesys.iobridge.master::drivesys.physmem.port 9700 # Packet count per connected master and slave (bytes)
-drivesys.membus.pkt_count_drivesys.iobridge.master::total 9700 # Packet count per connected master and slave (bytes)
-drivesys.membus.pkt_count::total 104008 # Packet count per connected master and slave (bytes)
-drivesys.membus.pkt_size_drivesys.cpu.icache_port::drivesys.physmem.port 144608 # Cumulative packet size per connected master and slave (bytes)
-drivesys.membus.pkt_size_drivesys.cpu.icache_port::total 144608 # Cumulative packet size per connected master and slave (bytes)
-drivesys.membus.pkt_size_drivesys.cpu.dcache_port::drivesys.bridge.slave 1928 # Cumulative packet size per connected master and slave (bytes)
-drivesys.membus.pkt_size_drivesys.cpu.dcache_port::drivesys.physmem.port 77640 # Cumulative packet size per connected master and slave (bytes)
-drivesys.membus.pkt_size_drivesys.cpu.dcache_port::total 79568 # Cumulative packet size per connected master and slave (bytes)
-drivesys.membus.pkt_size_drivesys.iobridge.master::drivesys.physmem.port 116400 # Cumulative packet size per connected master and slave (bytes)
-drivesys.membus.pkt_size_drivesys.iobridge.master::total 116400 # Cumulative packet size per connected master and slave (bytes)
-drivesys.membus.pkt_size::total 340576 # Cumulative packet size per connected master and slave (bytes)
-drivesys.membus.snoops 0 # Total snoops (count)
-drivesys.membus.snoop_fanout::samples 51723 # Request fanout histogram
-drivesys.membus.snoop_fanout::mean 0.792723 # Request fanout histogram
-drivesys.membus.snoop_fanout::stdev 0.405360 # Request fanout histogram
-drivesys.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-drivesys.membus.snoop_fanout::0 10721 20.73% 20.73% # Request fanout histogram
-drivesys.membus.snoop_fanout::1 41002 79.27% 100.00% # Request fanout histogram
-drivesys.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-drivesys.membus.snoop_fanout::min_value 0 # Request fanout histogram
-drivesys.membus.snoop_fanout::max_value 1 # Request fanout histogram
-drivesys.membus.snoop_fanout::total 51723 # Request fanout histogram
-drivesys.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
-drivesys.disk0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
-drivesys.disk0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
-drivesys.disk0.dma_write_full_pages 0 # Number of full page size DMA writes.
-drivesys.disk0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
-drivesys.disk0.dma_write_txs 0 # Number of DMA write transactions.
-drivesys.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
-drivesys.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
-drivesys.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
-drivesys.disk2.dma_write_full_pages 0 # Number of full page size DMA writes.
-drivesys.disk2.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
-drivesys.disk2.dma_write_txs 0 # Number of DMA write transactions.
drivesys.cpu.clk_domain.clock 250 # Clock period in ticks
drivesys.cpu.dtb.fetch_hits 0 # ITB hits
drivesys.cpu.dtb.fetch_misses 0 # ITB misses
drivesys.cpu.kern.mode_ticks::user 0 # number of ticks spent at the given mode
drivesys.cpu.kern.mode_ticks::idle 0 # number of ticks spent at the given mode
drivesys.cpu.kern.swap_context 0 # number of times the context was actually changed
+drivesys.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
+drivesys.disk0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
+drivesys.disk0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
+drivesys.disk0.dma_write_full_pages 0 # Number of full page size DMA writes.
+drivesys.disk0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
+drivesys.disk0.dma_write_txs 0 # Number of DMA write transactions.
+drivesys.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
+drivesys.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
+drivesys.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
+drivesys.disk2.dma_write_full_pages 0 # Number of full page size DMA writes.
+drivesys.disk2.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
+drivesys.disk2.dma_write_txs 0 # Number of DMA write transactions.
+drivesys.iobus.trans_dist::ReadReq 5050 # Transaction distribution
+drivesys.iobus.trans_dist::ReadResp 5050 # Transaction distribution
+drivesys.iobus.trans_dist::WriteReq 81 # Transaction distribution
+drivesys.iobus.trans_dist::WriteResp 81 # Transaction distribution
+drivesys.iobus.pkt_count_drivesys.bridge.master::drivesys.tsunami.cchip.pio 402 # Packet count per connected master and slave (bytes)
+drivesys.iobus.pkt_count_drivesys.bridge.master::drivesys.tsunami.ethernet.pio 160 # Packet count per connected master and slave (bytes)
+drivesys.iobus.pkt_count_drivesys.bridge.master::total 562 # Packet count per connected master and slave (bytes)
+drivesys.iobus.pkt_count_drivesys.tsunami.ethernet.dma::drivesys.iobridge.slave 9700 # Packet count per connected master and slave (bytes)
+drivesys.iobus.pkt_count_drivesys.tsunami.ethernet.dma::total 9700 # Packet count per connected master and slave (bytes)
+drivesys.iobus.pkt_count::total 10262 # Packet count per connected master and slave (bytes)
+drivesys.iobus.pkt_size_drivesys.bridge.master::drivesys.tsunami.cchip.pio 1608 # Cumulative packet size per connected master and slave (bytes)
+drivesys.iobus.pkt_size_drivesys.bridge.master::drivesys.tsunami.ethernet.pio 320 # Cumulative packet size per connected master and slave (bytes)
+drivesys.iobus.pkt_size_drivesys.bridge.master::total 1928 # Cumulative packet size per connected master and slave (bytes)
+drivesys.iobus.pkt_size_drivesys.tsunami.ethernet.dma::drivesys.iobridge.slave 116400 # Cumulative packet size per connected master and slave (bytes)
+drivesys.iobus.pkt_size_drivesys.tsunami.ethernet.dma::total 116400 # Cumulative packet size per connected master and slave (bytes)
+drivesys.iobus.pkt_size::total 118328 # Cumulative packet size per connected master and slave (bytes)
+drivesys.membus.trans_dist::ReadReq 47907 # Transaction distribution
+drivesys.membus.trans_dist::ReadResp 48111 # Transaction distribution
+drivesys.membus.trans_dist::WriteReq 3689 # Transaction distribution
+drivesys.membus.trans_dist::WriteResp 3689 # Transaction distribution
+drivesys.membus.trans_dist::LoadLockedReq 204 # Transaction distribution
+drivesys.membus.trans_dist::StoreCondReq 204 # Transaction distribution
+drivesys.membus.trans_dist::StoreCondResp 204 # Transaction distribution
+drivesys.membus.pkt_count_drivesys.cpu.icache_port::drivesys.physmem.port 72304 # Packet count per connected master and slave (bytes)
+drivesys.membus.pkt_count_drivesys.cpu.icache_port::total 72304 # Packet count per connected master and slave (bytes)
+drivesys.membus.pkt_count_drivesys.cpu.dcache_port::drivesys.bridge.slave 562 # Packet count per connected master and slave (bytes)
+drivesys.membus.pkt_count_drivesys.cpu.dcache_port::drivesys.physmem.port 21442 # Packet count per connected master and slave (bytes)
+drivesys.membus.pkt_count_drivesys.cpu.dcache_port::total 22004 # Packet count per connected master and slave (bytes)
+drivesys.membus.pkt_count_drivesys.iobridge.master::drivesys.physmem.port 9700 # Packet count per connected master and slave (bytes)
+drivesys.membus.pkt_count_drivesys.iobridge.master::total 9700 # Packet count per connected master and slave (bytes)
+drivesys.membus.pkt_count::total 104008 # Packet count per connected master and slave (bytes)
+drivesys.membus.pkt_size_drivesys.cpu.icache_port::drivesys.physmem.port 144608 # Cumulative packet size per connected master and slave (bytes)
+drivesys.membus.pkt_size_drivesys.cpu.icache_port::total 144608 # Cumulative packet size per connected master and slave (bytes)
+drivesys.membus.pkt_size_drivesys.cpu.dcache_port::drivesys.bridge.slave 1928 # Cumulative packet size per connected master and slave (bytes)
+drivesys.membus.pkt_size_drivesys.cpu.dcache_port::drivesys.physmem.port 77640 # Cumulative packet size per connected master and slave (bytes)
+drivesys.membus.pkt_size_drivesys.cpu.dcache_port::total 79568 # Cumulative packet size per connected master and slave (bytes)
+drivesys.membus.pkt_size_drivesys.iobridge.master::drivesys.physmem.port 116400 # Cumulative packet size per connected master and slave (bytes)
+drivesys.membus.pkt_size_drivesys.iobridge.master::total 116400 # Cumulative packet size per connected master and slave (bytes)
+drivesys.membus.pkt_size::total 340576 # Cumulative packet size per connected master and slave (bytes)
+drivesys.membus.snoops 0 # Total snoops (count)
+drivesys.membus.snoop_fanout::samples 51723 # Request fanout histogram
+drivesys.membus.snoop_fanout::mean 0.792723 # Request fanout histogram
+drivesys.membus.snoop_fanout::stdev 0.405360 # Request fanout histogram
+drivesys.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+drivesys.membus.snoop_fanout::0 10721 20.73% 20.73% # Request fanout histogram
+drivesys.membus.snoop_fanout::1 41002 79.27% 100.00% # Request fanout histogram
+drivesys.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+drivesys.membus.snoop_fanout::min_value 0 # Request fanout histogram
+drivesys.membus.snoop_fanout::max_value 1 # Request fanout histogram
+drivesys.membus.snoop_fanout::total 51723 # Request fanout histogram
drivesys.tsunami.ethernet.clk_domain.clock 2000 # Clock period in ticks
drivesys.tsunami.ethernet.descDMAReads 4850 # Number of descriptors the device read w/ DMA
drivesys.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
drivesys.tsunami.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
drivesys.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
drivesys.tsunami.ethernet.coalescedTotal 1 # average number of interrupts coalesced into each post
-drivesys.tsunami.ethernet.postedInterrupts 4850 # number of posts to CPU
-drivesys.tsunami.ethernet.droppedPackets 0 # number of packets dropped
-drivesys.iobus.trans_dist::ReadReq 5050 # Transaction distribution
-drivesys.iobus.trans_dist::ReadResp 5050 # Transaction distribution
-drivesys.iobus.trans_dist::WriteReq 81 # Transaction distribution
-drivesys.iobus.trans_dist::WriteResp 81 # Transaction distribution
-drivesys.iobus.pkt_count_drivesys.bridge.master::drivesys.tsunami.cchip.pio 402 # Packet count per connected master and slave (bytes)
-drivesys.iobus.pkt_count_drivesys.bridge.master::drivesys.tsunami.ethernet.pio 160 # Packet count per connected master and slave (bytes)
-drivesys.iobus.pkt_count_drivesys.bridge.master::total 562 # Packet count per connected master and slave (bytes)
-drivesys.iobus.pkt_count_drivesys.tsunami.ethernet.dma::drivesys.iobridge.slave 9700 # Packet count per connected master and slave (bytes)
-drivesys.iobus.pkt_count_drivesys.tsunami.ethernet.dma::total 9700 # Packet count per connected master and slave (bytes)
-drivesys.iobus.pkt_count::total 10262 # Packet count per connected master and slave (bytes)
-drivesys.iobus.pkt_size_drivesys.bridge.master::drivesys.tsunami.cchip.pio 1608 # Cumulative packet size per connected master and slave (bytes)
-drivesys.iobus.pkt_size_drivesys.bridge.master::drivesys.tsunami.ethernet.pio 320 # Cumulative packet size per connected master and slave (bytes)
-drivesys.iobus.pkt_size_drivesys.bridge.master::total 1928 # Cumulative packet size per connected master and slave (bytes)
-drivesys.iobus.pkt_size_drivesys.tsunami.ethernet.dma::drivesys.iobridge.slave 116400 # Cumulative packet size per connected master and slave (bytes)
-drivesys.iobus.pkt_size_drivesys.tsunami.ethernet.dma::total 116400 # Cumulative packet size per connected master and slave (bytes)
-drivesys.iobus.pkt_size::total 118328 # Cumulative packet size per connected master and slave (bytes)
+drivesys.tsunami.ethernet.postedInterrupts 4850 # number of posts to CPU
+drivesys.tsunami.ethernet.droppedPackets 0 # number of packets dropped
+testsys.voltage_domain.voltage 1 # Voltage in Volts
+testsys.clk_domain.clock 1000 # Clock period in ticks
+testsys.physmem.bytes_read::cpu.inst 144504 # Number of bytes read from this memory
+testsys.physmem.bytes_read::cpu.data 49936 # Number of bytes read from this memory
+testsys.physmem.bytes_read::tsunami.ethernet 116376 # Number of bytes read from this memory
+testsys.physmem.bytes_read::total 310816 # Number of bytes read from this memory
+testsys.physmem.bytes_inst_read::cpu.inst 144504 # Number of instructions bytes read from this memory
+testsys.physmem.bytes_inst_read::total 144504 # Number of instructions bytes read from this memory
+testsys.physmem.bytes_written::cpu.data 27704 # Number of bytes written to this memory
+testsys.physmem.bytes_written::total 27704 # Number of bytes written to this memory
+testsys.physmem.num_reads::cpu.inst 36126 # Number of read requests responded to by this memory
+testsys.physmem.num_reads::cpu.data 6905 # Number of read requests responded to by this memory
+testsys.physmem.num_reads::tsunami.ethernet 4849 # Number of read requests responded to by this memory
+testsys.physmem.num_reads::total 47880 # Number of read requests responded to by this memory
+testsys.physmem.num_writes::cpu.data 3814 # Number of write requests responded to by this memory
+testsys.physmem.num_writes::total 3814 # Number of write requests responded to by this memory
+testsys.physmem.bw_read::cpu.inst 354749025 # Total read bandwidth from this memory (bytes/s)
+testsys.physmem.bw_read::cpu.data 122590014 # Total read bandwidth from this memory (bytes/s)
+testsys.physmem.bw_read::tsunami.ethernet 285696400 # Total read bandwidth from this memory (bytes/s)
+testsys.physmem.bw_read::total 763035438 # Total read bandwidth from this memory (bytes/s)
+testsys.physmem.bw_inst_read::cpu.inst 354749025 # Instruction read bandwidth from this memory (bytes/s)
+testsys.physmem.bw_inst_read::total 354749025 # Instruction read bandwidth from this memory (bytes/s)
+testsys.physmem.bw_write::cpu.data 68011730 # Write bandwidth from this memory (bytes/s)
+testsys.physmem.bw_write::total 68011730 # Write bandwidth from this memory (bytes/s)
+testsys.physmem.bw_total::cpu.inst 354749025 # Total bandwidth to/from this memory (bytes/s)
+testsys.physmem.bw_total::cpu.data 190601743 # Total bandwidth to/from this memory (bytes/s)
+testsys.physmem.bw_total::tsunami.ethernet 285696400 # Total bandwidth to/from this memory (bytes/s)
+testsys.physmem.bw_total::total 831047168 # Total bandwidth to/from this memory (bytes/s)
+testsys.cpu.clk_domain.clock 500 # Clock period in ticks
+testsys.cpu.dtb.fetch_hits 0 # ITB hits
+testsys.cpu.dtb.fetch_misses 0 # ITB misses
+testsys.cpu.dtb.fetch_acv 0 # ITB acv
+testsys.cpu.dtb.fetch_accesses 0 # ITB accesses
+testsys.cpu.dtb.read_hits 7065 # DTB read hits
+testsys.cpu.dtb.read_misses 0 # DTB read misses
+testsys.cpu.dtb.read_acv 0 # DTB read access violations
+testsys.cpu.dtb.read_accesses 0 # DTB read accesses
+testsys.cpu.dtb.write_hits 3935 # DTB write hits
+testsys.cpu.dtb.write_misses 0 # DTB write misses
+testsys.cpu.dtb.write_acv 0 # DTB write access violations
+testsys.cpu.dtb.write_accesses 0 # DTB write accesses
+testsys.cpu.dtb.data_hits 11000 # DTB hits
+testsys.cpu.dtb.data_misses 0 # DTB misses
+testsys.cpu.dtb.data_acv 0 # DTB access violations
+testsys.cpu.dtb.data_accesses 0 # DTB accesses
+testsys.cpu.itb.fetch_hits 5992 # ITB hits
+testsys.cpu.itb.fetch_misses 0 # ITB misses
+testsys.cpu.itb.fetch_acv 0 # ITB acv
+testsys.cpu.itb.fetch_accesses 5992 # ITB accesses
+testsys.cpu.itb.read_hits 0 # DTB read hits
+testsys.cpu.itb.read_misses 0 # DTB read misses
+testsys.cpu.itb.read_acv 0 # DTB read access violations
+testsys.cpu.itb.read_accesses 0 # DTB read accesses
+testsys.cpu.itb.write_hits 0 # DTB write hits
+testsys.cpu.itb.write_misses 0 # DTB write misses
+testsys.cpu.itb.write_acv 0 # DTB write access violations
+testsys.cpu.itb.write_accesses 0 # DTB write accesses
+testsys.cpu.itb.data_hits 0 # DTB hits
+testsys.cpu.itb.data_misses 0 # DTB misses
+testsys.cpu.itb.data_acv 0 # DTB access violations
+testsys.cpu.itb.data_accesses 0 # DTB accesses
+testsys.cpu.numCycles 821056 # number of cpu cycles simulated
+testsys.cpu.numWorkItemsStarted 0 # number of work items this cpu started
+testsys.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
+testsys.cpu.committedInsts 36126 # Number of instructions committed
+testsys.cpu.committedOps 36126 # Number of ops (including micro ops) committed
+testsys.cpu.num_int_alu_accesses 33492 # Number of integer alu accesses
+testsys.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
+testsys.cpu.num_func_calls 2384 # number of times a function call or return occured
+testsys.cpu.num_conditional_control_insts 2346 # number of instructions that are conditional controls
+testsys.cpu.num_int_insts 33492 # number of integer instructions
+testsys.cpu.num_fp_insts 0 # number of float instructions
+testsys.cpu.num_int_register_reads 43747 # number of times the integer registers were read
+testsys.cpu.num_int_register_writes 26476 # number of times the integer registers were written
+testsys.cpu.num_fp_register_reads 0 # number of times the floating registers were read
+testsys.cpu.num_fp_register_writes 0 # number of times the floating registers were written
+testsys.cpu.num_mem_refs 11041 # number of memory refs
+testsys.cpu.num_load_insts 7105 # Number of load instructions
+testsys.cpu.num_store_insts 3936 # Number of store instructions
+testsys.cpu.num_idle_cycles 784687.711054 # Number of idle cycles
+testsys.cpu.num_busy_cycles 36368.288946 # Number of busy cycles
+testsys.cpu.not_idle_fraction 0.044295 # Percentage of non-idle cycles
+testsys.cpu.idle_fraction 0.955705 # Percentage of idle cycles
+testsys.cpu.Branches 5238 # Number of branches fetched
+testsys.cpu.op_class::No_OpClass 1261 3.49% 3.49% # Class of executed instruction
+testsys.cpu.op_class::IntAlu 21664 59.97% 63.46% # Class of executed instruction
+testsys.cpu.op_class::IntMult 44 0.12% 63.58% # Class of executed instruction
+testsys.cpu.op_class::IntDiv 0 0.00% 63.58% # Class of executed instruction
+testsys.cpu.op_class::FloatAdd 0 0.00% 63.58% # Class of executed instruction
+testsys.cpu.op_class::FloatCmp 0 0.00% 63.58% # Class of executed instruction
+testsys.cpu.op_class::FloatCvt 0 0.00% 63.58% # Class of executed instruction
+testsys.cpu.op_class::FloatMult 0 0.00% 63.58% # Class of executed instruction
+testsys.cpu.op_class::FloatDiv 0 0.00% 63.58% # Class of executed instruction
+testsys.cpu.op_class::FloatSqrt 0 0.00% 63.58% # Class of executed instruction
+testsys.cpu.op_class::SimdAdd 0 0.00% 63.58% # Class of executed instruction
+testsys.cpu.op_class::SimdAddAcc 0 0.00% 63.58% # Class of executed instruction
+testsys.cpu.op_class::SimdAlu 0 0.00% 63.58% # Class of executed instruction
+testsys.cpu.op_class::SimdCmp 0 0.00% 63.58% # Class of executed instruction
+testsys.cpu.op_class::SimdCvt 0 0.00% 63.58% # Class of executed instruction
+testsys.cpu.op_class::SimdMisc 0 0.00% 63.58% # Class of executed instruction
+testsys.cpu.op_class::SimdMult 0 0.00% 63.58% # Class of executed instruction
+testsys.cpu.op_class::SimdMultAcc 0 0.00% 63.58% # Class of executed instruction
+testsys.cpu.op_class::SimdShift 0 0.00% 63.58% # Class of executed instruction
+testsys.cpu.op_class::SimdShiftAcc 0 0.00% 63.58% # Class of executed instruction
+testsys.cpu.op_class::SimdSqrt 0 0.00% 63.58% # Class of executed instruction
+testsys.cpu.op_class::SimdFloatAdd 0 0.00% 63.58% # Class of executed instruction
+testsys.cpu.op_class::SimdFloatAlu 0 0.00% 63.58% # Class of executed instruction
+testsys.cpu.op_class::SimdFloatCmp 0 0.00% 63.58% # Class of executed instruction
+testsys.cpu.op_class::SimdFloatCvt 0 0.00% 63.58% # Class of executed instruction
+testsys.cpu.op_class::SimdFloatDiv 0 0.00% 63.58% # Class of executed instruction
+testsys.cpu.op_class::SimdFloatMisc 0 0.00% 63.58% # Class of executed instruction
+testsys.cpu.op_class::SimdFloatMult 0 0.00% 63.58% # Class of executed instruction
+testsys.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.58% # Class of executed instruction
+testsys.cpu.op_class::SimdFloatSqrt 0 0.00% 63.58% # Class of executed instruction
+testsys.cpu.op_class::MemRead 7674 21.24% 84.82% # Class of executed instruction
+testsys.cpu.op_class::MemWrite 3938 10.90% 95.72% # Class of executed instruction
+testsys.cpu.op_class::IprAccess 1545 4.28% 100.00% # Class of executed instruction
+testsys.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
+testsys.cpu.op_class::total 36126 # Class of executed instruction
+testsys.cpu.kern.inst.arm 0 # number of arm instructions executed
+testsys.cpu.kern.inst.quiesce 40 # number of quiesce instructions executed
+testsys.cpu.kern.inst.hwrei 295 # number of hwrei instructions executed
+testsys.cpu.kern.ipl_count::0 123 41.84% 41.84% # number of times we switched to this ipl
+testsys.cpu.kern.ipl_count::21 40 13.61% 55.44% # number of times we switched to this ipl
+testsys.cpu.kern.ipl_count::22 1 0.34% 55.78% # number of times we switched to this ipl
+testsys.cpu.kern.ipl_count::31 130 44.22% 100.00% # number of times we switched to this ipl
+testsys.cpu.kern.ipl_count::total 294 # number of times we switched to this ipl
+testsys.cpu.kern.ipl_good::0 123 42.86% 42.86% # number of times we switched to this ipl from a different ipl
+testsys.cpu.kern.ipl_good::21 40 13.94% 56.79% # number of times we switched to this ipl from a different ipl
+testsys.cpu.kern.ipl_good::22 1 0.35% 57.14% # number of times we switched to this ipl from a different ipl
+testsys.cpu.kern.ipl_good::31 123 42.86% 100.00% # number of times we switched to this ipl from a different ipl
+testsys.cpu.kern.ipl_good::total 287 # number of times we switched to this ipl from a different ipl
+testsys.cpu.kern.ipl_ticks::0 397967000 96.95% 96.95% # number of cycles we spent at this ipl
+testsys.cpu.kern.ipl_ticks::21 3240000 0.79% 97.73% # number of cycles we spent at this ipl
+testsys.cpu.kern.ipl_ticks::22 43000 0.01% 97.74% # number of cycles we spent at this ipl
+testsys.cpu.kern.ipl_ticks::31 9258000 2.26% 100.00% # number of cycles we spent at this ipl
+testsys.cpu.kern.ipl_ticks::total 410508000 # number of cycles we spent at this ipl
+testsys.cpu.kern.ipl_used::0 1 # fraction of swpipl calls that actually changed the ipl
+testsys.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
+testsys.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
+testsys.cpu.kern.ipl_used::31 0.946154 # fraction of swpipl calls that actually changed the ipl
+testsys.cpu.kern.ipl_used::total 0.976190 # fraction of swpipl calls that actually changed the ipl
+testsys.cpu.kern.callpal::swpipl 212 83.46% 83.46% # number of callpals executed
+testsys.cpu.kern.callpal::rdps 1 0.39% 83.86% # number of callpals executed
+testsys.cpu.kern.callpal::rti 41 16.14% 100.00% # number of callpals executed
+testsys.cpu.kern.callpal::total 254 # number of callpals executed
+testsys.cpu.kern.mode_switch::kernel 0 # number of protection mode switches
+testsys.cpu.kern.mode_switch::user 0 # number of protection mode switches
+testsys.cpu.kern.mode_switch::idle 41 # number of protection mode switches
+testsys.cpu.kern.mode_good::kernel 0
+testsys.cpu.kern.mode_good::user 0
+testsys.cpu.kern.mode_good::idle 0
+testsys.cpu.kern.mode_switch_good::kernel nan # fraction of useful protection mode switches
+testsys.cpu.kern.mode_switch_good::user nan # fraction of useful protection mode switches
+testsys.cpu.kern.mode_switch_good::idle 0 # fraction of useful protection mode switches
+testsys.cpu.kern.mode_switch_good::total 0 # fraction of useful protection mode switches
+testsys.cpu.kern.mode_ticks::kernel 0 # number of ticks spent at the given mode
+testsys.cpu.kern.mode_ticks::user 0 # number of ticks spent at the given mode
+testsys.cpu.kern.mode_ticks::idle 0 # number of ticks spent at the given mode
+testsys.cpu.kern.swap_context 0 # number of times the context was actually changed
+testsys.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
+testsys.disk0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
+testsys.disk0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
+testsys.disk0.dma_write_full_pages 0 # Number of full page size DMA writes.
+testsys.disk0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
+testsys.disk0.dma_write_txs 0 # Number of DMA write transactions.
+testsys.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
+testsys.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
+testsys.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
+testsys.disk2.dma_write_full_pages 0 # Number of full page size DMA writes.
+testsys.disk2.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
+testsys.disk2.dma_write_txs 0 # Number of DMA write transactions.
+testsys.iobus.trans_dist::ReadReq 5049 # Transaction distribution
+testsys.iobus.trans_dist::ReadResp 5049 # Transaction distribution
+testsys.iobus.trans_dist::WriteReq 81 # Transaction distribution
+testsys.iobus.trans_dist::WriteResp 81 # Transaction distribution
+testsys.iobus.pkt_count_testsys.bridge.master::testsys.tsunami.cchip.pio 402 # Packet count per connected master and slave (bytes)
+testsys.iobus.pkt_count_testsys.bridge.master::testsys.tsunami.ethernet.pio 160 # Packet count per connected master and slave (bytes)
+testsys.iobus.pkt_count_testsys.bridge.master::total 562 # Packet count per connected master and slave (bytes)
+testsys.iobus.pkt_count_testsys.tsunami.ethernet.dma::testsys.iobridge.slave 9698 # Packet count per connected master and slave (bytes)
+testsys.iobus.pkt_count_testsys.tsunami.ethernet.dma::total 9698 # Packet count per connected master and slave (bytes)
+testsys.iobus.pkt_count::total 10260 # Packet count per connected master and slave (bytes)
+testsys.iobus.pkt_size_testsys.bridge.master::testsys.tsunami.cchip.pio 1608 # Cumulative packet size per connected master and slave (bytes)
+testsys.iobus.pkt_size_testsys.bridge.master::testsys.tsunami.ethernet.pio 320 # Cumulative packet size per connected master and slave (bytes)
+testsys.iobus.pkt_size_testsys.bridge.master::total 1928 # Cumulative packet size per connected master and slave (bytes)
+testsys.iobus.pkt_size_testsys.tsunami.ethernet.dma::testsys.iobridge.slave 116376 # Cumulative packet size per connected master and slave (bytes)
+testsys.iobus.pkt_size_testsys.tsunami.ethernet.dma::total 116376 # Cumulative packet size per connected master and slave (bytes)
+testsys.iobus.pkt_size::total 118304 # Cumulative packet size per connected master and slave (bytes)
+testsys.membus.trans_dist::ReadReq 47876 # Transaction distribution
+testsys.membus.trans_dist::ReadResp 48080 # Transaction distribution
+testsys.membus.trans_dist::WriteReq 3691 # Transaction distribution
+testsys.membus.trans_dist::WriteResp 3691 # Transaction distribution
+testsys.membus.trans_dist::LoadLockedReq 204 # Transaction distribution
+testsys.membus.trans_dist::StoreCondReq 204 # Transaction distribution
+testsys.membus.trans_dist::StoreCondResp 204 # Transaction distribution
+testsys.membus.pkt_count_testsys.cpu.icache_port::testsys.physmem.port 72252 # Packet count per connected master and slave (bytes)
+testsys.membus.pkt_count_testsys.cpu.icache_port::total 72252 # Packet count per connected master and slave (bytes)
+testsys.membus.pkt_count_testsys.cpu.dcache_port::testsys.bridge.slave 562 # Packet count per connected master and slave (bytes)
+testsys.membus.pkt_count_testsys.cpu.dcache_port::testsys.physmem.port 21438 # Packet count per connected master and slave (bytes)
+testsys.membus.pkt_count_testsys.cpu.dcache_port::total 22000 # Packet count per connected master and slave (bytes)
+testsys.membus.pkt_count_testsys.iobridge.master::testsys.physmem.port 9698 # Packet count per connected master and slave (bytes)
+testsys.membus.pkt_count_testsys.iobridge.master::total 9698 # Packet count per connected master and slave (bytes)
+testsys.membus.pkt_count::total 103950 # Packet count per connected master and slave (bytes)
+testsys.membus.pkt_size_testsys.cpu.icache_port::testsys.physmem.port 144504 # Cumulative packet size per connected master and slave (bytes)
+testsys.membus.pkt_size_testsys.cpu.icache_port::total 144504 # Cumulative packet size per connected master and slave (bytes)
+testsys.membus.pkt_size_testsys.cpu.dcache_port::testsys.bridge.slave 1928 # Cumulative packet size per connected master and slave (bytes)
+testsys.membus.pkt_size_testsys.cpu.dcache_port::testsys.physmem.port 77640 # Cumulative packet size per connected master and slave (bytes)
+testsys.membus.pkt_size_testsys.cpu.dcache_port::total 79568 # Cumulative packet size per connected master and slave (bytes)
+testsys.membus.pkt_size_testsys.iobridge.master::testsys.physmem.port 116376 # Cumulative packet size per connected master and slave (bytes)
+testsys.membus.pkt_size_testsys.iobridge.master::total 116376 # Cumulative packet size per connected master and slave (bytes)
+testsys.membus.pkt_size::total 340448 # Cumulative packet size per connected master and slave (bytes)
+testsys.membus.snoops 0 # Total snoops (count)
+testsys.membus.snoop_fanout::samples 51694 # Request fanout histogram
+testsys.membus.snoop_fanout::mean 0.792645 # Request fanout histogram
+testsys.membus.snoop_fanout::stdev 0.405416 # Request fanout histogram
+testsys.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+testsys.membus.snoop_fanout::0 10719 20.74% 20.74% # Request fanout histogram
+testsys.membus.snoop_fanout::1 40975 79.26% 100.00% # Request fanout histogram
+testsys.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+testsys.membus.snoop_fanout::min_value 0 # Request fanout histogram
+testsys.membus.snoop_fanout::max_value 1 # Request fanout histogram
+testsys.membus.snoop_fanout::total 51694 # Request fanout histogram
+testsys.tsunami.ethernet.clk_domain.clock 2000 # Clock period in ticks
+testsys.tsunami.ethernet.descDMAReads 4849 # Number of descriptors the device read w/ DMA
+testsys.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
+testsys.tsunami.ethernet.descDmaReadBytes 116376 # number of descriptor bytes read w/ DMA
+testsys.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
+testsys.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
+testsys.tsunami.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
+testsys.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
+testsys.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
+testsys.tsunami.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
+testsys.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
+testsys.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
+testsys.tsunami.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
+testsys.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
+testsys.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
+testsys.tsunami.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
+testsys.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
+testsys.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
+testsys.tsunami.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
+testsys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
+testsys.tsunami.ethernet.postedTxIdle 40 # number of TxIdle interrupts posted to CPU
+testsys.tsunami.ethernet.coalescedTxIdle 1 # average number of TxIdle's coalesced into each post
+testsys.tsunami.ethernet.totalTxIdle 4849 # total number of TxIdle written to ISR
+testsys.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
+testsys.tsunami.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
+testsys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
+testsys.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
+testsys.tsunami.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
+testsys.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
+testsys.tsunami.ethernet.coalescedTotal 1 # average number of interrupts coalesced into each post
+testsys.tsunami.ethernet.postedInterrupts 4849 # number of posts to CPU
+testsys.tsunami.ethernet.droppedPackets 0 # number of packets dropped
---------- End Simulation Statistics ----------
projects / gem5.git / commitdiff