verilog: fix wildcard port connections leaking memory

diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index 4e601b51d35c7062fd63a87df5c3a84f25cbde59..7d750ea28dea16788e8c3b26a95c398d3bfed2f2 100644 (file)
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -2084,6 +2084,7 @@ cell_port:
                if (!sv_mode)
                        frontend_verilog_yyerror("Wildcard port connections are only supported in SystemVerilog mode.");
                astbuf2->attributes[ID::wildcard_port_conns] = AstNode::mkconst_int(1, false);
+               free_attr($1);
        };
 
 always_comb_or_latch: