read_aiger: consistency between ascii and binary

diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index d6efdaafec38d4a7ec835a34142cc8b2944c74a8..f937ae1f02ee6bec04445e8babf2fe9f27a358a1 100644 (file)
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -496,13 +496,14 @@ void AigerReader::parse_aiger_ascii()
        unsigned l1, l2, l3;
 
        // Parse inputs
+       int digits = ceil(log10(I));
        for (unsigned i = 1; i <= I; ++i, ++line_count) {
                if (!(f >> l1))
                        log_error("Line %u cannot be interpreted as an input!\n", line_count);
                log_debug2("%d is an input\n", l1);
-               log_assert(!(l1 & 1)); // Inputs can't be inverted
-               RTLIL::Wire *wire = createWireIfNotExists(module, l1);
+               RTLIL::Wire *wire = module->addWire(stringf("$i%0*d", digits, l1));
                wire->port_input = true;
+               module->connect(createWireIfNotExists(module, l1 << 1), wire);
                inputs.push_back(wire);
        }
 
@@ -552,25 +553,18 @@ void AigerReader::parse_aiger_ascii()
        }
 
        // Parse outputs
+       digits = ceil(log10(O));
        for (unsigned i = 0; i < O; ++i, ++line_count) {
                if (!(f >> l1))
                        log_error("Line %u cannot be interpreted as an output!\n", line_count);
 
                log_debug2("%d is an output\n", l1);
-               const unsigned variable = l1 >> 1;
-               const bool invert = l1 & 1;
-               RTLIL::IdString wire_name(stringf("$%d%s", variable, invert ? "b" : "")); // FIXME: is "b" the right suffix?
-               RTLIL::Wire *wire = module->wire(wire_name);
-               if (!wire)
-                       wire = createWireIfNotExists(module, l1);
-               else if (wire->port_input || wire->port_output) {
-                       RTLIL::Wire *new_wire = module->addWire(NEW_ID);
-                       module->connect(new_wire, wire);
-                       wire = new_wire;
-               }
+               RTLIL::Wire *wire = module->addWire(stringf("$o%0*d", digits, i));
                wire->port_output = true;
+               module->connect(wire, createWireIfNotExists(module, l1));
                outputs.push_back(wire);
        }
+       std::getline(f, line); // Ignore up to start of next line
 
        // Parse bad properties
        for (unsigned i = 0; i < B; ++i, ++line_count) {