mibuild/xilinx/common: add LatticeDDROutput

diff --git a/mibuild/lattice/common.py b/mibuild/lattice/common.py
index 2eef69d343c57b0a5c1e65fb46d7863572eca985..c087c2aadf6e1ac90831fa98280b01f6ecfef4a5 100644 (file)
--- a/mibuild/lattice/common.py
+++ b/mibuild/lattice/common.py
@@ -1 +1,18 @@
-lattice_special_overrides = {}
+from migen.fhdl.std import *
+from migen.genlib.io import *
+
+class LatticeDifferentialOutput:
+       @staticmethod
+       def lower(dr):
+               return LatticeDifferentialOutputImpl(dr.i, dr.o_p, dr.o_n)
+
+class LatticeDDROutputImpl(Module):
+       def __init__(self, i1, i2, o, clk):
+               self.specials += Instance("ODDRA",
+                               i_CLK=clk, i_RST=0,
+                               i_DA=i1, i_DB=i2, o_Q=o,
+               )
+
+lattice_special_overrides = {
+       DDROutput:      LatticeDDROutput
+}