rl78-real.md (bf): New pattern.

* config/rl78/rl78-real.md (bf): New pattern.
(bt): New pattern.
* config/rl78/rl78.c (rl78_print_operand_1): Handle %B.
(rl78_print_operand): Do not put a # before a %B.
* config/rl78/rl78.opt: Tweak doc strings.

From-SVN: r202676

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 0a50e23c768a77af2b376eb2da3b21c400b53d0e..d2c79a167d99542af426be8e5ac5269be0ef110f 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,11 @@
+2013-09-17  Nick Clifton  <nickc@redhat.com>
+
+       * config/rl78/rl78-real.md (bf): New pattern.
+       (bt): New pattern.
+       * config/rl78/rl78.c (rl78_print_operand_1): Handle %B.
+       (rl78_print_operand): Do not put a # before a %B.
+       * config/rl78/rl78.opt: Tweak doc strings.
+
 2013-09-17  DJ Delorie  <dj@redhat.com>
 
        * config/rl78/constraints.md (Wcv): Allow up to $r31.

diff --git a/gcc/config/rl78/rl78-real.md b/gcc/config/rl78/rl78-real.md
index 409abcc4a2a71310ae0b59989bf0310d60d63558..90b380a54e4e06412bbed9de9cb1bf2ae9f22a13 100644 (file)
--- a/gcc/config/rl78/rl78-real.md
+++ b/gcc/config/rl78/rl78-real.md
@@ -459,3 +459,58 @@
   [(set (match_dup 0) (reg:HI AX_REG))]
   )
 
+;; Bit test and branch insns.
+
+;; NOTE: These patterns will work for bits in other places, not just A.
+
+(define_insn "bf"
+  [(set (pc)
+       (if_then_else (eq (and (reg:QI A_REG)
+                              (match_operand 0 "immediate_operand" "n"))
+                         (const_int 0))
+                     (label_ref (match_operand 1 "" ""))
+                     (pc)))]
+  ""
+  "bf\tA.%B0, $%1"
+)
+
+(define_insn "bt"
+  [(set (pc)
+       (if_then_else (ne (and (reg:QI A_REG)
+                              (match_operand 0 "immediate_operand" "n"))
+                         (const_int 0))
+                     (label_ref (match_operand 1 "" ""))
+                     (pc)))]
+  ""
+  "bt\tA.%B0, $%1"
+)
+
+;; NOTE: These peepholes are fragile.  They rely upon GCC generating
+;; a specific sequence on insns, based upon examination of test code.
+;; Improvements to GCC or using code other than the test code can result
+;; in the peephole not matching and the optimization being missed.
+
+(define_peephole2
+  [(set (match_operand:QI 1 "register_operand") (reg:QI A_REG))
+   (set (match_dup 1) (and:QI (match_dup 1) (match_operand 2 "immediate_operand")))
+   (set (pc) (if_then_else (eq (match_dup 1) (const_int 0))
+                          (label_ref (match_operand 3 ""))
+                          (pc)))]
+  "peep2_regno_dead_p (3, REGNO (operands[1]))
+   && exact_log2 (INTVAL (operands[2])) >= 0"
+  [(set (pc) (if_then_else (eq (and (reg:QI A_REG) (match_dup 2)) (const_int 0))
+                          (label_ref (match_dup 3)) (pc)))]
+  )
+
+(define_peephole2
+  [(set (match_operand:QI 1 "register_operand") (reg:QI A_REG))
+   (set (match_dup 1) (and:QI (match_dup 1) (match_operand 2 "immediate_operand")))
+   (set (pc) (if_then_else (ne (match_dup 1) (const_int 0))
+                          (label_ref (match_operand 3 ""))
+                          (pc)))]
+  "peep2_regno_dead_p (3, REGNO (operands[1]))
+   && exact_log2 (INTVAL (operands[2])) >= 0"
+  [(set (pc) (if_then_else (ne (and (reg:QI A_REG) (match_dup 2)) (const_int 0))
+                          (label_ref (match_dup 3)) (pc)))]
+  )
+

diff --git a/gcc/config/rl78/rl78.c b/gcc/config/rl78/rl78.c
index 41fec465adb41abdf11eb0c7068a9767dae0b69b..5902e1ecd8f282668ef4114253092d74cdb34067 100644 (file)
--- a/gcc/config/rl78/rl78.c
+++ b/gcc/config/rl78/rl78.c
@@ -1286,6 +1286,7 @@ rl78_function_arg_boundary (enum machine_mode mode ATTRIBUTE_UNUSED,
    s - shift count mod 8
    S - shift count mod 16
    r - reverse shift count (8-(count mod 8))
+   B - bit position
 
    h - bottom HI of an SI
    H - top HI of an SI
@@ -1412,6 +1413,8 @@ rl78_print_operand_1 (FILE * file, rtx op, int letter)
        fprintf (file, "%ld", INTVAL (op) & 0xffff);
       else if (letter == 'e')
        fprintf (file, "%ld", (INTVAL (op) >> 16) & 0xff);
+      else if (letter == 'B')
+       fprintf (file, "%d", exact_log2 (INTVAL (op)));
       else if (letter == 'E')
        fprintf (file, "%ld", (INTVAL (op) >> 24) & 0xff);
       else if (letter == 'm')
@@ -1605,7 +1608,7 @@ rl78_print_operand_1 (FILE * file, rtx op, int letter)
 static void
 rl78_print_operand (FILE * file, rtx op, int letter)
 {
-  if (CONSTANT_P (op) && letter != 'u' && letter != 's' && letter != 'r' && letter != 'S')
+  if (CONSTANT_P (op) && letter != 'u' && letter != 's' && letter != 'r' && letter != 'S' && letter != 'B')
     fprintf (file, "#");
   rl78_print_operand_1 (file, op, letter);
 }

diff --git a/gcc/config/rl78/rl78.opt b/gcc/config/rl78/rl78.opt
index 5fc8816f8c32bdc44c4da7a9fa53c2199b10a8f8..ebcf903126d96d830c94e682e0706405bbbfdec2 100644 (file)
--- a/gcc/config/rl78/rl78.opt
+++ b/gcc/config/rl78/rl78.opt
@@ -23,7 +23,7 @@ HeaderInclude
 config/rl78/rl78-opts.h
 
 msim
-Target
+Target Report
 Use the simulator runtime.
 
 mmul=
@@ -43,13 +43,13 @@ EnumValue
 Enum(rl78_mul_types) String(g13) Value(MUL_G13)
 
 mallregs
-Target Mask(ALLREGS)
+Target Mask(ALLREGS) Report Optimization
 Use all registers, reserving none for interrupt handlers.
 
 mrelax
-Target
-Enable assembler and linker relaxation.
+Target Report Optimization
+Enable assembler and linker relaxation.  Enabled by default at -Os.
 
 mg10
-Target Mask(G10)
+Target Mask(G10) Report
 Target the RL78/G10 series