sram: fix WE signal

diff --git a/milkymist/sram/__init__.py b/milkymist/sram/__init__.py
index 756b2c51601fa1f53f8da723d03b1e5ec2889733..792ae1525cb0bc86b8d56e5e8fd2b1bdfb3f5ca2 100644 (file)
--- a/milkymist/sram/__init__.py
+++ b/milkymist/sram/__init__.py
@@ -9,7 +9,7 @@ class SRAM:
        def get_fragment(self):
                # generate write enable signal
                we = Signal(BV(4))
-               comb = [we[i].eq(self.bus.cyc_i & self.bus.stb_i & self.bus.sel_i[3-i])
+               comb = [we[i].eq(self.bus.cyc_i & self.bus.stb_i & self.bus.we_i & self.bus.sel_i[3-i])
                        for i in range(4)]
                # split address
                nbits = bits_for(self.depth-1)