Simple-V is **not RISC-V and is not RISC-V Vectors**.
[NEC SX Aurora](https://sxauroratsubasa.sakura.ne.jp/documents/guide/pdfs/Aurora_ISA_guide.pdf),
-[RVV](https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc), [Simple-V](https://ftp.libre-soc.org/simple_v_spec.pdf) and
+[RVV](https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc),
+[Simple-V](https://ftp.libre-soc.org/simple_v_spec.pdf) and
[MRISC32](https://github.com/mrisc32/mrisc32)
are all based on Cray-style Scalable Vectors
of 30 years ago, hence the similarity,
We invented Simple-V to be simple because we don't like complicated.
-| description, URL |
-|---------------------------------------------------------------------------------------------|
| **Unit tests and simulator for Power ISA v3.0 and SVP64** |
+|---------------------------------------------------------------------------------------------|
| <https://git.libre-soc.org/?p=openpower-isa.git;a=tree;f=src/openpower/decoder/isa;hb=HEAD> |
-| - - - |
+
| **pypowersim tutorial** |
+|---------------------------------------------------------------------------------------------|
| <https://libre-soc.org/docs/pypowersim/> |
-| - - - |
+
| **several thousand more ISA unit tests** |
+|---------------------------------------------------------------------------------------------|
| <https://git.libre-soc.org/?p=openpower-isa.git;a=tree;f=src/openpower/test;hb=HEAD> |
-| - - - |
+
| **demo, showing 4.5x reduction in program size for MP3 decode, greatly simplifies assembler development** |
-| <https://git.libre-soc.org/?p=openpower-isa.git;a=tree;f=media/audio/mp3;hb=HEAD> |
-| - - - |
+|-----------------------------------------------------------------------------------------------------------|
+| <https://git.libre-soc.org/?p=openpower-isa.git;a=tree;f=media/audio/mp3;hb=HEAD> |
+
| **binutils support for SVP64** |
+|---------------------------------------------------------------------------------------------|
| <https://git.libre-soc.org/?p=binutils-gdb.git;a=shortlog;h=refs/heads/svp64-ng> |
+