Fixes for checker. The RC/RS instructions check the interrupt flag, which isn't...

src/arch/alpha/isa/decoder.isa:
src/cpu/checker/cpu.cc:
    Fixes for checker.

--HG--
extra : convert_revision : b0ec8f3c4a10453a567cd6691283fc498403795e

diff --git a/src/arch/alpha/isa/decoder.isa b/src/arch/alpha/isa/decoder.isa
index fab2ca2e10a6020b4b1f7b329135e3840f7b2a1b..dd29e47e4578898849e0b75647ce212e76551742 100644 (file)
--- a/src/arch/alpha/isa/decoder.isa
+++ b/src/arch/alpha/isa/decoder.isa
@@ -659,11 +659,11 @@ decode OPCODE default Unknown::unknown() {
             0xe000: rc({{
                 Ra = xc->readIntrFlag();
                 xc->setIntrFlag(0);
-            }}, IsNonSpeculative);
+            }}, IsNonSpeculative, IsUnverifiable);
             0xf000: rs({{
                 Ra = xc->readIntrFlag();
                 xc->setIntrFlag(1);
-            }}, IsNonSpeculative);
+            }}, IsNonSpeculative, IsUnverifiable);
         }
 #else
         format FailUnimpl {

diff --git a/src/cpu/checker/cpu.cc b/src/cpu/checker/cpu.cc
index ebc02f7beb019d7363283ea78ac607ffab4df462..b1167c1d8fc9fb984b4b33cee1e2c42fcf782ce6 100644 (file)
--- a/src/cpu/checker/cpu.cc
+++ b/src/cpu/checker/cpu.cc
@@ -84,6 +84,8 @@ CheckerCPU::CheckerCPU(Params *p)
 #else
     process = p->process;
 #endif
+
+    result.integer = 0;
 }
 
 CheckerCPU::~CheckerCPU()