update image, mention read/write and regfile porting

diff --git a/3d_gpu/architecture/6600scoreboard.mdwn b/3d_gpu/architecture/6600scoreboard.mdwn
index 48cab33d43f8d330c676cd7d808c6889c217c390..35a2f58f2ef63cc5d60ae5e0aa21a41716301fd9 100644 (file)
--- a/3d_gpu/architecture/6600scoreboard.mdwn
+++ b/3d_gpu/architecture/6600scoreboard.mdwn
@@ -85,7 +85,9 @@ ultimately then, there is:
 # Example allocation of Function Units
 
 This is the key diagram showing the relationship between Function Units
-and the Register File(s).
+and the Register File(s), covering "read".  A similar diagram exists
+for regfile "write".  Observe also that there are *two* Increment
+Function Units.
 
 The Dependency Matrices manage the DAG of read-write relationships:
 each Function Unit indicates which registers it requires for read
@@ -101,6 +103,12 @@ is to "double up" (or triple, or quadruple etc.) the number of Function
 Units, but to *share the same pipeline*.  See "Concurrent Computation Unit"
 section below for details.
 
+In the arrangement below (from the CDC 6600), it can be observed that
+there are actually separate Register Files (A, B and X).  Also observe
+that whilst X goes to *all* Function Units as input, B only goes to
+Branch, Increment and LongAdd, where A goes to Branch and the two Increment
+Function Units.  Thus, A was 3R3W, B was 4R3W, and X was 5R4W.
+
 [[!img multiple_function_units.png size="600x"]]
 
 # Modifications needed to Computation Unit and Group Picker

diff --git a/multiple_function_units.png b/multiple_function_units.png
index d246d08b2cc12b55b877c83597918c0a574e5cd7..bbfdc5eb0bd929b8f0dfd0b3ee200ac6de34ac5b 100644 (file)
Binary files a/multiple_function_units.png and b/multiple_function_units.png differ