pipe_mutex_init(mgr->bo_va_mutex);
mgr->va = rws->info.r600_virtual_address;
- mgr->va_offset = rws->info.r600_va_start;
+ mgr->va_offset = rws->va_start;
list_inithead(&mgr->va_holes);
return &mgr->base;
ws->info.r600_virtual_address = FALSE;
if (ws->info.drm_minor >= 13) {
+ uint32_t ib_vm_max_size;
+
ws->info.r600_virtual_address = TRUE;
if (!radeon_get_drm_value(ws->fd, RADEON_INFO_VA_START, NULL,
- &ws->info.r600_va_start))
+ &ws->va_start))
ws->info.r600_virtual_address = FALSE;
if (!radeon_get_drm_value(ws->fd, RADEON_INFO_IB_VM_MAX_SIZE, NULL,
- &ws->info.r600_ib_vm_max_size))
+ &ib_vm_max_size))
ws->info.r600_virtual_address = FALSE;
}
if (ws->gen == DRV_R600 && !debug_get_bool_option("RADEON_VA", FALSE))
enum radeon_generation gen;
struct radeon_info info;
+ uint32_t va_start;
struct pb_manager *kman;
struct pb_manager *cman;
uint32_t r600_clock_crystal_freq;
uint32_t r600_tiling_config;
uint32_t r600_num_tile_pipes;
- uint32_t r600_backend_map;
- uint32_t r600_va_start;
- uint32_t r600_ib_vm_max_size;
uint32_t r600_max_pipes;
- boolean r600_backend_map_valid;
boolean r600_virtual_address;
boolean r600_has_dma;
+ uint32_t r600_backend_map;
+ boolean r600_backend_map_valid;
+
boolean si_tile_mode_array_valid;
uint32_t si_tile_mode_array[32];