radv: binding streamout buffers doesn't change context regs

Cc: 18.3 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index ee5373950f68ad788328e2d5ae527071474598a5..1f22fda7c55d3cee4e4439c3a129b64702b3d06b 100644 (file)
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -3541,8 +3541,13 @@ static bool radv_need_late_scissor_emission(struct radv_cmd_buffer *cmd_buffer,
 
        uint32_t used_states = cmd_buffer->state.pipeline->graphics.needed_dynamic_state | ~RADV_CMD_DIRTY_DYNAMIC_ALL;
 
-       /* Index & Vertex buffer don't change context regs, and pipeline is handled later. */
-       used_states &= ~(RADV_CMD_DIRTY_INDEX_BUFFER | RADV_CMD_DIRTY_VERTEX_BUFFER | RADV_CMD_DIRTY_PIPELINE);
+       /* Index, vertex and streamout buffers don't change context regs, and
+        * pipeline is handled later.
+        */
+       used_states &= ~(RADV_CMD_DIRTY_INDEX_BUFFER |
+                        RADV_CMD_DIRTY_VERTEX_BUFFER |
+                        RADV_CMD_DIRTY_STREAMOUT_BUFFER |
+                        RADV_CMD_DIRTY_PIPELINE);
 
        /* Assume all state changes except  these two can imply context rolls. */
        if (cmd_buffer->state.dirty & used_states)