Generate variable declaration in some missing places

diff --git a/src/openpower/decoder/test/_pyrtl.py b/src/openpower/decoder/test/_pyrtl.py
index a384c3acc9607feeb027936f5ad4a332f97fbd20..07d68a965f11a6ebc2cdc076b250d7960f57dac3 100644 (file)
--- a/src/openpower/decoder/test/_pyrtl.py
+++ b/src/openpower/decoder/test/_pyrtl.py
@@ -405,7 +405,7 @@ class _StatementCompiler(StatementVisitor, _Compiler):
         output_indexes = [state.get_signal(signal) for signal in stmt._lhs_signals()]
         emitter = _PythonEmitter()
         for signal_index in output_indexes:
-            emitter.append(f"next_{signal_index} = slots[{signal_index}].next")
+            emitter.append(f"uint64_t next_{signal_index} = slots[{signal_index}].next")
         compiler = cls(state, emitter)
         compiler(stmt)
         for signal_index in output_indexes:
@@ -471,7 +471,7 @@ class _FragmentCompiler:
 
                     for signal in domain_signals:
                         signal_index = self.state.get_signal(signal)
-                        emitter.append(f"next_{signal_index} = slots[{signal_index}].next;")
+                        emitter.append(f"uint64_t next_{signal_index} = slots[{signal_index}].next;")
 
                     _StatementCompiler(self.state, emitter)(domain_stmts)