m1crg: allow up to 150MHz pixel clock

diff --git a/verilog/m1crg/m1crg.v b/verilog/m1crg/m1crg.v
index bf91d2be919d1c2e4ff9b943752c669883b6734a..8d9bf31ed55370cd8268993afdd22e612469acc3 100644 (file)
--- a/verilog/m1crg/m1crg.v
+++ b/verilog/m1crg/m1crg.v
@@ -267,7 +267,7 @@ assign eth_tx_clk = eth_tx_clk_pad;
 DCM_CLKGEN #(
        .CLKFXDV_DIVIDE(2),
        .CLKFX_DIVIDE(4),
-       .CLKFX_MD_MAX(2.0),
+       .CLKFX_MD_MAX(3.0),
        .CLKFX_MULTIPLY(2),
        .CLKIN_PERIOD(20.0),
        .SPREAD_SPECTRUM("NONE"),