str2file("soc.v", src_verilog)
str2file("soc.ucf", src_ucf)
verilog_sources.append("build/soc.v")
-
+#raise SystemExit
# xst
xst_prj = ""
for s in verilog_sources:
self.tx = Signal(reset=1)
self.rx = Signal()
- self.divisor = int(clk_freq/baud/16); # TODO
+ self.divisor = int(clk_freq/baud/16) # TODO
def get_fragment(self):
enable16 = Signal()
norflash0 = norflash.Inst(25, 12)
frag = norflash0.get_fragment()
-v = verilog.Convert(frag, name="norflash",
+v = verilog.convert(frag, name="norflash",
ios={norflash0.bus.cyc_i, norflash0.bus.stb_i, norflash0.bus.we_i, norflash0.bus.adr_i, norflash0.bus.sel_i, norflash0.bus.dat_i, norflash0.bus.dat_o, norflash0.bus.ack_o})
print(v)
frag = autofragment.from_local()
vns = convtools.Namespace()
- src_verilog = verilog.Convert(frag,
+ src_verilog = verilog.convert(frag,
{clkfx_sys.clkin, reset0.trigger_reset},
name="soc",
clk_signal=clkfx_sys.clkout,