Update CHANGELOG and README

Signed-off-by: David Shah <dave@ds0.me>

diff --git a/CHANGELOG b/CHANGELOG
index 1fc139d498d58d2a7431b2040ae86f8a0583cf05..a49c27b05c76df46a02cc7a44e94c66ea077030a 100644 (file)
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -51,6 +51,8 @@ Yosys 0.9 .. Yosys 0.9-dev
     - "synth_ice40 -dsp" to infer DSP blocks
     - Added latch support to synth_xilinx
     - Added "check -mapped"
+    - Added checking of SystemVerilog always block types (always_comb,
+      always_latch and always_ff)
 
 Yosys 0.8 .. Yosys 0.9
 ----------------------

diff --git a/README.md b/README.md
index db7810cb4f51d9bed1339e9549169a2f3d4ad713..e46971526ab15ec78ae42d066e74cdb4749048a7 100644 (file)
--- a/README.md
+++ b/README.md
@@ -371,6 +371,11 @@ Verilog Attributes and non-standard features
   for example, to specify the clk-to-Q delay of a flip-flop for consideration
   during techmapping.
 
+- The frontend sets attributes ``always_comb``, ``always_latch`` and
+  ``always_ff`` on processes derived from SystemVerilog style always blocks
+  according to the type of the always. These are checked for correctness in
+  ``proc_dlatch``.
+
 - In addition to the ``(* ... *)`` attribute syntax, Yosys supports
   the non-standard ``{* ... *}`` attribute syntax to set default attributes
   for everything that comes after the ``{* ... *}`` statement. (Reset