RISC-V: Support Zicond extension

    This implements the Zicond (conditional integer operations) extension,
    as of version 1.0-rc2.

    The Zicond extension acts as a building block for branchless sequences
    including conditional-arithmetic, conditional-logic and
    conditional-select/move.
    The following instructions constitute Zicond:
      - czero.eqz rd, rs1, rs2  =>  rd = (rs2 == 0) ? 0 : rs1
      - czero.nez rd, rs1, rs2  =>  rd = (rs2 != 0) ? 0 : rs1

    See
      https://github.com/riscv/riscv-zicond/releases/download/v1.0-rc2/riscv-zicond-v1.0-rc2.pdf
    for the proposed specification and usage details.

    bfd/ChangeLog:

            * elfxx-riscv.c (riscv_multi_subset_supports): Recognize
            INSN_CLASS_ZICOND.
            (riscv_multi_subset_supports_ext): Recognize INSN_CLASS_ZICOND.

    gas/ChangeLog:

            * testsuite/gas/riscv/zicond.d: New test.
            * testsuite/gas/riscv/zicond.s: New test.

    include/ChangeLog:

            * opcode/riscv-opc.h (MATCH_CZERO_EQZ): Define.
            (MASK_CZERO_EQZ): Define.
            (MATCH_CZERO_NEZ): Define,
            (MASK_CZERO_NEZ): Define.
            (DECLARE_INSN): Add czero.eqz and czero.nez.
            * opcode/riscv.h (enum riscv_insn_class): Add
            INSN_CLASS_ZICOND.

    opcodes/ChangeLog:

            * riscv-opc.c: Add czero.eqz and czero.nez.

    Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>

diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 7f453246449d47038bfce286e11739ac40466835..1407c55597df12553419a5e3169f0594a682e0b1 100644 (file)
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1222,6 +1222,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
   {"zicbom",           ISA_SPEC_CLASS_DRAFT,           1, 0,  0 },
   {"zicbop",           ISA_SPEC_CLASS_DRAFT,           1, 0,  0 },
   {"zicboz",           ISA_SPEC_CLASS_DRAFT,           1, 0,  0 },
+  {"zicond",           ISA_SPEC_CLASS_DRAFT,           1, 0,  0 },
   {"zicsr",            ISA_SPEC_CLASS_20191213,        2, 0,  0 },
   {"zicsr",            ISA_SPEC_CLASS_20190608,        2, 0,  0 },
   {"zifencei",         ISA_SPEC_CLASS_20191213,        2, 0,  0 },
@@ -2314,6 +2315,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
       return riscv_subset_supports (rps, "zicbop");
     case INSN_CLASS_ZICBOZ:
       return riscv_subset_supports (rps, "zicboz");
+    case INSN_CLASS_ZICOND:
+      return riscv_subset_supports (rps, "zicond");
     case INSN_CLASS_ZICSR:
       return riscv_subset_supports (rps, "zicsr");
     case INSN_CLASS_ZIFENCEI:
@@ -2465,6 +2468,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
       return "zicbop";
     case INSN_CLASS_ZICBOZ:
       return "zicboz";
+    case INSN_CLASS_ZICOND:
+      return "zicond";
     case INSN_CLASS_ZICSR:
       return "zicsr";
     case INSN_CLASS_ZIFENCEI:

diff --git a/gas/testsuite/gas/riscv/zicond.d b/gas/testsuite/gas/riscv/zicond.d
new file mode 100644 (file)
index 0000000..7a79ee6
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zicond.d
@@ -0,0 +1,12 @@
+#as: -march=rv64i_zicond
+#source: zicond.s
+#objdump: -d
+
+.*:[    ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[       ]+0:[   ]+0ec5d533[     ]+czero.eqz[    ]+a0,a1,a2
+[       ]+4:[   ]+0ee6f533[     ]+czero.nez[    ]+a0,a3,a4

diff --git a/gas/testsuite/gas/riscv/zicond.s b/gas/testsuite/gas/riscv/zicond.s
new file mode 100644 (file)
index 0000000..4e5edd5
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zicond.s
@@ -0,0 +1,3 @@
+target:
+       czero.eqz       a0, a1, a2
+       czero.nez       a0, a3, a4

diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 91e56c03191b4e894bf74bf54faf5bb181bce13e..ad91c5a7b086064a1605584b7a01ac7736c5a9f1 100644 (file)
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2113,6 +2113,11 @@
 #define MASK_CBO_INVAL 0xfff07fff
 #define MATCH_CBO_ZERO 0x40200f
 #define MASK_CBO_ZERO 0xfff07fff
+/* Zicond instructions. */
+#define MATCH_CZERO_EQZ 0xe005033
+#define MASK_CZERO_EQZ 0xfe00707f
+#define MATCH_CZERO_NEZ 0xe007033
+#define MASK_CZERO_NEZ 0xfe00707f
 /* Zawrs intructions.  */
 #define MATCH_WRS_NTO 0x00d00073
 #define MASK_WRS_NTO 0xffffffff
@@ -3120,6 +3125,9 @@ DECLARE_INSN(cbo_clean, MATCH_CBO_CLEAN, MASK_CBO_CLEAN);
 DECLARE_INSN(cbo_flush, MATCH_CBO_FLUSH, MASK_CBO_FLUSH);
 DECLARE_INSN(cbo_inval, MATCH_CBO_INVAL, MASK_CBO_INVAL);
 DECLARE_INSN(cbo_zero, MATCH_CBO_ZERO, MASK_CBO_ZERO);
+/* Zicond instructions. */
+DECLARE_INSN(czero_eqz, MATCH_CZERO_EQZ, MASK_CZERO_EQZ)
+DECLARE_INSN(czero_nez, MATCH_CZERO_NEZ, MASK_CZERO_NEZ)
 /* Zawrs instructions.  */
 DECLARE_INSN(wrs_nto, MATCH_WRS_NTO, MASK_WRS_NTO)
 DECLARE_INSN(wrs_sto, MATCH_WRS_STO, MASK_WRS_STO)

diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index 877ec66b957f3c34af8d01aef9e2421c911e191e..4b108e439c474bd2018e4d55fc8b5d99f6e60c5b 100644 (file)
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -375,6 +375,7 @@ enum riscv_insn_class
   INSN_CLASS_Q,
   INSN_CLASS_F_AND_C,
   INSN_CLASS_D_AND_C,
+  INSN_CLASS_ZICOND,
   INSN_CLASS_ZICSR,
   INSN_CLASS_ZIFENCEI,
   INSN_CLASS_ZIHINTPAUSE,

diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 57e7b90e480cefc9473d8b96927cd51dcbbb60fe..2b2dce1a19467adb49586d1963ac02a95f94b2b0 100644 (file)
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -936,6 +936,10 @@ const struct riscv_opcode riscv_opcodes[] =
 {"cbo.inval",  0, INSN_CLASS_ZICBOM, "0(s)", MATCH_CBO_INVAL, MASK_CBO_INVAL, match_opcode, 0 },
 {"cbo.zero",   0, INSN_CLASS_ZICBOZ, "0(s)", MATCH_CBO_ZERO, MASK_CBO_ZERO, match_opcode, 0 },
 
+/* Zicond instructions.  */
+{"czero.eqz",  0, INSN_CLASS_ZICOND, "d,s,t", MATCH_CZERO_EQZ, MASK_CZERO_EQZ, match_opcode, 0 },
+{"czero.nez",  0, INSN_CLASS_ZICOND, "d,s,t", MATCH_CZERO_NEZ, MASK_CZERO_NEZ, match_opcode, 0 },
+
 /* Zawrs instructions.  */
 {"wrs.nto",    0, INSN_CLASS_ZAWRS, "", MATCH_WRS_NTO, MASK_WRS_NTO, match_opcode, 0 },
 {"wrs.sto",    0, INSN_CLASS_ZAWRS, "", MATCH_WRS_STO, MASK_WRS_STO, match_opcode, 0 },