writeBursts++;
// see if we can merge with an existing item in the write
- // queue and keep track of whether we have merged or not, as
- // there is only ever one item to merge with
+ // queue and keep track of whether we have merged or not so we
+ // can stop at that point and also avoid enqueueing a new
+ // request
bool merged = false;
auto w = writeQueue.begin();
// either of the two could be first, if they are the same
// it does not matter which way we go
if ((*w)->addr >= addr) {
+ // the existing one starts after the new one, figure
+ // out where the new one ends with respect to the
+ // existing one
if ((addr + size) >= ((*w)->addr + (*w)->size)) {
// check if the existing one is completely
// subsumed in the new one
(*w)->size = (*w)->addr + (*w)->size - addr;
}
} else {
+ // the new one starts after the current one, figure
+ // out where the existing one ends with respect to the
+ // new one
if (((*w)->addr + (*w)->size) >= (addr + size)) {
// check if the new one is completely subsumed in the
// existing one
---------- Begin Simulation Statistics ----------
-sim_seconds 1.904274 # Number of seconds simulated
-sim_ticks 1904273734500 # Number of ticks simulated
-final_tick 1904273734500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 1.902739 # Number of seconds simulated
+sim_ticks 1902738973500 # Number of ticks simulated
+final_tick 1902738973500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 95291 # Simulator instruction rate (inst/s)
-host_op_rate 95291 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 3200085877 # Simulator tick rate (ticks/s)
-host_mem_usage 314408 # Number of bytes of host memory used
-host_seconds 595.07 # Real time elapsed on the host
-sim_insts 56704659 # Number of instructions simulated
-sim_ops 56704659 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu0.inst 939456 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 24909888 # Number of bytes read from this memory
+host_inst_rate 97410 # Simulator instruction rate (inst/s)
+host_op_rate 97410 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 3267297836 # Simulator tick rate (ticks/s)
+host_mem_usage 312988 # Number of bytes of host memory used
+host_seconds 582.36 # Real time elapsed on the host
+sim_insts 56727331 # Number of instructions simulated
+sim_ops 56727331 # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu0.inst 900544 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 24806400 # Number of bytes read from this memory
system.physmem.bytes_read::tsunami.ide 2650816 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 36288 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 341184 # Number of bytes read from this memory
-system.physmem.bytes_read::total 28877632 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 939456 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 36288 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 975744 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 7866880 # Number of bytes written to this memory
-system.physmem.bytes_written::total 7866880 # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.inst 14679 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 389217 # Number of read requests responded to by this memory
+system.physmem.bytes_read::cpu1.inst 74944 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 436992 # Number of bytes read from this memory
+system.physmem.bytes_read::total 28869696 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 900544 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 74944 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 975488 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 7821440 # Number of bytes written to this memory
+system.physmem.bytes_written::total 7821440 # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.inst 14071 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 387600 # Number of read requests responded to by this memory
system.physmem.num_reads::tsunami.ide 41419 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 567 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 5331 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 451213 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 122920 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 122920 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.inst 493341 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 13081044 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::tsunami.ide 1392035 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 19056 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 179168 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 15164643 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 493341 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 19056 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 512397 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 4131171 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 4131171 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 4131171 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 493341 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 13081044 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::tsunami.ide 1392035 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 19056 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 179168 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 19295814 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 451213 # Total number of read requests seen
-system.physmem.writeReqs 122920 # Total number of write requests seen
-system.physmem.cpureqs 579004 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 28877632 # Total number of bytes read from memory
-system.physmem.bytesWritten 7866880 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 28877632 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 7866880 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 75 # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite 4871 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 28315 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 28267 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 28452 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 27960 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 28079 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 27988 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 28494 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 27838 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 28154 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 28095 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 28334 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 27996 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 28689 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 28482 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 28304 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 27691 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 8030 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 7738 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2 7941 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 7420 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 7615 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5 7448 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6 8007 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 7267 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 7422 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 7442 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 7742 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11 7420 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12 8140 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13 8013 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14 7952 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15 7323 # Track writes on a per bank basis
+system.physmem.num_reads::cpu1.inst 1171 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 6828 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 451089 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 122210 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 122210 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.inst 473288 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 13037206 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::tsunami.ide 1393158 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 39387 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 229665 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 15172704 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 473288 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 39387 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 512676 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 4110622 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 4110622 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 4110622 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 473288 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 13037206 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::tsunami.ide 1393158 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 39387 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 229665 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 19283326 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 451089 # Total number of read requests accepted by DRAM controller
+system.physmem.writeReqs 122210 # Total number of write requests accepted by DRAM controller
+system.physmem.readBursts 451089 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
+system.physmem.writeBursts 122210 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
+system.physmem.bytesRead 28869696 # Total number of bytes read from memory
+system.physmem.bytesWritten 7821440 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 28869696 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 7821440 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 73 # Number of DRAM read bursts serviced by write Q
+system.physmem.neitherReadNorWrite 4926 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 28134 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 28249 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 28671 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 28418 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 27918 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 28169 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 28110 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 27493 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 27636 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 28106 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 28006 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 28071 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 28522 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 28683 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 28473 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 28357 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 7885 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 7743 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 8146 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 7856 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 7349 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 7637 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 7614 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 6924 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 6873 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 7305 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 7296 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 7454 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 7954 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 8175 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 8091 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 7908 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
-system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 1904269209000 # Total gap between requests
+system.physmem.numWrRetry 1 # Number of times wr buffer was full causing retry
+system.physmem.totGap 1902738952500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 451213 # Categorize read packet sizes
+system.physmem.readPktSize::6 451089 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
system.physmem.writePktSize::2 0 # Categorize write packet sizes
system.physmem.writePktSize::3 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
-system.physmem.writePktSize::6 122920 # Categorize write packet sizes
-system.physmem.rdQLenPdf::0 323687 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 64950 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 30594 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 6666 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 3343 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 3044 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 1568 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 1533 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 1488 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 1465 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 1421 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11 1414 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12 1398 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13 2035 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 122210 # Categorize write packet sizes
+system.physmem.rdQLenPdf::0 323917 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 64738 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 30395 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 6616 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 3317 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 3023 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 1574 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 1542 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 1506 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 1471 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10 1443 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11 1440 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12 1410 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13 2046 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 2339 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15 2211 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16 1201 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17 450 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18 213 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19 107 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15 2216 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16 1205 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17 449 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18 234 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19 121 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 8 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21 3 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21 6 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 3741 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 3975 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 5058 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 5341 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 5343 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 5345 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6 5345 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 5345 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8 5344 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9 5344 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10 5344 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11 5344 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12 5344 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13 5344 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14 5344 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 5344 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 5344 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 5344 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 5344 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 5344 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 5344 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 5344 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 5344 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 1604 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 1370 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 287 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 4 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 2 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 40619 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 904.415372 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 224.615874 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 2354.830128 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::64-67 14269 35.13% 35.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-131 6234 15.35% 50.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::192-195 3791 9.33% 59.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-259 2540 6.25% 66.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::320-323 1773 4.36% 70.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-387 1547 3.81% 74.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::448-451 1102 2.71% 76.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-515 849 2.09% 79.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::576-579 692 1.70% 80.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-643 549 1.35% 82.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::704-707 540 1.33% 83.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-771 500 1.23% 84.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::832-835 249 0.61% 85.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-899 230 0.57% 85.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::960-963 188 0.46% 86.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1027 304 0.75% 87.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1088-1091 110 0.27% 87.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1152-1155 108 0.27% 87.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1216-1219 118 0.29% 87.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1280-1283 201 0.49% 88.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1344-1347 187 0.46% 88.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1408-1411 117 0.29% 89.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1472-1475 501 1.23% 90.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1536-1539 643 1.58% 91.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1600-1603 97 0.24% 92.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1664-1667 31 0.08% 92.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1728-1731 28 0.07% 92.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1792-1795 107 0.26% 92.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1856-1859 29 0.07% 92.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1920-1923 9 0.02% 92.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1984-1987 14 0.03% 92.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2048-2051 38 0.09% 92.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2112-2115 26 0.06% 92.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2176-2179 3 0.01% 92.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2240-2243 4 0.01% 92.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2304-2307 21 0.05% 92.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2368-2371 11 0.03% 92.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2432-2435 8 0.02% 92.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2496-2499 2 0.00% 92.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2560-2563 6 0.01% 93.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2624-2627 4 0.01% 93.01% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2688-2691 1 0.00% 93.01% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2752-2755 3 0.01% 93.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2816-2819 5 0.01% 93.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2880-2883 3 0.01% 93.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2944-2947 1 0.00% 93.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3008-3011 1 0.00% 93.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3072-3075 3 0.01% 93.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3136-3139 4 0.01% 93.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3264-3267 1 0.00% 93.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3392-3395 2 0.00% 93.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3456-3459 1 0.00% 93.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3584-3587 1 0.00% 93.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3648-3651 2 0.00% 93.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3776-3779 2 0.00% 93.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3840-3843 2 0.00% 93.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3904-3907 2 0.00% 93.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4032-4035 3 0.01% 93.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4096-4099 3 0.01% 93.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4224-4227 1 0.00% 93.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4288-4291 1 0.00% 93.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4416-4419 2 0.00% 93.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4544-4547 1 0.00% 93.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4608-4611 1 0.00% 93.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4736-4739 1 0.00% 93.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4800-4803 2 0.00% 93.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4864-4867 1 0.00% 93.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4928-4931 1 0.00% 93.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5120-5123 1 0.00% 93.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5184-5187 1 0.00% 93.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5376-5379 2 0.00% 93.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5440-5443 1 0.00% 93.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5632-5635 1 0.00% 93.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5760-5763 1 0.00% 93.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6080-6083 1 0.00% 93.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6144-6147 1 0.00% 93.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6336-6339 1 0.00% 93.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6720-6723 1 0.00% 93.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6848-6851 2 0.00% 93.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7040-7043 1 0.00% 93.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7104-7107 1 0.00% 93.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7168-7171 3 0.01% 93.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7296-7299 2 0.00% 93.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7360-7363 2 0.00% 93.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7424-7427 1 0.00% 93.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7616-7619 2 0.00% 93.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7808-7811 2 0.00% 93.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7936-7939 1 0.00% 93.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8000-8003 3 0.01% 93.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8064-8067 3 0.01% 93.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8128-8131 7 0.02% 93.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8192-8195 2429 5.98% 99.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8384-8387 1 0.00% 99.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8448-8451 1 0.00% 99.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8896-8899 1 0.00% 99.22% # Bytes accessed per row activation
+system.physmem.wrQLenPdf::0 3729 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 3933 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 5016 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 5304 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 5307 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 5307 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6 5312 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 5312 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8 5313 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9 5314 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10 5314 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11 5313 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12 5313 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13 5313 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14 5313 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 5313 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 5313 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 5313 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 5313 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 5313 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 5313 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 5313 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 5313 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 1585 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 1381 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 298 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 10 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 7 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 7 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 2 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 2 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 1 # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples 40469 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 906.491388 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 223.789110 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 2353.116019 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::64-67 14451 35.71% 35.71% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-131 6072 15.00% 50.71% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::192-195 3826 9.45% 60.17% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-259 2468 6.10% 66.27% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::320-323 1670 4.13% 70.39% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-387 1520 3.76% 74.15% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::448-451 1058 2.61% 76.76% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-515 819 2.02% 78.79% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::576-579 687 1.70% 80.48% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-643 564 1.39% 81.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::704-707 556 1.37% 83.25% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-771 509 1.26% 84.51% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::832-835 268 0.66% 85.17% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-899 232 0.57% 85.74% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::960-963 203 0.50% 86.25% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1027 288 0.71% 86.96% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1088-1091 119 0.29% 87.25% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1152-1155 109 0.27% 87.52% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1216-1219 110 0.27% 87.79% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1280-1283 196 0.48% 88.28% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1344-1347 187 0.46% 88.74% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1408-1411 119 0.29% 89.03% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1472-1475 500 1.24% 90.27% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1536-1539 628 1.55% 91.82% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1600-1603 91 0.22% 92.05% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1664-1667 33 0.08% 92.13% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1728-1731 28 0.07% 92.20% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1792-1795 99 0.24% 92.44% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1856-1859 30 0.07% 92.52% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1920-1923 12 0.03% 92.54% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1984-1987 17 0.04% 92.59% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2048-2051 48 0.12% 92.71% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2112-2115 23 0.06% 92.76% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2176-2179 5 0.01% 92.77% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2240-2243 6 0.01% 92.79% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2304-2307 33 0.08% 92.87% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2368-2371 8 0.02% 92.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2432-2435 8 0.02% 92.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2496-2499 3 0.01% 92.92% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2560-2563 6 0.01% 92.93% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2624-2627 8 0.02% 92.95% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2688-2691 3 0.01% 92.96% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2752-2755 2 0.00% 92.96% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2816-2819 7 0.02% 92.98% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2880-2883 5 0.01% 92.99% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2944-2947 2 0.00% 93.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3008-3011 1 0.00% 93.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3072-3075 3 0.01% 93.01% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3136-3139 4 0.01% 93.02% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3200-3203 1 0.00% 93.02% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3264-3267 2 0.00% 93.03% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3328-3331 2 0.00% 93.03% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3392-3395 3 0.01% 93.04% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3456-3459 2 0.00% 93.04% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3520-3523 1 0.00% 93.05% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3584-3587 3 0.01% 93.05% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3648-3651 4 0.01% 93.06% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3776-3779 1 0.00% 93.07% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3840-3843 1 0.00% 93.07% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3904-3907 2 0.00% 93.07% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4032-4035 3 0.01% 93.08% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4096-4099 2 0.00% 93.09% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4224-4227 1 0.00% 93.09% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4288-4291 1 0.00% 93.09% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4352-4355 1 0.00% 93.09% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4416-4419 2 0.00% 93.10% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4544-4547 1 0.00% 93.10% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4608-4611 1 0.00% 93.10% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4736-4739 1 0.00% 93.11% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4800-4803 3 0.01% 93.11% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4864-4867 1 0.00% 93.12% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4928-4931 1 0.00% 93.12% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5184-5187 1 0.00% 93.12% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5376-5379 2 0.00% 93.13% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5440-5443 1 0.00% 93.13% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5632-5635 1 0.00% 93.13% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5760-5763 1 0.00% 93.13% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6080-6083 1 0.00% 93.14% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6144-6147 1 0.00% 93.14% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6336-6339 1 0.00% 93.14% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6720-6723 1 0.00% 93.14% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6848-6851 2 0.00% 93.15% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7040-7043 1 0.00% 93.15% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7104-7107 2 0.00% 93.16% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7168-7171 3 0.01% 93.16% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7296-7299 2 0.00% 93.17% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7360-7363 2 0.00% 93.17% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7424-7427 1 0.00% 93.18% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7616-7619 2 0.00% 93.18% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7808-7811 2 0.00% 93.18% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7936-7939 1 0.00% 93.19% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::8000-8003 3 0.01% 93.19% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::8064-8067 3 0.01% 93.20% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::8128-8131 7 0.02% 93.22% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::8192-8195 2429 6.00% 99.22% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::8576-8579 1 0.00% 99.22% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::9216-9219 1 0.00% 99.23% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::9344-9347 1 0.00% 99.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10432-10435 1 0.00% 99.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13568-13571 1 0.00% 99.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13952-13955 1 0.00% 99.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14528-14531 1 0.00% 99.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14592-14595 1 0.00% 99.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14656-14659 1 0.00% 99.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14912-14915 1 0.00% 99.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14976-14979 1 0.00% 99.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15040-15043 1 0.00% 99.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15104-15107 1 0.00% 99.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15168-15171 1 0.00% 99.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15232-15235 1 0.00% 99.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15296-15299 1 0.00% 99.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15360-15363 14 0.03% 99.29% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15424-15427 1 0.00% 99.29% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15488-15491 1 0.00% 99.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15744-15747 1 0.00% 99.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16192-16195 1 0.00% 99.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16384-16387 248 0.61% 99.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16448-16451 3 0.01% 99.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16512-16515 5 0.01% 99.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16576-16579 7 0.02% 99.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16640-16643 6 0.01% 99.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16704-16707 1 0.00% 99.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16768-16771 2 0.00% 99.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16832-16835 2 0.00% 99.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16960-16963 1 0.00% 99.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::17088-17091 4 0.01% 99.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::17216-17219 2 0.00% 99.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::17344-17347 1 0.00% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::17408-17411 1 0.00% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::17664-17667 1 0.00% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 40619 # Bytes accessed per row activation
-system.physmem.totQLat 6391304750 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 13854944750 # Sum of mem lat for all requests
-system.physmem.totBusLat 2255690000 # Total cycles spent in databus access
-system.physmem.totBankLat 5207950000 # Total cycles spent in bank access
-system.physmem.avgQLat 14167.07 # Average queueing delay per request
-system.physmem.avgBankLat 11544.03 # Average bank access latency per request
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+system.physmem.totQLat 6403559750 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 13868349750 # Sum of mem lat for all requests
+system.physmem.totBusLat 2255080000 # Total cycles spent in databus access
+system.physmem.totBankLat 5209710000 # Total cycles spent in bank access
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+system.physmem.avgBankLat 11551.05 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 30711.10 # Average memory access latency
-system.physmem.avgRdBW 15.16 # Average achieved read bandwidth in MB/s
-system.physmem.avgWrBW 4.13 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 15.16 # Average consumed read bandwidth in MB/s
-system.physmem.avgConsumedWrBW 4.13 # Average consumed write bandwidth in MB/s
+system.physmem.avgMemAccLat 30749.13 # Average memory access latency
+system.physmem.avgRdBW 15.17 # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW 4.11 # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW 15.17 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedWrBW 4.11 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 0.15 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.01 # Average read queue length over time
-system.physmem.avgWrQLen 14.33 # Average write queue length over time
-system.physmem.readRowHits 435283 # Number of row buffer hits during reads
-system.physmem.writeRowHits 98148 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 96.49 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 79.85 # Row buffer hit rate for writes
-system.physmem.avgGap 3316773.66 # Average gap between requests
-system.membus.throughput 19353836 # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq 296513 # Transaction distribution
-system.membus.trans_dist::ReadResp 296436 # Transaction distribution
-system.membus.trans_dist::WriteReq 13046 # Transaction distribution
-system.membus.trans_dist::WriteResp 13046 # Transaction distribution
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+system.physmem.readRowHitRate 96.48 # Row buffer hit rate for reads
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system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124666 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 124666 # Packet count per connected master and slave (bytes)
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system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5308096 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::total 5308096 # Cumulative packet size per connected master and slave (bytes)
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-system.membus.data_through_bus 36818266 # Total data (bytes)
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system.membus.snoop_data_through_bus 36736 # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy 37871498 # Layer occupancy (ticks)
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system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
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system.membus.reqLayer1.utilization 0.1 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 99000 # Layer occupancy (ticks)
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system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
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system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
-system.membus.respLayer2.occupancy 376228744 # Layer occupancy (ticks)
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system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
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-system.l2c.tags.tagsinuse 65254.004539 # Cycle average of tags in use
-system.l2c.tags.total_refs 2578331 # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs 409473 # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs 6.296706 # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle 6889943750 # Cycle when the warmup percentage was hit.
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+system.iocache.ReadReq_avg_miss_latency::total 123259.331429 # average ReadReq miss latency
+system.iocache.WriteReq_avg_miss_latency::tsunami.ide 252550.154313 # average WriteReq miss latency
+system.iocache.WriteReq_avg_miss_latency::total 252550.154313 # average WriteReq miss latency
+system.iocache.demand_avg_miss_latency::tsunami.ide 252007.918015 # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 252007.918015 # average overall miss latency
+system.iocache.overall_avg_miss_latency::tsunami.ide 252007.918015 # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 252007.918015 # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs 275771 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.iocache.blocked::no_mshrs 27017 # number of cycles access was blocked
+system.iocache.blocked::no_mshrs 27285 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs 10.103675 # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs 10.107055 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.demand_mshr_misses::total 41727 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::tsunami.ide 41727 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 41727 # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12472883 # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total 12472883 # number of ReadReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8298854290 # number of WriteReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::total 8298854290 # number of WriteReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::tsunami.ide 8311327173 # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total 8311327173 # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::tsunami.ide 8311327173 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total 8311327173 # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12468883 # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total 12468883 # number of ReadReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8331886522 # number of WriteReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::total 8331886522 # number of WriteReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::tsunami.ide 8344355405 # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total 8344355405 # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::tsunami.ide 8344355405 # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total 8344355405 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 71273.617143 # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 71273.617143 # average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 199722.138285 # average WriteReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::total 199722.138285 # average WriteReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 199183.434539 # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 199183.434539 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 199183.434539 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 199183.434539 # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 71250.760000 # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 71250.760000 # average ReadReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 200517.099586 # average WriteReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::total 200517.099586 # average WriteReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 199974.965969 # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 199974.965969 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 199974.965969 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 199974.965969 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
-system.cpu0.branchPred.lookups 12622908 # Number of BP lookups
-system.cpu0.branchPred.condPredicted 10616030 # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect 342195 # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups 8196943 # Number of BTB lookups
-system.cpu0.branchPred.BTBHits 5349460 # Number of BTB hits
+system.cpu0.branchPred.lookups 12458299 # Number of BP lookups
+system.cpu0.branchPred.condPredicted 10491650 # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect 332886 # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups 8054816 # Number of BTB lookups
+system.cpu0.branchPred.BTBHits 5283733 # Number of BTB hits
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct 65.261647 # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS 815211 # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect 29656 # Number of incorrect RAS predictions.
+system.cpu0.branchPred.BTBHitPct 65.597191 # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS 799392 # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect 28656 # Number of incorrect RAS predictions.
system.cpu0.dtb.fetch_hits 0 # ITB hits
system.cpu0.dtb.fetch_misses 0 # ITB misses
system.cpu0.dtb.fetch_acv 0 # ITB acv
system.cpu0.dtb.fetch_accesses 0 # ITB accesses
-system.cpu0.dtb.read_hits 9003860 # DTB read hits
-system.cpu0.dtb.read_misses 33263 # DTB read misses
-system.cpu0.dtb.read_acv 538 # DTB read access violations
-system.cpu0.dtb.read_accesses 672573 # DTB read accesses
-system.cpu0.dtb.write_hits 5893133 # DTB write hits
-system.cpu0.dtb.write_misses 8284 # DTB write misses
-system.cpu0.dtb.write_acv 368 # DTB write access violations
-system.cpu0.dtb.write_accesses 235576 # DTB write accesses
-system.cpu0.dtb.data_hits 14896993 # DTB hits
-system.cpu0.dtb.data_misses 41547 # DTB misses
-system.cpu0.dtb.data_acv 906 # DTB access violations
-system.cpu0.dtb.data_accesses 908149 # DTB accesses
-system.cpu0.itb.fetch_hits 1042149 # ITB hits
-system.cpu0.itb.fetch_misses 31540 # ITB misses
-system.cpu0.itb.fetch_acv 1064 # ITB acv
-system.cpu0.itb.fetch_accesses 1073689 # ITB accesses
+system.cpu0.dtb.read_hits 8872852 # DTB read hits
+system.cpu0.dtb.read_misses 32010 # DTB read misses
+system.cpu0.dtb.read_acv 540 # DTB read access violations
+system.cpu0.dtb.read_accesses 628428 # DTB read accesses
+system.cpu0.dtb.write_hits 5797852 # DTB write hits
+system.cpu0.dtb.write_misses 8130 # DTB write misses
+system.cpu0.dtb.write_acv 348 # DTB write access violations
+system.cpu0.dtb.write_accesses 210128 # DTB write accesses
+system.cpu0.dtb.data_hits 14670704 # DTB hits
+system.cpu0.dtb.data_misses 40140 # DTB misses
+system.cpu0.dtb.data_acv 888 # DTB access violations
+system.cpu0.dtb.data_accesses 838556 # DTB accesses
+system.cpu0.itb.fetch_hits 994919 # ITB hits
+system.cpu0.itb.fetch_misses 28800 # ITB misses
+system.cpu0.itb.fetch_acv 922 # ITB acv
+system.cpu0.itb.fetch_accesses 1023719 # ITB accesses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.read_acv 0 # DTB read access violations
system.cpu0.itb.data_misses 0 # DTB misses
system.cpu0.itb.data_acv 0 # DTB access violations
system.cpu0.itb.data_accesses 0 # DTB accesses
-system.cpu0.numCycles 115698572 # number of cpu cycles simulated
+system.cpu0.numCycles 114636003 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.fetch.icacheStallCycles 25430461 # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts 64765722 # Number of instructions fetch has processed
-system.cpu0.fetch.Branches 12622908 # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches 6164671 # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles 12173111 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles 1754282 # Number of cycles fetch has spent squashing
-system.cpu0.fetch.BlockedCycles 37681561 # Number of cycles fetch has spent blocked
-system.cpu0.fetch.MiscStallCycles 33129 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingTrapStallCycles 206182 # Number of stall cycles due to pending traps
-system.cpu0.fetch.PendingQuiesceStallCycles 360791 # Number of stall cycles due to pending quiesce instructions
-system.cpu0.fetch.IcacheWaitRetryStallCycles 463 # Number of stall cycles due to full MSHR
-system.cpu0.fetch.CacheLines 7843120 # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes 229143 # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.rateDist::samples 77014869 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean 0.840951 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev 2.178782 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.icacheStallCycles 25048083 # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts 63888139 # Number of instructions fetch has processed
+system.cpu0.fetch.Branches 12458299 # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches 6083125 # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles 12009946 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles 1716539 # Number of cycles fetch has spent squashing
+system.cpu0.fetch.BlockedCycles 37364333 # Number of cycles fetch has spent blocked
+system.cpu0.fetch.MiscStallCycles 31995 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu0.fetch.PendingTrapStallCycles 196940 # Number of stall cycles due to pending traps
+system.cpu0.fetch.PendingQuiesceStallCycles 358937 # Number of stall cycles due to pending quiesce instructions
+system.cpu0.fetch.IcacheWaitRetryStallCycles 467 # Number of stall cycles due to full MSHR
+system.cpu0.fetch.CacheLines 7724257 # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes 222992 # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.rateDist::samples 76114982 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean 0.839364 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev 2.177033 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0 64841758 84.19% 84.19% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1 778083 1.01% 85.20% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2 1579221 2.05% 87.25% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3 722075 0.94% 88.19% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::4 2615191 3.40% 91.59% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::5 535253 0.69% 92.28% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::6 589170 0.77% 93.05% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::7 842021 1.09% 94.14% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::8 4512097 5.86% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0 64105036 84.22% 84.22% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1 766655 1.01% 85.23% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2 1565630 2.06% 87.29% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3 705022 0.93% 88.21% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::4 2586372 3.40% 91.61% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::5 523946 0.69% 92.30% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::6 578047 0.76% 93.06% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::7 832534 1.09% 94.15% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::8 4451740 5.85% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total 77014869 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate 0.109102 # Number of branch fetches per cycle
-system.cpu0.fetch.rate 0.559780 # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles 26714732 # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles 37197398 # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles 11068686 # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles 941364 # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles 1092688 # Number of cycles decode is squashing
-system.cpu0.decode.BranchResolved 522796 # Number of times decode resolved a branch
-system.cpu0.decode.BranchMispred 36882 # Number of times decode detected a branch misprediction
-system.cpu0.decode.DecodedInsts 63559406 # Number of instructions handled by decode
-system.cpu0.decode.SquashedInsts 110759 # Number of squashed instructions handled by decode
-system.cpu0.rename.SquashCycles 1092688 # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles 27743135 # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles 15107351 # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles 18539290 # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles 10375436 # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles 4156967 # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts 60135459 # Number of instructions processed by rename
-system.cpu0.rename.ROBFullEvents 7108 # Number of times rename has blocked due to ROB full
-system.cpu0.rename.IQFullEvents 639244 # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LSQFullEvents 1468640 # Number of times rename has blocked due to LSQ full
-system.cpu0.rename.RenamedOperands 40265671 # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups 73230382 # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups 72843642 # Number of integer rename lookups
-system.cpu0.rename.fp_rename_lookups 386740 # Number of floating rename lookups
-system.cpu0.rename.CommittedMaps 35289688 # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps 4975975 # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts 1473731 # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts 214800 # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts 11344202 # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads 9431276 # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores 6179329 # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads 1162337 # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores 768163 # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded 53333771 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded 1831002 # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued 52106137 # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued 101747 # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined 6058761 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined 3179609 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved 1240264 # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples 77014869 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean 0.676572 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev 1.327910 # Number of insts issued each cycle
+system.cpu0.fetch.rateDist::total 76114982 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate 0.108677 # Number of branch fetches per cycle
+system.cpu0.fetch.rate 0.557313 # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles 26317520 # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles 36878715 # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles 10917325 # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles 932522 # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles 1068899 # Number of cycles decode is squashing
+system.cpu0.decode.BranchResolved 511897 # Number of times decode resolved a branch
+system.cpu0.decode.BranchMispred 35733 # Number of times decode detected a branch misprediction
+system.cpu0.decode.DecodedInsts 62704701 # Number of instructions handled by decode
+system.cpu0.decode.SquashedInsts 106993 # Number of squashed instructions handled by decode
+system.cpu0.rename.SquashCycles 1068899 # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles 27334042 # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles 15040257 # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles 18326535 # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles 10227103 # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles 4118144 # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts 59323627 # Number of instructions processed by rename
+system.cpu0.rename.ROBFullEvents 7153 # Number of times rename has blocked due to ROB full
+system.cpu0.rename.IQFullEvents 638131 # Number of times rename has blocked due to IQ full
+system.cpu0.rename.LSQFullEvents 1449994 # Number of times rename has blocked due to LSQ full
+system.cpu0.rename.RenamedOperands 39722637 # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups 72231674 # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups 71847381 # Number of integer rename lookups
+system.cpu0.rename.fp_rename_lookups 384293 # Number of floating rename lookups
+system.cpu0.rename.CommittedMaps 34859464 # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps 4863165 # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts 1453792 # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts 211881 # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts 11242711 # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads 9290886 # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores 6078694 # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads 1146384 # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores 744084 # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded 52609114 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded 1811011 # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued 51412755 # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued 100173 # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined 5939256 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined 3114263 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedNonSpecRemoved 1226583 # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.issued_per_cycle::samples 76114982 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean 0.675462 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev 1.326460 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0 53895136 69.98% 69.98% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1 10485242 13.61% 83.59% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2 4754218 6.17% 89.77% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3 3135006 4.07% 93.84% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4 2479570 3.22% 97.06% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5 1230098 1.60% 98.66% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::6 664050 0.86% 99.52% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::7 318021 0.41% 99.93% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::8 53528 0.07% 100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0 53279780 70.00% 70.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1 10372988 13.63% 83.63% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2 4693410 6.17% 89.79% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3 3092664 4.06% 93.86% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4 2443569 3.21% 97.07% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5 1213853 1.59% 98.66% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::6 652140 0.86% 99.52% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::7 314050 0.41% 99.93% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::8 52528 0.07% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total 77014869 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total 76114982 # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu 83201 11.94% 11.94% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult 0 0.00% 11.94% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv 0 0.00% 11.94% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd 0 0.00% 11.94% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp 0 0.00% 11.94% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt 0 0.00% 11.94% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult 0 0.00% 11.94% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv 0 0.00% 11.94% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 11.94% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd 0 0.00% 11.94% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 11.94% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu 0 0.00% 11.94% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp 0 0.00% 11.94% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt 0 0.00% 11.94% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc 0 0.00% 11.94% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult 0 0.00% 11.94% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 11.94% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift 0 0.00% 11.94% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 11.94% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 11.94% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 11.94% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 11.94% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 11.94% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 11.94% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 11.94% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 11.94% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 11.94% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.94% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 11.94% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead 325493 46.71% 58.64% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite 288201 41.36% 100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu 82827 12.15% 12.15% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult 0 0.00% 12.15% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntDiv 0 0.00% 12.15% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatAdd 0 0.00% 12.15% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCmp 0 0.00% 12.15% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCvt 0 0.00% 12.15% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult 0 0.00% 12.15% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv 0 0.00% 12.15% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 12.15% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd 0 0.00% 12.15% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 12.15% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAlu 0 0.00% 12.15% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCmp 0 0.00% 12.15% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCvt 0 0.00% 12.15% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMisc 0 0.00% 12.15% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult 0 0.00% 12.15% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 12.15% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift 0 0.00% 12.15% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 12.15% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 12.15% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 12.15% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 12.15% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 12.15% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 12.15% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 12.15% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 12.15% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 12.15% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.15% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 12.15% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead 318873 46.78% 58.93% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite 279966 41.07% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass 3785 0.01% 0.01% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu 35867732 68.84% 68.84% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult 57468 0.11% 68.95% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.95% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatAdd 15763 0.03% 68.98% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.98% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.98% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.98% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatDiv 1883 0.00% 68.99% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.99% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.99% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.99% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.99% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.99% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.99% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.99% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.99% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.99% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.99% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.99% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.99% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.99% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.99% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.99% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.99% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.99% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.99% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.99% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.99% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.99% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead 9368607 17.98% 86.97% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite 5962928 11.44% 98.41% # Type of FU issued
-system.cpu0.iq.FU_type_0::IprAccess 827971 1.59% 100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu 35420825 68.90% 68.90% # Type of FU issued
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+system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 69.01% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatAdd 15702 0.03% 69.04% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 69.04% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 69.04% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 69.04% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatDiv 1879 0.00% 69.05% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 69.05% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 69.05% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 69.05% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 69.05% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 69.05% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 69.05% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 69.05% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 69.05% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 69.05% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 69.05% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.05% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 69.05% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 69.05% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.05% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 69.05% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 69.05% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.05% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 69.05% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 69.05% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.05% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.05% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead 9231506 17.96% 87.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite 5866326 11.41% 98.41% # Type of FU issued
+system.cpu0.iq.FU_type_0::IprAccess 816348 1.59% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total 52106137 # Type of FU issued
-system.cpu0.iq.rate 0.450361 # Inst issue rate
-system.cpu0.iq.fu_busy_cnt 696895 # FU busy when requested
-system.cpu0.iq.fu_busy_rate 0.013375 # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads 181470771 # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes 60967498 # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses 51029740 # Number of integer instruction queue wakeup accesses
-system.cpu0.iq.fp_inst_queue_reads 555013 # Number of floating instruction queue reads
-system.cpu0.iq.fp_inst_queue_writes 268874 # Number of floating instruction queue writes
-system.cpu0.iq.fp_inst_queue_wakeup_accesses 261978 # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses 52508945 # Number of integer alu accesses
-system.cpu0.iq.fp_alu_accesses 290302 # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads 547963 # Number of loads that had data forwarded from stores
+system.cpu0.iq.FU_type_0::total 51412755 # Type of FU issued
+system.cpu0.iq.rate 0.448487 # Inst issue rate
+system.cpu0.iq.fu_busy_cnt 681666 # FU busy when requested
+system.cpu0.iq.fu_busy_rate 0.013259 # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads 179170597 # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes 60104783 # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses 50356616 # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.fp_inst_queue_reads 551733 # Number of floating instruction queue reads
+system.cpu0.iq.fp_inst_queue_writes 267128 # Number of floating instruction queue writes
+system.cpu0.iq.fp_inst_queue_wakeup_accesses 260409 # Number of floating instruction queue wakeup accesses
+system.cpu0.iq.int_alu_accesses 51801972 # Number of integer alu accesses
+system.cpu0.iq.fp_alu_accesses 288664 # Number of floating point alu accesses
+system.cpu0.iew.lsq.thread0.forwLoads 541765 # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads 1165767 # Number of loads squashed
-system.cpu0.iew.lsq.thread0.ignoredResponses 4234 # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread0.memOrderViolation 13137 # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores 465736 # Number of stores squashed
+system.cpu0.iew.lsq.thread0.squashedLoads 1139912 # Number of loads squashed
+system.cpu0.iew.lsq.thread0.ignoredResponses 4116 # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread0.memOrderViolation 12815 # Number of memory ordering violations
+system.cpu0.iew.lsq.thread0.squashedStores 456622 # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu0.iew.lsq.thread0.rescheduledLoads 18478 # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked 155290 # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread0.rescheduledLoads 18431 # Number of loads that were rescheduled
+system.cpu0.iew.lsq.thread0.cacheBlocked 154294 # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles 1092688 # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles 10796951 # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles 798319 # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts 58424017 # Number of instructions dispatched to IQ
-system.cpu0.iew.iewDispSquashedInsts 633798 # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts 9431276 # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts 6179329 # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts 1612922 # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents 582630 # Number of times the IQ has become full, causing a stall
-system.cpu0.iew.iewLSQFullEvents 5498 # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.memOrderViolationEvents 13137 # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect 168729 # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect 358890 # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts 527619 # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts 51705429 # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts 9061014 # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts 400707 # Number of squashed instructions skipped in execute
+system.cpu0.iew.iewSquashCycles 1068899 # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles 10746647 # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles 795792 # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts 57645786 # Number of instructions dispatched to IQ
+system.cpu0.iew.iewDispSquashedInsts 623000 # Number of squashed instructions skipped by dispatch
+system.cpu0.iew.iewDispLoadInsts 9290886 # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts 6078694 # Number of dispatched store instructions
+system.cpu0.iew.iewDispNonSpecInsts 1595130 # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewIQFullEvents 581617 # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewLSQFullEvents 5318 # Number of times the LSQ has become full, causing a stall
+system.cpu0.iew.memOrderViolationEvents 12815 # Number of memory order violations
+system.cpu0.iew.predictedTakenIncorrect 164656 # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedNotTakenIncorrect 351489 # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts 516145 # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewExecutedInsts 51022070 # Number of executed instructions
+system.cpu0.iew.iewExecLoadInsts 8928198 # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts 390684 # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp 0 # number of swp insts executed
-system.cpu0.iew.exec_nop 3259244 # number of nop insts executed
-system.cpu0.iew.exec_refs 14976241 # number of memory reference insts executed
-system.cpu0.iew.exec_branches 8231181 # Number of branches executed
-system.cpu0.iew.exec_stores 5915227 # Number of stores executed
-system.cpu0.iew.exec_rate 0.446898 # Inst execution rate
-system.cpu0.iew.wb_sent 51387761 # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count 51291718 # cumulative count of insts written-back
-system.cpu0.iew.wb_producers 25550537 # num instructions producing a value
-system.cpu0.iew.wb_consumers 34415470 # num instructions consuming a value
+system.cpu0.iew.exec_nop 3225661 # number of nop insts executed
+system.cpu0.iew.exec_refs 14747797 # number of memory reference insts executed
+system.cpu0.iew.exec_branches 8123465 # Number of branches executed
+system.cpu0.iew.exec_stores 5819599 # Number of stores executed
+system.cpu0.iew.exec_rate 0.445079 # Inst execution rate
+system.cpu0.iew.wb_sent 50710143 # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count 50617025 # cumulative count of insts written-back
+system.cpu0.iew.wb_producers 25247170 # num instructions producing a value
+system.cpu0.iew.wb_consumers 34011376 # num instructions consuming a value
system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu0.iew.wb_rate 0.443322 # insts written-back per cycle
-system.cpu0.iew.wb_fanout 0.742414 # average fanout of values written-back
+system.cpu0.iew.wb_rate 0.441546 # insts written-back per cycle
+system.cpu0.iew.wb_fanout 0.742315 # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu0.commit.commitSquashedInsts 6546847 # The number of squashed insts skipped by commit
-system.cpu0.commit.commitNonSpecStalls 590738 # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts 492268 # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples 75922181 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean 0.681996 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev 1.596696 # Number of insts commited each cycle
+system.cpu0.commit.commitSquashedInsts 6411331 # The number of squashed insts skipped by commit
+system.cpu0.commit.commitNonSpecStalls 584428 # The number of times commit has been forced to stall to communicate backwards
+system.cpu0.commit.branchMispredicts 481702 # The number of times a branch was mispredicted
+system.cpu0.commit.committed_per_cycle::samples 75046083 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean 0.681415 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev 1.595696 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0 56427011 74.32% 74.32% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1 8133810 10.71% 85.04% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2 4455745 5.87% 90.90% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3 2411043 3.18% 94.08% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4 1335893 1.76% 95.84% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5 570067 0.75% 96.59% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6 478554 0.63% 97.22% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7 445477 0.59% 97.81% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8 1664581 2.19% 100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0 55785925 74.34% 74.34% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1 8029512 10.70% 85.04% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2 4410175 5.88% 90.91% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3 2388789 3.18% 94.09% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4 1317256 1.76% 95.85% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5 560978 0.75% 96.60% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6 472301 0.63% 97.23% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7 435634 0.58% 97.81% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8 1645513 2.19% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total 75922181 # Number of insts commited each cycle
-system.cpu0.commit.committedInsts 51778647 # Number of instructions committed
-system.cpu0.commit.committedOps 51778647 # Number of ops (including micro ops) committed
+system.cpu0.commit.committed_per_cycle::total 75046083 # Number of insts commited each cycle
+system.cpu0.commit.committedInsts 51137491 # Number of instructions committed
+system.cpu0.commit.committedOps 51137491 # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu0.commit.refs 13979102 # Number of memory references committed
-system.cpu0.commit.loads 8265509 # Number of loads committed
-system.cpu0.commit.membars 200777 # Number of memory barriers committed
-system.cpu0.commit.branches 7822311 # Number of branches committed
-system.cpu0.commit.fp_insts 259967 # Number of committed floating point instructions.
-system.cpu0.commit.int_insts 47959803 # Number of committed integer instructions.
-system.cpu0.commit.function_calls 666551 # Number of function calls committed.
-system.cpu0.commit.bw_lim_events 1664581 # number cycles where commit BW limit reached
+system.cpu0.commit.refs 13773046 # Number of memory references committed
+system.cpu0.commit.loads 8150974 # Number of loads committed
+system.cpu0.commit.membars 198820 # Number of memory barriers committed
+system.cpu0.commit.branches 7724848 # Number of branches committed
+system.cpu0.commit.fp_insts 258424 # Number of committed floating point instructions.
+system.cpu0.commit.int_insts 47356368 # Number of committed integer instructions.
+system.cpu0.commit.function_calls 655486 # Number of function calls committed.
+system.cpu0.commit.bw_lim_events 1645513 # number cycles where commit BW limit reached
system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu0.rob.rob_reads 132380203 # The number of ROB reads
-system.cpu0.rob.rob_writes 117743806 # The number of ROB writes
-system.cpu0.timesIdled 1106178 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu0.idleCycles 38683703 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.quiesceCycles 3692842270 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.committedInsts 48811521 # Number of Instructions Simulated
-system.cpu0.committedOps 48811521 # Number of Ops (including micro ops) Simulated
-system.cpu0.committedInsts_total 48811521 # Number of Instructions Simulated
-system.cpu0.cpi 2.370313 # CPI: Cycles Per Instruction
-system.cpu0.cpi_total 2.370313 # CPI: Total CPI of All Threads
-system.cpu0.ipc 0.421885 # IPC: Instructions Per Cycle
-system.cpu0.ipc_total 0.421885 # IPC: Total IPC of All Threads
-system.cpu0.int_regfile_reads 68020458 # number of integer regfile reads
-system.cpu0.int_regfile_writes 37124303 # number of integer regfile writes
-system.cpu0.fp_regfile_reads 128594 # number of floating regfile reads
-system.cpu0.fp_regfile_writes 130201 # number of floating regfile writes
-system.cpu0.misc_regfile_reads 1727987 # number of misc regfile reads
-system.cpu0.misc_regfile_writes 827975 # number of misc regfile writes
+system.cpu0.rob.rob_reads 130752703 # The number of ROB reads
+system.cpu0.rob.rob_writes 116166541 # The number of ROB writes
+system.cpu0.timesIdled 1097555 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu0.idleCycles 38521021 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu0.quiesceCycles 3690835342 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.committedInsts 48197169 # Number of Instructions Simulated
+system.cpu0.committedOps 48197169 # Number of Ops (including micro ops) Simulated
+system.cpu0.committedInsts_total 48197169 # Number of Instructions Simulated
+system.cpu0.cpi 2.378480 # CPI: Cycles Per Instruction
+system.cpu0.cpi_total 2.378480 # CPI: Total CPI of All Threads
+system.cpu0.ipc 0.420437 # IPC: Instructions Per Cycle
+system.cpu0.ipc_total 0.420437 # IPC: Total IPC of All Threads
+system.cpu0.int_regfile_reads 67125195 # number of integer regfile reads
+system.cpu0.int_regfile_writes 36645952 # number of integer regfile writes
+system.cpu0.fp_regfile_reads 127833 # number of floating regfile reads
+system.cpu0.fp_regfile_writes 129422 # number of floating regfile writes
+system.cpu0.misc_regfile_reads 1709874 # number of misc regfile reads
+system.cpu0.misc_regfile_writes 817230 # number of misc regfile writes
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
-system.toL2Bus.throughput 111303171 # Throughput (bytes/s)
-system.toL2Bus.trans_dist::ReadReq 2194950 # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp 2194857 # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq 13046 # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp 13046 # Transaction distribution
-system.toL2Bus.trans_dist::Writeback 821103 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq 9701 # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq 5568 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp 15269 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 343378 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 301828 # Transaction distribution
-system.toL2Bus.trans_dist::BadAddressError 77 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 1783020 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 3388598 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.icache.mem_side 397843 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side 270349 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count 5839810 # Packet count per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 57053376 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 131002064 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side 12730112 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side 9815754 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size 210601306 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.data_through_bus 210591002 # Total data (bytes)
-system.toL2Bus.snoop_data_through_bus 1360704 # Total snoop data (bytes)
-system.toL2Bus.reqLayer0.occupancy 4964254488 # Layer occupancy (ticks)
+system.toL2Bus.throughput 111571177 # Throughput (bytes/s)
+system.toL2Bus.trans_dist::ReadReq 2198759 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 2198668 # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq 13061 # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp 13061 # Transaction distribution
+system.toL2Bus.trans_dist::Writeback 822225 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 10020 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq 5803 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 15823 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 343740 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 302191 # Transaction distribution
+system.toL2Bus.trans_dist::BadAddressError 74 # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1753935 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3363647 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 431103 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 300395 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 5849080 # Packet count per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 56122624 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 129969996 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 13794368 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 11000190 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size::total 210887178 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.data_through_bus 210876874 # Total data (bytes)
+system.toL2Bus.snoop_data_through_bus 1413952 # Total snoop data (bytes)
+system.toL2Bus.reqLayer0.occupancy 4971684979 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy 724500 # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy 4017252621 # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy 3951712593 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy 5927096055 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy 5887546567 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.3 # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy 895637092 # Layer occupancy (ticks)
-system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy 468506529 # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy 970657716 # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.utilization 0.1 # Layer utilization (%)
+system.toL2Bus.respLayer3.occupancy 517795038 # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.throughput 1436442 # Throughput (bytes/s)
-system.iobus.trans_dist::ReadReq 7370 # Transaction distribution
-system.iobus.trans_dist::ReadResp 7370 # Transaction distribution
-system.iobus.trans_dist::WriteReq 54598 # Transaction distribution
-system.iobus.trans_dist::WriteResp 54598 # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 11882 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 476 # Packet count per connected master and slave (bytes)
+system.iobus.throughput 1437659 # Throughput (bytes/s)
+system.iobus.trans_dist::ReadReq 7369 # Transaction distribution
+system.iobus.trans_dist::ReadResp 7369 # Transaction distribution
+system.iobus.trans_dist::WriteReq 54613 # Transaction distribution
+system.iobus.trans_dist::WriteResp 54613 # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 11914 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 40482 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 40510 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83454 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::total 83454 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.tsunami.cchip.pio 11882 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.tsunami.pchip.pio 476 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.tsunami.uart.pio 18148 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.tsunami.backdoor.pio 2468 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.iocache.cpu_side 83454 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 123936 # Packet count per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 47528 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1904 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count::total 123964 # Packet count per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 47656 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::total 73754 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::total 73866 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661624 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661624 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.tsunami.cchip.pio 47528 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.tsunami.pchip.pio 1904 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.tsunami.backdoor.pio 9852 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.iocache.cpu_side 2661624 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::total 2735378 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.data_through_bus 2735378 # Total data (bytes)
-system.iobus.reqLayer0.occupancy 11237000 # Layer occupancy (ticks)
+system.iobus.tot_pkt_size::total 2735490 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.data_through_bus 2735490 # Total data (bytes)
+system.iobus.reqLayer0.occupancy 11269000 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer1.occupancy 356000 # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer29.occupancy 378252917 # Layer occupancy (ticks)
+system.iobus.reqLayer29.occupancy 378285900 # Layer occupancy (ticks)
system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks)
system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer0.occupancy 27436000 # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy 27449000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer1.occupancy 43098256 # Layer occupancy (ticks)
+system.iobus.respLayer1.occupancy 43112505 # Layer occupancy (ticks)
system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.cpu0.icache.tags.replacements 890887 # number of replacements
-system.cpu0.icache.tags.tagsinuse 509.759385 # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs 6905559 # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs 891396 # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs 7.746904 # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle 26019048250 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.759385 # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst 0.995624 # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total 0.995624 # Average percentage of cache occupancy
-system.cpu0.icache.ReadReq_hits::cpu0.inst 6905559 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total 6905559 # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst 6905559 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total 6905559 # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst 6905559 # number of overall hits
-system.cpu0.icache.overall_hits::total 6905559 # number of overall hits
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-system.cpu0.icache.ReadReq_misses::total 937559 # number of ReadReq misses
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+system.cpu0.dcache.demand_hits::total 10108289 # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data 10108289 # number of overall hits
+system.cpu0.dcache.overall_hits::total 10108289 # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data 1585845 # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total 1585845 # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data 1749611 # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total 1749611 # number of WriteReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20563 # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total 20563 # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2808 # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total 2808 # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data 3335456 # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total 3335456 # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data 3335456 # number of overall misses
+system.cpu0.dcache.overall_misses::total 3335456 # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 40055257591 # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total 40055257591 # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 78246234000 # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total 78246234000 # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 299434996 # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total 299434996 # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 20885924 # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total 20885924 # number of StoreCondReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data 118301491591 # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total 118301491591 # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data 118301491591 # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total 118301491591 # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data 8026681 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total 8026681 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data 5417064 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total 5417064 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 183303 # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total 183303 # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 190273 # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total 190273 # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data 13443745 # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total 13443745 # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data 13443745 # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total 13443745 # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.197572 # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total 0.197572 # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.322981 # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total 0.322981 # miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.112180 # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.112180 # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.014758 # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total 0.014758 # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data 0.248105 # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total 0.248105 # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data 0.248105 # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total 0.248105 # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 25257.990277 # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 25257.990277 # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44722.074793 # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 44722.074793 # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14561.834168 # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14561.834168 # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7438.007123 # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7438.007123 # average StoreCondReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 35467.861543 # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 35467.861543 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 35467.861543 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 35467.861543 # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs 2886351 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 1258 # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs 52342 # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs 51822 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 7 # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs 56.327022 # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs 55.697407 # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets 179.714286 # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks 760237 # number of writebacks
-system.cpu0.dcache.writebacks::total 760237 # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 590547 # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total 590547 # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1499620 # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total 1499620 # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 4585 # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total 4585 # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data 2090167 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total 2090167 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data 2090167 # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total 2090167 # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1007374 # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total 1007374 # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 278109 # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total 278109 # number of WriteReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 16087 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total 16087 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2668 # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total 2668 # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data 1285483 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total 1285483 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data 1285483 # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total 1285483 # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 26624787726 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total 26624787726 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 11708735082 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total 11708735082 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 178034254 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 178034254 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 14826085 # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 14826085 # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 38333522808 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total 38333522808 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 38333522808 # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total 38333522808 # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1465041000 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1465041000 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2164117998 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2164117998 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3629158998 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3629158998 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.123622 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.123622 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.050509 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.050509 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.086609 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.086609 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.013859 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.013859 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.094140 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total 0.094140 # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.094140 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total 0.094140 # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26429.893690 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26429.893690 # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 42101.244771 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 42101.244771 # average WriteReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11066.964257 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11066.964257 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5557.003373 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5557.003373 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 29820.326529 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 29820.326529 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 29820.326529 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 29820.326529 # average overall mshr miss latency
+system.cpu0.dcache.writebacks::writebacks 752999 # number of writebacks
+system.cpu0.dcache.writebacks::total 752999 # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 583027 # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total 583027 # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1475561 # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total 1475561 # number of WriteReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 4528 # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total 4528 # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data 2058588 # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total 2058588 # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data 2058588 # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total 2058588 # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1002818 # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total 1002818 # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 274050 # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total 274050 # number of WriteReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 16035 # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total 16035 # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2807 # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total 2807 # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data 1276868 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total 1276868 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data 1276868 # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total 1276868 # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 26563866972 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total 26563866972 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 11468217837 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total 11468217837 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 177500254 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 177500254 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 15271076 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 15271076 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 38032084809 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total 38032084809 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 38032084809 # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total 38032084809 # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1459298500 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1459298500 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2147907499 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2147907499 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3607205999 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3607205999 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.124936 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.124936 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.050590 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.050590 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.087478 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.087478 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.014752 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.014752 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.094979 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total 0.094979 # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.094979 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total 0.094979 # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26489.220349 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26489.220349 # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 41847.173279 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 41847.173279 # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11069.551232 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11069.551232 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5440.354827 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5440.354827 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 29785.447524 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 29785.447524 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 29785.447524 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 29785.447524 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.branchPred.lookups 2340238 # Number of BP lookups
-system.cpu1.branchPred.condPredicted 1946356 # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect 62804 # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups 1358794 # Number of BTB lookups
-system.cpu1.branchPred.BTBHits 776922 # Number of BTB hits
+system.cpu1.branchPred.lookups 2517085 # Number of BP lookups
+system.cpu1.branchPred.condPredicted 2083961 # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect 72869 # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups 1481224 # Number of BTB lookups
+system.cpu1.branchPred.BTBHits 844711 # Number of BTB hits
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct 57.177320 # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS 157214 # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect 6628 # Number of incorrect RAS predictions.
+system.cpu1.branchPred.BTBHitPct 57.027904 # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS 172550 # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect 7415 # Number of incorrect RAS predictions.
system.cpu1.dtb.fetch_hits 0 # ITB hits
system.cpu1.dtb.fetch_misses 0 # ITB misses
system.cpu1.dtb.fetch_acv 0 # ITB acv
system.cpu1.dtb.fetch_accesses 0 # ITB accesses
-system.cpu1.dtb.read_hits 1733483 # DTB read hits
-system.cpu1.dtb.read_misses 9288 # DTB read misses
-system.cpu1.dtb.read_acv 9 # DTB read access violations
-system.cpu1.dtb.read_accesses 276268 # DTB read accesses
-system.cpu1.dtb.write_hits 1103623 # DTB write hits
-system.cpu1.dtb.write_misses 1818 # DTB write misses
-system.cpu1.dtb.write_acv 38 # DTB write access violations
-system.cpu1.dtb.write_accesses 104203 # DTB write accesses
-system.cpu1.dtb.data_hits 2837106 # DTB hits
-system.cpu1.dtb.data_misses 11106 # DTB misses
-system.cpu1.dtb.data_acv 47 # DTB access violations
-system.cpu1.dtb.data_accesses 380471 # DTB accesses
-system.cpu1.itb.fetch_hits 375000 # ITB hits
-system.cpu1.itb.fetch_misses 5508 # ITB misses
-system.cpu1.itb.fetch_acv 148 # ITB acv
-system.cpu1.itb.fetch_accesses 380508 # ITB accesses
+system.cpu1.dtb.read_hits 1869470 # DTB read hits
+system.cpu1.dtb.read_misses 10476 # DTB read misses
+system.cpu1.dtb.read_acv 22 # DTB read access violations
+system.cpu1.dtb.read_accesses 321268 # DTB read accesses
+system.cpu1.dtb.write_hits 1203365 # DTB write hits
+system.cpu1.dtb.write_misses 2061 # DTB write misses
+system.cpu1.dtb.write_acv 64 # DTB write access violations
+system.cpu1.dtb.write_accesses 130567 # DTB write accesses
+system.cpu1.dtb.data_hits 3072835 # DTB hits
+system.cpu1.dtb.data_misses 12537 # DTB misses
+system.cpu1.dtb.data_acv 86 # DTB access violations
+system.cpu1.dtb.data_accesses 451835 # DTB accesses
+system.cpu1.itb.fetch_hits 424254 # ITB hits
+system.cpu1.itb.fetch_misses 6539 # ITB misses
+system.cpu1.itb.fetch_acv 190 # ITB acv
+system.cpu1.itb.fetch_accesses 430793 # ITB accesses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.read_acv 0 # DTB read access violations
system.cpu1.itb.data_misses 0 # DTB misses
system.cpu1.itb.data_acv 0 # DTB access violations
system.cpu1.itb.data_accesses 0 # DTB accesses
-system.cpu1.numCycles 14113255 # number of cpu cycles simulated
+system.cpu1.numCycles 15249987 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.fetch.icacheStallCycles 5353605 # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts 10974333 # Number of instructions fetch has processed
-system.cpu1.fetch.Branches 2340238 # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches 934136 # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles 1960258 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles 346091 # Number of cycles fetch has spent squashing
-system.cpu1.fetch.BlockedCycles 5695969 # Number of cycles fetch has spent blocked
-system.cpu1.fetch.MiscStallCycles 25528 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.PendingTrapStallCycles 53832 # Number of stall cycles due to pending traps
-system.cpu1.fetch.PendingQuiesceStallCycles 54284 # Number of stall cycles due to pending quiesce instructions
-system.cpu1.fetch.IcacheWaitRetryStallCycles 23 # Number of stall cycles due to full MSHR
-system.cpu1.fetch.CacheLines 1309338 # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes 41617 # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.rateDist::samples 13363974 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean 0.821188 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev 2.197770 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.icacheStallCycles 5781097 # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts 11894429 # Number of instructions fetch has processed
+system.cpu1.fetch.Branches 2517085 # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches 1017261 # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles 2131045 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles 385761 # Number of cycles fetch has spent squashing
+system.cpu1.fetch.BlockedCycles 6016414 # Number of cycles fetch has spent blocked
+system.cpu1.fetch.MiscStallCycles 25794 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.PendingTrapStallCycles 62392 # Number of stall cycles due to pending traps
+system.cpu1.fetch.PendingQuiesceStallCycles 56888 # Number of stall cycles due to pending quiesce instructions
+system.cpu1.fetch.IcacheWaitRetryStallCycles 41 # Number of stall cycles due to full MSHR
+system.cpu1.fetch.CacheLines 1433413 # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes 48410 # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.rateDist::samples 14320297 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean 0.830599 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev 2.206016 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0 11403716 85.33% 85.33% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1 124023 0.93% 86.26% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2 213549 1.60% 87.86% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3 153465 1.15% 89.01% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::4 264643 1.98% 90.99% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::5 105166 0.79% 91.77% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::6 115273 0.86% 92.64% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::7 186335 1.39% 94.03% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::8 797804 5.97% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0 12189252 85.12% 85.12% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1 136413 0.95% 86.07% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2 229060 1.60% 87.67% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3 170637 1.19% 88.86% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::4 294592 2.06% 90.92% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::5 114916 0.80% 91.72% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::6 126454 0.88% 92.61% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::7 195471 1.36% 93.97% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::8 863502 6.03% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total 13363974 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate 0.165818 # Number of branch fetches per cycle
-system.cpu1.fetch.rate 0.777590 # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles 5293087 # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles 5922521 # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles 1836128 # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles 97560 # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles 214677 # Number of cycles decode is squashing
-system.cpu1.decode.BranchResolved 97799 # Number of times decode resolved a branch
-system.cpu1.decode.BranchMispred 5876 # Number of times decode detected a branch misprediction
-system.cpu1.decode.DecodedInsts 10774764 # Number of instructions handled by decode
-system.cpu1.decode.SquashedInsts 17225 # Number of squashed instructions handled by decode
-system.cpu1.rename.SquashCycles 214677 # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles 5481600 # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles 352411 # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles 4990949 # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles 1741665 # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles 582670 # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts 9967248 # Number of instructions processed by rename
-system.cpu1.rename.ROBFullEvents 30 # Number of times rename has blocked due to ROB full
-system.cpu1.rename.IQFullEvents 54670 # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LSQFullEvents 132191 # Number of times rename has blocked due to LSQ full
-system.cpu1.rename.RenamedOperands 6553947 # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups 11886744 # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups 11748684 # Number of integer rename lookups
-system.cpu1.rename.fp_rename_lookups 138060 # Number of floating rename lookups
-system.cpu1.rename.CommittedMaps 5636582 # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps 917365 # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts 415822 # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts 37623 # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts 1815514 # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads 1827244 # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores 1170543 # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads 163690 # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores 89610 # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded 8737156 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded 452580 # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued 8518295 # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued 27160 # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined 1245229 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined 620627 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved 325893 # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples 13363974 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean 0.637407 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev 1.312561 # Number of insts issued each cycle
+system.cpu1.fetch.rateDist::total 14320297 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate 0.165055 # Number of branch fetches per cycle
+system.cpu1.fetch.rate 0.779963 # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles 5724387 # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles 6255039 # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles 1992849 # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles 108261 # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles 239760 # Number of cycles decode is squashing
+system.cpu1.decode.BranchResolved 108451 # Number of times decode resolved a branch
+system.cpu1.decode.BranchMispred 6971 # Number of times decode detected a branch misprediction
+system.cpu1.decode.DecodedInsts 11669639 # Number of instructions handled by decode
+system.cpu1.decode.SquashedInsts 20547 # Number of squashed instructions handled by decode
+system.cpu1.rename.SquashCycles 239760 # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles 5925475 # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles 420572 # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles 5212839 # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles 1896462 # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles 625187 # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts 10812976 # Number of instructions processed by rename
+system.cpu1.rename.ROBFullEvents 71 # Number of times rename has blocked due to ROB full
+system.cpu1.rename.IQFullEvents 55937 # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LSQFullEvents 153486 # Number of times rename has blocked due to LSQ full
+system.cpu1.rename.RenamedOperands 7119549 # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups 12930789 # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups 12790175 # Number of integer rename lookups
+system.cpu1.rename.fp_rename_lookups 140614 # Number of floating rename lookups
+system.cpu1.rename.CommittedMaps 6082585 # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps 1036964 # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts 436590 # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts 40484 # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts 1926881 # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads 1976180 # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores 1276143 # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads 178422 # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores 98267 # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded 9491737 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded 473513 # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued 9233560 # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued 29148 # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined 1376057 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined 698810 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved 340347 # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples 14320297 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean 0.644788 # Number of insts issued each cycle
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system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0 9608930 71.90% 71.90% # Number of insts issued each cycle
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-system.cpu1.iq.issued_per_cycle::2 727835 5.45% 90.34% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3 487296 3.65% 93.99% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4 421265 3.15% 97.14% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5 191133 1.43% 98.57% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::6 120060 0.90% 99.47% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::7 63613 0.48% 99.95% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::8 7217 0.05% 100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0 10263877 71.67% 71.67% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1 1860247 12.99% 84.66% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2 792265 5.53% 90.20% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3 533948 3.73% 93.92% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4 454852 3.18% 97.10% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5 207190 1.45% 98.55% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::6 132078 0.92% 99.47% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::7 67607 0.47% 99.94% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::8 8233 0.06% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total 13363974 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total 14320297 # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu 2685 1.53% 1.53% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult 0 0.00% 1.53% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntDiv 0 0.00% 1.53% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.53% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.53% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.53% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMult 0 0.00% 1.53% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.53% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.53% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.53% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.53% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.53% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.53% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.53% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.53% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMult 0 0.00% 1.53% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.53% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShift 0 0.00% 1.53% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.53% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.53% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.53% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.53% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.53% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.53% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.53% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.53% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.53% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.53% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.53% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead 94663 54.03% 55.56% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite 77863 44.44% 100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu 3147 1.66% 1.66% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult 0 0.00% 1.66% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntDiv 0 0.00% 1.66% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.66% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.66% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.66% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatMult 0 0.00% 1.66% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.66% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.66% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.66% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.66% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.66% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.66% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.66% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.66% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMult 0 0.00% 1.66% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.66% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShift 0 0.00% 1.66% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.66% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.66% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.66% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.66% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.66% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.66% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.66% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.66% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.66% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.66% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.66% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead 101977 53.82% 55.48% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite 84363 44.52% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu1.iq.FU_type_0::No_OpClass 3518 0.04% 0.04% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu 5299330 62.21% 62.25% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult 14840 0.17% 62.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd 10732 0.13% 62.55% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.55% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.55% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.55% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv 1759 0.02% 62.57% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.57% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.57% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.57% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.57% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.57% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.57% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.57% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.57% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.57% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.57% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.57% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.57% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.57% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.57% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.57% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.57% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.57% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.57% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.57% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.57% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.57% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead 1812344 21.28% 83.85% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite 1125275 13.21% 97.06% # Type of FU issued
-system.cpu1.iq.FU_type_0::IprAccess 250497 2.94% 100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::No_OpClass 3526 0.04% 0.04% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu 5756733 62.35% 62.38% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult 16005 0.17% 62.56% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.56% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd 10795 0.12% 62.67% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.67% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.67% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.67% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv 1763 0.02% 62.69% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.69% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.69% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.69% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.69% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.69% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.69% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.69% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.69% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.69% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.69% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.69% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.69% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.69% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.69% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.69% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.69% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.69% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.69% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.69% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.69% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.69% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead 1955574 21.18% 83.87% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite 1226577 13.28% 97.16% # Type of FU issued
+system.cpu1.iq.FU_type_0::IprAccess 262587 2.84% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total 8518295 # Type of FU issued
-system.cpu1.iq.rate 0.603567 # Inst issue rate
-system.cpu1.iq.fu_busy_cnt 175211 # FU busy when requested
-system.cpu1.iq.fu_busy_rate 0.020569 # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads 30403276 # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes 10338814 # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses 8274405 # Number of integer instruction queue wakeup accesses
-system.cpu1.iq.fp_inst_queue_reads 199659 # Number of floating instruction queue reads
-system.cpu1.iq.fp_inst_queue_writes 97460 # Number of floating instruction queue writes
-system.cpu1.iq.fp_inst_queue_wakeup_accesses 94461 # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses 8585899 # Number of integer alu accesses
-system.cpu1.iq.fp_alu_accesses 104089 # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads 83773 # Number of loads that had data forwarded from stores
+system.cpu1.iq.FU_type_0::total 9233560 # Type of FU issued
+system.cpu1.iq.rate 0.605480 # Inst issue rate
+system.cpu1.iq.fu_busy_cnt 189487 # FU busy when requested
+system.cpu1.iq.fu_busy_rate 0.020522 # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads 32803401 # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes 11243674 # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses 8968182 # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.fp_inst_queue_reads 202651 # Number of floating instruction queue reads
+system.cpu1.iq.fp_inst_queue_writes 99238 # Number of floating instruction queue writes
+system.cpu1.iq.fp_inst_queue_wakeup_accesses 96146 # Number of floating instruction queue wakeup accesses
+system.cpu1.iq.int_alu_accesses 9314130 # Number of integer alu accesses
+system.cpu1.iq.fp_alu_accesses 105391 # Number of floating point alu accesses
+system.cpu1.iew.lsq.thread0.forwLoads 90243 # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads 247116 # Number of loads squashed
-system.cpu1.iew.lsq.thread0.ignoredResponses 1193 # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation 1397 # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores 111584 # Number of stores squashed
+system.cpu1.iew.lsq.thread0.squashedLoads 277299 # Number of loads squashed
+system.cpu1.iew.lsq.thread0.ignoredResponses 1341 # Number of memory responses ignored because the instruction is squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation 1688 # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores 122180 # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu1.iew.lsq.thread0.rescheduledLoads 268 # Number of loads that were rescheduled
-system.cpu1.iew.lsq.thread0.cacheBlocked 14213 # Number of times an access to memory failed due to the cache being blocked
+system.cpu1.iew.lsq.thread0.rescheduledLoads 318 # Number of loads that were rescheduled
+system.cpu1.iew.lsq.thread0.cacheBlocked 14956 # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles 214677 # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles 210872 # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles 38123 # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts 9643840 # Number of instructions dispatched to IQ
-system.cpu1.iew.iewDispSquashedInsts 131515 # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts 1827244 # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts 1170543 # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts 410565 # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents 32525 # Number of times the IQ has become full, causing a stall
-system.cpu1.iew.iewLSQFullEvents 1557 # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents 1397 # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect 28168 # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect 87904 # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts 116072 # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts 8443529 # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts 1749257 # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts 74766 # Number of squashed instructions skipped in execute
+system.cpu1.iew.iewSquashCycles 239760 # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles 255964 # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles 40163 # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts 10453412 # Number of instructions dispatched to IQ
+system.cpu1.iew.iewDispSquashedInsts 142319 # Number of squashed instructions skipped by dispatch
+system.cpu1.iew.iewDispLoadInsts 1976180 # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts 1276143 # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts 429143 # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents 33341 # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewLSQFullEvents 1750 # Number of times the LSQ has become full, causing a stall
+system.cpu1.iew.memOrderViolationEvents 1688 # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect 32963 # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect 95419 # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts 128382 # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts 9148055 # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts 1886987 # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts 85505 # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp 0 # number of swp insts executed
-system.cpu1.iew.exec_nop 454104 # number of nop insts executed
-system.cpu1.iew.exec_refs 2860324 # number of memory reference insts executed
-system.cpu1.iew.exec_branches 1252098 # Number of branches executed
-system.cpu1.iew.exec_stores 1111067 # Number of stores executed
-system.cpu1.iew.exec_rate 0.598269 # Inst execution rate
-system.cpu1.iew.wb_sent 8394111 # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count 8368866 # cumulative count of insts written-back
-system.cpu1.iew.wb_producers 3943473 # num instructions producing a value
-system.cpu1.iew.wb_consumers 5568899 # num instructions consuming a value
+system.cpu1.iew.exec_nop 488162 # number of nop insts executed
+system.cpu1.iew.exec_refs 3098273 # number of memory reference insts executed
+system.cpu1.iew.exec_branches 1362461 # Number of branches executed
+system.cpu1.iew.exec_stores 1211286 # Number of stores executed
+system.cpu1.iew.exec_rate 0.599873 # Inst execution rate
+system.cpu1.iew.wb_sent 9092483 # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count 9064328 # cumulative count of insts written-back
+system.cpu1.iew.wb_producers 4254481 # num instructions producing a value
+system.cpu1.iew.wb_consumers 5984515 # num instructions consuming a value
system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu1.iew.wb_rate 0.592979 # insts written-back per cycle
-system.cpu1.iew.wb_fanout 0.708124 # average fanout of values written-back
+system.cpu1.iew.wb_rate 0.594383 # insts written-back per cycle
+system.cpu1.iew.wb_fanout 0.710915 # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu1.commit.commitSquashedInsts 1277535 # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls 126687 # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts 110026 # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples 13149297 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean 0.631052 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev 1.572436 # Number of insts commited each cycle
+system.cpu1.commit.commitSquashedInsts 1421128 # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls 133166 # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts 121427 # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples 14080537 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean 0.636506 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev 1.577564 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0 10035587 76.32% 76.32% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1 1461499 11.11% 87.43% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2 536339 4.08% 91.51% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3 329312 2.50% 94.02% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4 237007 1.80% 95.82% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5 91157 0.69% 96.51% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6 98866 0.75% 97.27% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7 97470 0.74% 98.01% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8 262060 1.99% 100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0 10719102 76.13% 76.13% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1 1572221 11.17% 87.29% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2 583613 4.14% 91.44% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3 356342 2.53% 93.97% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4 255998 1.82% 95.79% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5 100117 0.71% 96.50% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6 105425 0.75% 97.25% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7 105001 0.75% 97.99% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8 282718 2.01% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total 13149297 # Number of insts commited each cycle
-system.cpu1.commit.committedInsts 8297892 # Number of instructions committed
-system.cpu1.commit.committedOps 8297892 # Number of ops (including micro ops) committed
+system.cpu1.commit.committed_per_cycle::total 14080537 # Number of insts commited each cycle
+system.cpu1.commit.committedInsts 8962351 # Number of instructions committed
+system.cpu1.commit.committedOps 8962351 # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu1.commit.refs 2639087 # Number of memory references committed
-system.cpu1.commit.loads 1580128 # Number of loads committed
-system.cpu1.commit.membars 40354 # Number of memory barriers committed
-system.cpu1.commit.branches 1179945 # Number of branches committed
-system.cpu1.commit.fp_insts 93281 # Number of committed floating point instructions.
-system.cpu1.commit.int_insts 7680197 # Number of committed integer instructions.
-system.cpu1.commit.function_calls 130349 # Number of function calls committed.
-system.cpu1.commit.bw_lim_events 262060 # number cycles where commit BW limit reached
+system.cpu1.commit.refs 2852844 # Number of memory references committed
+system.cpu1.commit.loads 1698881 # Number of loads committed
+system.cpu1.commit.membars 42409 # Number of memory barriers committed
+system.cpu1.commit.branches 1280511 # Number of branches committed
+system.cpu1.commit.fp_insts 94891 # Number of committed floating point instructions.
+system.cpu1.commit.int_insts 8306060 # Number of committed integer instructions.
+system.cpu1.commit.function_calls 141484 # Number of function calls committed.
+system.cpu1.commit.bw_lim_events 282718 # number cycles where commit BW limit reached
system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu1.rob.rob_reads 22380631 # The number of ROB reads
-system.cpu1.rob.rob_writes 19363835 # The number of ROB writes
-system.cpu1.timesIdled 119058 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles 749281 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.quiesceCycles 3793736462 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts 7893138 # Number of Instructions Simulated
-system.cpu1.committedOps 7893138 # Number of Ops (including micro ops) Simulated
-system.cpu1.committedInsts_total 7893138 # Number of Instructions Simulated
-system.cpu1.cpi 1.788041 # CPI: Cycles Per Instruction
-system.cpu1.cpi_total 1.788041 # CPI: Total CPI of All Threads
-system.cpu1.ipc 0.559271 # IPC: Instructions Per Cycle
-system.cpu1.ipc_total 0.559271 # IPC: Total IPC of All Threads
-system.cpu1.int_regfile_reads 10874027 # number of integer regfile reads
-system.cpu1.int_regfile_writes 5958512 # number of integer regfile writes
-system.cpu1.fp_regfile_reads 51748 # number of floating regfile reads
-system.cpu1.fp_regfile_writes 51512 # number of floating regfile writes
-system.cpu1.misc_regfile_reads 484557 # number of misc regfile reads
-system.cpu1.misc_regfile_writes 198633 # number of misc regfile writes
-system.cpu1.icache.tags.replacements 198364 # number of replacements
-system.cpu1.icache.tags.tagsinuse 470.505741 # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs 1103940 # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs 198874 # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs 5.550952 # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle 1894556454000 # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst 470.505741 # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst 0.918957 # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total 0.918957 # Average percentage of cache occupancy
-system.cpu1.icache.ReadReq_hits::cpu1.inst 1103940 # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total 1103940 # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst 1103940 # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total 1103940 # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst 1103940 # number of overall hits
-system.cpu1.icache.overall_hits::total 1103940 # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst 205398 # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total 205398 # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst 205398 # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total 205398 # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst 205398 # number of overall misses
-system.cpu1.icache.overall_misses::total 205398 # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 2726676790 # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total 2726676790 # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst 2726676790 # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total 2726676790 # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst 2726676790 # number of overall miss cycles
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-system.cpu1.icache.demand_avg_miss_latency::total 13275.089290 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13275.089290 # average overall miss latency
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+system.cpu1.committedOps 8530162 # Number of Ops (including micro ops) Simulated
+system.cpu1.committedInsts_total 8530162 # Number of Instructions Simulated
+system.cpu1.cpi 1.787772 # CPI: Cycles Per Instruction
+system.cpu1.cpi_total 1.787772 # CPI: Total CPI of All Threads
+system.cpu1.ipc 0.559355 # IPC: Instructions Per Cycle
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system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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+system.cpu1.dcache.LoadLockedReq_miss_latency::total 51136995 # number of LoadLockedReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 22092953 # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::total 22092953 # number of StoreCondReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data 10194825400 # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total 10194825400 # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data 10194825400 # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total 10194825400 # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data 1737315 # number of ReadReq accesses(hits+misses)
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+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 32829 # number of StoreCondReq accesses(hits+misses)
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+system.cpu1.dcache.overall_accesses::total 2852558 # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.115227 # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total 0.115227 # miss rate for ReadReq accesses
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system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.142687 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.142687 # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.094920 # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total 0.094920 # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data 0.137966 # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total 0.137966 # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data 0.137966 # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total 0.137966 # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13989.255488 # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 13989.255488 # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 32537.764192 # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 32537.764192 # average WriteReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9733.764251 # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9733.764251 # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7434.509649 # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7434.509649 # average StoreCondReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 23105.812821 # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 23105.812821 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 23105.812821 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 23105.812821 # average overall miss latency
-system.cpu1.dcache.blocked_cycles::no_mshrs 188355 # number of cycles access was blocked
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.091322 # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total 0.091322 # miss rate for StoreCondReq accesses
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+system.cpu1.dcache.overall_miss_rate::total 0.143742 # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14069.734932 # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 14069.734932 # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 35160.362566 # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 35160.362566 # average WriteReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9931.442028 # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9931.442028 # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7369.230487 # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7369.230487 # average StoreCondReq miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 24863.487240 # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 24863.487240 # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 24863.487240 # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 24863.487240 # average overall miss latency
+system.cpu1.dcache.blocked_cycles::no_mshrs 240672 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_mshrs 3483 # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_mshrs 3904 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs 54.078381 # average number of cycles each access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_mshrs 61.647541 # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks 60866 # number of writebacks
-system.cpu1.dcache.writebacks::total 60866 # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 114750 # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total 114750 # number of ReadReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 145883 # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::total 145883 # number of WriteReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 398 # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::total 398 # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits::cpu1.data 260633 # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_hits::total 260633 # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.data 260633 # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total 260633 # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 69975 # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total 69975 # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 32665 # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total 32665 # number of WriteReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4391 # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4391 # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 2900 # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total 2900 # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data 102640 # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total 102640 # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data 102640 # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total 102640 # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 781048941 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total 781048941 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 869596715 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total 869596715 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 32787753 # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 32787753 # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 15774053 # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 15774053 # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 1650645656 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total 1650645656 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 1650645656 # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total 1650645656 # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 18096000 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 18096000 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 600498502 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 600498502 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 618594502 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total 618594502 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.043453 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.043453 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.031939 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.031939 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.130829 # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.130829 # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.094855 # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.094855 # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.038981 # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total 0.038981 # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.038981 # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total 0.038981 # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11161.828382 # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11161.828382 # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26621.665850 # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 26621.665850 # average WriteReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7467.035527 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7467.035527 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5439.328621 # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5439.328621 # average StoreCondReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16081.894544 # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16081.894544 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16081.894544 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16081.894544 # average overall mshr miss latency
+system.cpu1.dcache.writebacks::writebacks 69226 # number of writebacks
+system.cpu1.dcache.writebacks::total 69226 # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 124077 # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total 124077 # number of ReadReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 172447 # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::total 172447 # number of WriteReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 558 # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::total 558 # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.demand_mshr_hits::cpu1.data 296524 # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_hits::total 296524 # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits::cpu1.data 296524 # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_hits::total 296524 # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 76109 # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total 76109 # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 37399 # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total 37399 # number of WriteReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4591 # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4591 # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 2996 # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total 2996 # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data 113508 # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total 113508 # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data 113508 # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total 113508 # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 856275217 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total 856275217 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1088322932 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1088322932 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 34640753 # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 34640753 # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 16100047 # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 16100047 # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 1944598149 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total 1944598149 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 1944598149 # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total 1944598149 # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 23613000 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 23613000 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 620064002 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 620064002 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 643677002 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total 643677002 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.043808 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.043808 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.033534 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.033534 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.127224 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.127224 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.091261 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.091261 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.039792 # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total 0.039792 # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.039792 # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total 0.039792 # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11250.643380 # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11250.643380 # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 29100.321720 # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 29100.321720 # average WriteReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7545.361141 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7545.361141 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5373.847463 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5373.847463 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17131.815810 # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17131.815810 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17131.815810 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17131.815810 # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.quiesce 6628 # number of quiesce instructions executed
-system.cpu0.kern.inst.hwrei 186556 # number of hwrei instructions executed
-system.cpu0.kern.ipl_count::0 65870 40.60% 40.60% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::21 131 0.08% 40.68% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::22 1925 1.19% 41.86% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::30 193 0.12% 41.98% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::31 94141 58.02% 100.00% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::total 162260 # number of times we switched to this ipl
-system.cpu0.kern.ipl_good::0 64876 49.22% 49.22% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::21 131 0.10% 49.32% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::22 1925 1.46% 50.78% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::30 193 0.15% 50.93% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::31 64684 49.07% 100.00% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::total 131809 # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_ticks::0 1863192383000 97.84% 97.84% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::21 64528500 0.00% 97.85% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::22 571927000 0.03% 97.88% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::30 92721000 0.00% 97.88% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::31 40351323000 2.12% 100.00% # number of cycles we spent at this ipl
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-system.cpu0.kern.ipl_used::0 0.984910 # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.inst.quiesce 6603 # number of quiesce instructions executed
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+system.cpu0.kern.ipl_count::0 65080 40.52% 40.52% # number of times we switched to this ipl
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+system.cpu0.kern.ipl_count::30 193 0.12% 41.92% # number of times we switched to this ipl
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+system.cpu0.kern.ipl_good::0 64086 49.21% 49.21% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::21 131 0.10% 49.31% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::22 1924 1.48% 50.79% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::30 193 0.15% 50.94% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::31 63894 49.06% 100.00% # number of times we switched to this ipl from a different ipl
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+system.cpu0.kern.ipl_ticks::0 1861779564000 97.85% 97.85% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::21 63861000 0.00% 97.85% # number of cycles we spent at this ipl
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+system.cpu0.kern.ipl_ticks::31 40230450500 2.11% 100.00% # number of cycles we spent at this ipl
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system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
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-system.cpu0.kern.ipl_used::total 0.812332 # fraction of swpipl calls that actually changed the ipl
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-system.cpu0.kern.syscall::24 3 1.28% 41.03% # number of syscalls executed
-system.cpu0.kern.syscall::33 8 3.42% 44.44% # number of syscalls executed
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-system.cpu0.kern.syscall::47 3 1.28% 63.25% # number of syscalls executed
-system.cpu0.kern.syscall::48 10 4.27% 67.52% # number of syscalls executed
-system.cpu0.kern.syscall::54 10 4.27% 71.79% # number of syscalls executed
-system.cpu0.kern.syscall::58 1 0.43% 72.22% # number of syscalls executed
-system.cpu0.kern.syscall::59 6 2.56% 74.79% # number of syscalls executed
-system.cpu0.kern.syscall::71 27 11.54% 86.32% # number of syscalls executed
-system.cpu0.kern.syscall::73 3 1.28% 87.61% # number of syscalls executed
-system.cpu0.kern.syscall::74 7 2.99% 90.60% # number of syscalls executed
-system.cpu0.kern.syscall::87 1 0.43% 91.03% # number of syscalls executed
-system.cpu0.kern.syscall::90 3 1.28% 92.31% # number of syscalls executed
-system.cpu0.kern.syscall::92 9 3.85% 96.15% # number of syscalls executed
-system.cpu0.kern.syscall::97 2 0.85% 97.01% # number of syscalls executed
-system.cpu0.kern.syscall::98 2 0.85% 97.86% # number of syscalls executed
-system.cpu0.kern.syscall::132 1 0.43% 98.29% # number of syscalls executed
-system.cpu0.kern.syscall::144 2 0.85% 99.15% # number of syscalls executed
-system.cpu0.kern.syscall::147 2 0.85% 100.00% # number of syscalls executed
-system.cpu0.kern.syscall::total 234 # number of syscalls executed
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+system.cpu0.kern.ipl_used::total 0.810889 # fraction of swpipl calls that actually changed the ipl
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+system.cpu0.kern.syscall::71 27 12.80% 86.73% # number of syscalls executed
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+system.cpu0.kern.syscall::92 7 3.32% 96.21% # number of syscalls executed
+system.cpu0.kern.syscall::97 2 0.95% 97.16% # number of syscalls executed
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+system.cpu0.kern.syscall::132 1 0.47% 98.58% # number of syscalls executed
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system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
-system.cpu0.kern.callpal::wripir 275 0.16% 0.16% # number of callpals executed
-system.cpu0.kern.callpal::wrmces 1 0.00% 0.16% # number of callpals executed
-system.cpu0.kern.callpal::wrfen 1 0.00% 0.16% # number of callpals executed
-system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.16% # number of callpals executed
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-system.cpu0.kern.callpal::total 171120 # number of callpals executed
-system.cpu0.kern.mode_switch::kernel 7202 # number of protection mode switches
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system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches
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+system.cpu0.kern.mode_good::kernel 1285
+system.cpu0.kern.mode_good::user 1286
system.cpu0.kern.mode_good::idle 0
-system.cpu0.kern.mode_switch_good::kernel 0.190225 # fraction of useful protection mode switches
+system.cpu0.kern.mode_switch_good::kernel 0.181986 # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches
-system.cpu0.kern.mode_switch_good::total 0.319725 # fraction of useful protection mode switches
-system.cpu0.kern.mode_ticks::kernel 1902171924000 99.89% 99.89% # number of ticks spent at the given mode
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+system.cpu0.kern.mode_switch_good::total 0.308015 # fraction of useful protection mode switches
+system.cpu0.kern.mode_ticks::kernel 1900726417500 99.89% 99.89% # number of ticks spent at the given mode
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system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode
-system.cpu0.kern.swap_context 3569 # number of times the context was actually changed
+system.cpu0.kern.swap_context 3515 # number of times the context was actually changed
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
-system.cpu1.kern.inst.quiesce 2405 # number of quiesce instructions executed
-system.cpu1.kern.inst.hwrei 53020 # number of hwrei instructions executed
-system.cpu1.kern.ipl_count::0 16452 36.11% 36.11% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::22 1923 4.22% 40.33% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::30 275 0.60% 40.93% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::31 26914 59.07% 100.00% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::total 45564 # number of times we switched to this ipl
-system.cpu1.kern.ipl_good::0 16069 47.18% 47.18% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::22 1923 5.65% 52.82% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::30 275 0.81% 53.63% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::31 15794 46.37% 100.00% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::total 34061 # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_ticks::0 1873583378500 98.41% 98.41% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::22 531505500 0.03% 98.43% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::30 123925000 0.01% 98.44% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::31 29687237000 1.56% 100.00% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::total 1903926046000 # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_used::0 0.976720 # fraction of swpipl calls that actually changed the ipl
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+system.cpu1.kern.ipl_count::0 17233 36.50% 36.50% # number of times we switched to this ipl
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+system.cpu1.kern.ipl_count::30 284 0.60% 41.17% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::31 27775 58.83% 100.00% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::total 47214 # number of times we switched to this ipl
+system.cpu1.kern.ipl_good::0 16850 47.30% 47.30% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::22 1922 5.40% 52.70% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::30 284 0.80% 53.50% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::31 16566 46.50% 100.00% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::total 35622 # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_ticks::0 1871948155000 98.40% 98.40% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::22 531300500 0.03% 98.43% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::30 128640500 0.01% 98.43% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::31 29802235500 1.57% 100.00% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::total 1902410331500 # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_used::0 0.977775 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used::31 0.586832 # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used::total 0.747542 # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.syscall::3 10 10.87% 10.87% # number of syscalls executed
-system.cpu1.kern.syscall::6 9 9.78% 20.65% # number of syscalls executed
-system.cpu1.kern.syscall::15 1 1.09% 21.74% # number of syscalls executed
-system.cpu1.kern.syscall::17 5 5.43% 27.17% # number of syscalls executed
-system.cpu1.kern.syscall::23 3 3.26% 30.43% # number of syscalls executed
-system.cpu1.kern.syscall::24 3 3.26% 33.70% # number of syscalls executed
-system.cpu1.kern.syscall::33 3 3.26% 36.96% # number of syscalls executed
-system.cpu1.kern.syscall::45 15 16.30% 53.26% # number of syscalls executed
-system.cpu1.kern.syscall::47 3 3.26% 56.52% # number of syscalls executed
-system.cpu1.kern.syscall::59 1 1.09% 57.61% # number of syscalls executed
-system.cpu1.kern.syscall::71 27 29.35% 86.96% # number of syscalls executed
-system.cpu1.kern.syscall::74 9 9.78% 96.74% # number of syscalls executed
-system.cpu1.kern.syscall::132 3 3.26% 100.00% # number of syscalls executed
-system.cpu1.kern.syscall::total 92 # number of syscalls executed
+system.cpu1.kern.ipl_used::31 0.596436 # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.ipl_used::total 0.754480 # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.syscall::2 1 0.87% 0.87% # number of syscalls executed
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system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
-system.cpu1.kern.callpal::wripir 193 0.41% 0.41% # number of callpals executed
-system.cpu1.kern.callpal::wrmces 1 0.00% 0.42% # number of callpals executed
-system.cpu1.kern.callpal::wrfen 1 0.00% 0.42% # number of callpals executed
-system.cpu1.kern.callpal::swpctx 1035 2.21% 2.63% # number of callpals executed
-system.cpu1.kern.callpal::tbi 3 0.01% 2.63% # number of callpals executed
-system.cpu1.kern.callpal::wrent 7 0.01% 2.65% # number of callpals executed
-system.cpu1.kern.callpal::swpipl 40418 86.22% 88.87% # number of callpals executed
-system.cpu1.kern.callpal::rdps 2100 4.48% 93.35% # number of callpals executed
-system.cpu1.kern.callpal::wrkgp 1 0.00% 93.35% # number of callpals executed
-system.cpu1.kern.callpal::wrusp 3 0.01% 93.36% # number of callpals executed
-system.cpu1.kern.callpal::whami 3 0.01% 93.36% # number of callpals executed
-system.cpu1.kern.callpal::rti 2947 6.29% 99.65% # number of callpals executed
-system.cpu1.kern.callpal::callsys 121 0.26% 99.91% # number of callpals executed
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+system.cpu1.kern.callpal::wrfen 1 0.00% 0.40% # number of callpals executed
+system.cpu1.kern.callpal::swpctx 1095 2.25% 2.65% # number of callpals executed
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+system.cpu1.kern.callpal::rdusp 1 0.00% 93.30% # number of callpals executed
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+system.cpu1.kern.callpal::callsys 172 0.35% 99.91% # number of callpals executed
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system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed
-system.cpu1.kern.callpal::total 46877 # number of callpals executed
-system.cpu1.kern.mode_switch::kernel 1217 # number of protection mode switches
-system.cpu1.kern.mode_switch::user 367 # number of protection mode switches
-system.cpu1.kern.mode_switch::idle 2392 # number of protection mode switches
-system.cpu1.kern.mode_good::kernel 567
-system.cpu1.kern.mode_good::user 367
-system.cpu1.kern.mode_good::idle 200
-system.cpu1.kern.mode_switch_good::kernel 0.465900 # fraction of useful protection mode switches
+system.cpu1.kern.callpal::total 48756 # number of callpals executed
+system.cpu1.kern.mode_switch::kernel 1363 # number of protection mode switches
+system.cpu1.kern.mode_switch::user 459 # number of protection mode switches
+system.cpu1.kern.mode_switch::idle 2408 # number of protection mode switches
+system.cpu1.kern.mode_good::kernel 668
+system.cpu1.kern.mode_good::user 459
+system.cpu1.kern.mode_good::idle 209
+system.cpu1.kern.mode_switch_good::kernel 0.490095 # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good::idle 0.083612 # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good::total 0.285211 # fraction of useful protection mode switches
-system.cpu1.kern.mode_ticks::kernel 3949860500 0.21% 0.21% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::user 686482000 0.04% 0.24% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::idle 1898967291500 99.76% 100.00% # number of ticks spent at the given mode
-system.cpu1.kern.swap_context 1036 # number of times the context was actually changed
+system.cpu1.kern.mode_switch_good::idle 0.086794 # fraction of useful protection mode switches
+system.cpu1.kern.mode_switch_good::total 0.315839 # fraction of useful protection mode switches
+system.cpu1.kern.mode_ticks::kernel 4405402000 0.23% 0.23% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks::user 814709500 0.04% 0.27% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks::idle 1897179577000 99.73% 100.00% # number of ticks spent at the given mode
+system.cpu1.kern.swap_context 1096 # number of times the context was actually changed
---------- End Simulation Statistics ----------
sim_ticks 1860200687500 # Number of ticks simulated
final_tick 1860200687500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 112423 # Simulator instruction rate (inst/s)
-host_op_rate 112423 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 3947369845 # Simulator tick rate (ticks/s)
-host_mem_usage 310252 # Number of bytes of host memory used
-host_seconds 471.25 # Real time elapsed on the host
+host_inst_rate 95880 # Simulator instruction rate (inst/s)
+host_op_rate 95880 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 3366492305 # Simulator tick rate (ticks/s)
+host_mem_usage 308824 # Number of bytes of host memory used
+host_seconds 552.56 # Real time elapsed on the host
sim_insts 52979577 # Number of instructions simulated
sim_ops 52979577 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 963968 # Number of bytes read from this memory
system.physmem.bw_total::cpu.data 13374523 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::tsunami.ide 1425807 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 19358943 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 445243 # Total number of read requests seen
-system.physmem.writeReqs 117437 # Total number of write requests seen
-system.physmem.cpureqs 562856 # Reqs generatd by CPU via cache - shady
+system.physmem.readReqs 445243 # Total number of read requests accepted by DRAM controller
+system.physmem.writeReqs 117437 # Total number of write requests accepted by DRAM controller
+system.physmem.readBursts 445243 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
+system.physmem.writeBursts 117437 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
system.physmem.bytesRead 28495552 # Total number of bytes read from memory
system.physmem.bytesWritten 7515968 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 28495552 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 7515968 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 55 # Number of read reqs serviced by write Q
+system.physmem.servicedByWrQ 55 # Number of DRAM read bursts serviced by write Q
system.physmem.neitherReadNorWrite 175 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 28218 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 27974 # Track reads on a per bank basis
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 917369 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124679 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 124679 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::system.bridge.slave 33056 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::system.physmem.port 1008832 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::system.membus.badaddr_responder.pio 160 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 1042048 # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44148 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30702464 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 30746612 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5309056 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::total 5309056 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::system.bridge.slave 44148 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::system.physmem.port 36011520 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total 36055668 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 36055668 # Total data (bytes)
system.membus.snoop_data_through_bus 35584 # Total snoop data (bytes)
system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
system.membus.respLayer2.occupancy 376215241 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.iocache.tags.replacements 41685 # number of replacements
-system.iocache.tags.tagsinuse 1.261083 # Cycle average of tags in use
-system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks.
-system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle 1710344305000 # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::tsunami.ide 1.261083 # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::tsunami.ide 0.078818 # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total 0.078818 # Average percentage of cache occupancy
+system.iocache.tags.replacements 41685 # number of replacements
+system.iocache.tags.tagsinuse 1.261083 # Cycle average of tags in use
+system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
+system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks.
+system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
+system.iocache.tags.warmup_cycle 1710344305000 # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::tsunami.ide 1.261083 # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::tsunami.ide 0.078818 # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total 0.078818 # Average percentage of cache occupancy
system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses
system.iocache.ReadReq_misses::total 173 # number of ReadReq misses
system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses
system.iobus.pkt_count_system.bridge.master::total 33056 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.tsunami.cchip.pio 5052 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.tsunami.uart.pio 18120 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total 116506 # Packet count per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 20208 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::total 44148 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.tsunami.cchip.pio 20208 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::total 2705756 # Cumulative packet size per connected master and slave (bytes)
system.iobus.data_through_bus 2705756 # Total data (bytes)
system.iobus.reqLayer0.occupancy 4663000 # Layer occupancy (ticks)
system.cpu.toL2Bus.trans_dist::ReadExReq 342614 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 301063 # Transaction distribution
system.cpu.toL2Bus.trans_dist::BadAddressError 80 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 2019865 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 3677460 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count 5697325 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 64631872 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 143567348 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size 208199220 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2019865 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3677460 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 5697325 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 64631872 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143567348 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total 208199220 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus 208189172 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 17664 # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy 2480161498 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 2194600669 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
-system.cpu.icache.tags.replacements 1009263 # number of replacements
-system.cpu.icache.tags.tagsinuse 509.727374 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 7487430 # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs 1009771 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 7.414978 # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle 25799742250 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 509.727374 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.995561 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.995561 # Average percentage of cache occupancy
+system.cpu.icache.tags.replacements 1009263 # number of replacements
+system.cpu.icache.tags.tagsinuse 509.727374 # Cycle average of tags in use
+system.cpu.icache.tags.total_refs 7487430 # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs 1009771 # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs 7.414978 # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle 25799742250 # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst 509.727374 # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst 0.995561 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total 0.995561 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 7487431 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 7487431 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 7487431 # number of demand (read+write) hits
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12151.922838 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 12151.922838 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements 338298 # number of replacements
-system.cpu.l2cache.tags.tagsinuse 65343.107599 # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs 2545731 # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs 403463 # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs 6.309701 # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle 5353022750 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.replacements 338298 # number of replacements
+system.cpu.l2cache.tags.tagsinuse 65343.107599 # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs 2545731 # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs 403463 # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs 6.309701 # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle 5353022750 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 53859.326644 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 5308.706799 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 6175.074156 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 5308.706799 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 6175.074156 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.821828 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.081004 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.094224 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total 0.997057 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total 0.997057 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 994809 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 826788 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 1821597 # number of ReadReq hits
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements 1401048 # number of replacements
-system.cpu.dcache.tags.tagsinuse 511.994535 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 11808107 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 1401560 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 8.424974 # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle 25348250 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 511.994535 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.999989 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.999989 # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements 1401048 # number of replacements
+system.cpu.dcache.tags.tagsinuse 511.994535 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 11808107 # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs 1401560 # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 8.424974 # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle 25348250 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data 511.994535 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data 0.999989 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total 0.999989 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 7202464 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 7202464 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 4203713 # number of WriteReq hits
sim_ticks 1842705252000 # Number of ticks simulated
final_tick 1842705252000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 221595 # Simulator instruction rate (inst/s)
-host_op_rate 221595 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 5621199023 # Simulator tick rate (ticks/s)
-host_mem_usage 308252 # Number of bytes of host memory used
-host_seconds 327.81 # Real time elapsed on the host
+host_inst_rate 308319 # Simulator instruction rate (inst/s)
+host_op_rate 308319 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 7821132493 # Simulator tick rate (ticks/s)
+host_mem_usage 307864 # Number of bytes of host memory used
+host_seconds 235.61 # Real time elapsed on the host
sim_insts 72641883 # Number of instructions simulated
sim_ops 72641883 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu0.inst 488448 # Number of bytes read from this memory
system.physmem.bw_total::cpu2.inst 153097 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.data 1370680 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 19479638 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 99238 # Total number of read requests seen
-system.physmem.writeReqs 44800 # Total number of write requests seen
-system.physmem.cpureqs 144082 # Reqs generatd by CPU via cache - shady
+system.physmem.readReqs 99238 # Total number of read requests accepted by DRAM controller
+system.physmem.writeReqs 44800 # Total number of write requests accepted by DRAM controller
+system.physmem.readBursts 99238 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
+system.physmem.writeBursts 44800 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
system.physmem.bytesRead 6351232 # Total number of bytes read from memory
system.physmem.bytesWritten 2867200 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 6351232 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 2867200 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 11 # Number of read reqs serviced by write Q
+system.physmem.servicedByWrQ 11 # Number of DRAM read bursts serviced by write Q
system.physmem.neitherReadNorWrite 44 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 6232 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 6043 # Track reads on a per bank basis
system.membus.pkt_count_system.l2c.mem_side::total 205046 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 51865 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 51865 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::system.bridge.slave 13322 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::system.physmem.port 243525 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::system.membus.badaddr_responder.pio 64 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 256911 # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 15754 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 7009472 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::total 7025226 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 2208960 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::total 2208960 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::system.bridge.slave 15754 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::system.physmem.port 9218432 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total 9234186 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 35966088 # Total data (bytes)
system.membus.snoop_data_through_bus 10112 # Total snoop data (bytes)
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
system.membus.respLayer2.occupancy 156435750 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
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-system.l2c.tags.tagsinuse 65423.390976 # Cycle average of tags in use
-system.l2c.tags.total_refs 2471195 # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs 402547 # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs 6.138898 # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle 614754000 # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks 54840.022307 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst 2455.785986 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data 2733.317890 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst 573.564095 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data 593.217562 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.inst 2104.783507 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.data 2122.699630 # Average occupied blocks per requestor
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system.l2c.ReadReq_hits::cpu0.inst 518817 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data 493229 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst 124693 # number of ReadReq hits
system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.iocache.tags.replacements 41685 # number of replacements
-system.iocache.tags.tagsinuse 1.254957 # Cycle average of tags in use
-system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks.
-system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle 1694872745000 # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::tsunami.ide 1.254957 # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::tsunami.ide 0.078435 # Average percentage of cache occupancy
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+system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
+system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks.
+system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
+system.iocache.tags.warmup_cycle 1694872745000 # Cycle when the warmup percentage was hit.
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system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses
system.iocache.ReadReq_misses::total 173 # number of ReadReq misses
system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses
system.cpu0.num_mem_refs 8444409 # number of memory refs
system.cpu0.num_load_insts 4931349 # Number of load instructions
system.cpu0.num_store_insts 3513060 # Number of store instructions
-system.cpu0.num_idle_cycles 212988700365.392029 # Number of idle cycles
-system.cpu0.num_busy_cycles -212060383474.392029 # Number of busy cycles
-system.cpu0.not_idle_fraction -228.435339 # Percentage of non-idle cycles
-system.cpu0.idle_fraction 229.435339 # Percentage of idle cycles
+system.cpu0.num_idle_cycles 903633014.989213 # Number of idle cycles
+system.cpu0.num_busy_cycles 24683876.010787 # Number of busy cycles
+system.cpu0.not_idle_fraction 0.026590 # Percentage of non-idle cycles
+system.cpu0.idle_fraction 0.973410 # Percentage of idle cycles
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
system.cpu0.kern.inst.quiesce 6419 # number of quiesce instructions executed
system.cpu0.kern.inst.hwrei 211396 # number of hwrei instructions executed
system.toL2Bus.trans_dist::ReadExReq 151061 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 133781 # Transaction distribution
system.toL2Bus.trans_dist::BadAddressError 32 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 849315 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 1370344 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count 2219659 # Packet count per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 27177600 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 55325386 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size 82502986 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 849315 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1370344 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 2219659 # Packet count per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 27177600 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 55325386 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size::total 82502986 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.data_through_bus 203464200 # Total data (bytes)
system.toL2Bus.snoop_data_through_bus 11072 # Total snoop data (bytes)
system.toL2Bus.reqLayer0.occupancy 2135432500 # Layer occupancy (ticks)
system.iobus.pkt_count_system.bridge.master::total 13322 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 34700 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::total 34700 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.tsunami.cchip.pio 2342 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.tsunami.pchip.pio 140 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.tsunami.io.pio 66 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.tsunami.uart.pio 8320 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.tsunami.ide.pio 2420 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.tsunami.ide-pciconf 34 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.iocache.cpu_side 34700 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total 48022 # Packet count per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 9368 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 560 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::total 15754 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 1107376 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 1107376 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.tsunami.cchip.pio 9368 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.tsunami.pchip.pio 560 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.tsunami.io.pio 61 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.tsunami.uart.pio 4160 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.tsunami.ide.pio 1574 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.tsunami.ide-pciconf 31 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.iocache.cpu_side 1107376 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::total 1123130 # Cumulative packet size per connected master and slave (bytes)
system.iobus.data_through_bus 2707184 # Total data (bytes)
system.iobus.reqLayer0.occupancy 2208000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer1.occupancy 17990250 # Layer occupancy (ticks)
system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.cpu0.icache.tags.replacements 950451 # number of replacements
-system.cpu0.icache.tags.tagsinuse 511.192015 # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs 43221003 # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs 950962 # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs 45.449769 # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle 10381115250 # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.replacements 950451 # number of replacements
+system.cpu0.icache.tags.tagsinuse 511.192015 # Cycle average of tags in use
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+system.cpu0.icache.tags.sampled_refs 950962 # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs 45.449769 # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle 10381115250 # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst 246.999230 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu1.inst 99.674980 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu2.inst 164.517805 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.482420 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu1.inst 0.194678 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu2.inst 0.321324 # Average percentage of cache occupancy
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system.cpu0.icache.ReadReq_hits::cpu0.inst 33216972 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst 7763860 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu2.inst 2240171 # number of ReadReq hits
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12348.793741 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 12348.272007 # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.dcache.tags.replacements 1391525 # number of replacements
-system.cpu0.dcache.tags.tagsinuse 511.997811 # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs 13285085 # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs 1392037 # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs 9.543629 # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.tags.replacements 1391525 # number of replacements
+system.cpu0.dcache.tags.tagsinuse 511.997811 # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs 13285085 # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs 1392037 # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs 9.543629 # Average number of references to valid blocks.
+system.cpu0.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data 250.196143 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu1.data 130.348399 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu2.data 131.453270 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.488664 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu1.data 0.254587 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu2.data 0.256745 # Average percentage of cache occupancy
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system.cpu0.dcache.ReadReq_hits::cpu0.data 4073389 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data 1086662 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu2.data 2399601 # number of ReadReq hits
system.cpu1.num_mem_refs 2116682 # number of memory refs
system.cpu1.num_load_insts 1209934 # Number of load instructions
system.cpu1.num_store_insts 906748 # Number of store instructions
-system.cpu1.num_idle_cycles -715527638.238183 # Number of idle cycles
-system.cpu1.num_busy_cycles 1669158056.238183 # Number of busy cycles
-system.cpu1.not_idle_fraction 1.750320 # Percentage of non-idle cycles
-system.cpu1.idle_fraction -0.750320 # Percentage of idle cycles
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+system.cpu1.num_busy_cycles 29929440.536089 # Number of busy cycles
+system.cpu1.not_idle_fraction 0.031385 # Percentage of non-idle cycles
+system.cpu1.idle_fraction 0.968615 # Percentage of idle cycles
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
system.cpu1.kern.inst.hwrei 0 # number of hwrei instructions executed
---------- Begin Simulation Statistics ----------
-sim_seconds 2.534332 # Number of seconds simulated
-sim_ticks 2534332336000 # Number of ticks simulated
-final_tick 2534332336000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 2.524310 # Number of seconds simulated
+sim_ticks 2524309551500 # Number of ticks simulated
+final_tick 2524309551500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 47356 # Simulator instruction rate (inst/s)
-host_op_rate 60934 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1990051953 # Simulator tick rate (ticks/s)
-host_mem_usage 400524 # Number of bytes of host memory used
-host_seconds 1273.50 # Real time elapsed on the host
-sim_insts 60307773 # Number of instructions simulated
-sim_ops 77599321 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::realview.clcd 119572608 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.dtb.walker 2816 # Number of bytes read from this memory
+host_inst_rate 67450 # Simulator instruction rate (inst/s)
+host_op_rate 86789 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2823365435 # Simulator tick rate (ticks/s)
+host_mem_usage 397608 # Number of bytes of host memory used
+host_seconds 894.08 # Real time elapsed on the host
+sim_insts 60305560 # Number of instructions simulated
+sim_ops 77596391 # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.dtb.walker 3264 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst 798144 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 9095056 # Number of bytes read from this memory
-system.physmem.bytes_read::total 129468752 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 798144 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 798144 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 3785216 # Number of bytes written to this memory
+system.physmem.bytes_read::cpu.inst 796608 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 9093968 # Number of bytes read from this memory
+system.physmem.bytes_read::total 129431632 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 796608 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 796608 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 3783552 # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory
-system.physmem.bytes_written::total 6801288 # Number of bytes written to this memory
-system.physmem.num_reads::realview.clcd 14946576 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.dtb.walker 44 # Number of read requests responded to by this memory
+system.physmem.bytes_written::total 6799624 # Number of bytes written to this memory
+system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.dtb.walker 51 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst 12471 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 142144 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 15101237 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 59144 # Number of write requests responded to by this memory
+system.physmem.num_reads::cpu.inst 12447 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 142127 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 15096835 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 59118 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 813162 # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd 47181108 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.dtb.walker 1111 # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total 813136 # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd 47354598 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.dtb.walker 1293 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker 51 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst 314933 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 3588738 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 51085941 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 314933 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 314933 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1493575 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data 1190085 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 2683661 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1493575 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd 47181108 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker 1111 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 315575 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 3602557 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 51274073 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 315575 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 315575 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 1498846 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data 1194811 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 2693657 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 1498846 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd 47354598 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker 1293 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker 51 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 314933 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 4778824 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 53769602 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 15101237 # Total number of read requests seen
-system.physmem.writeReqs 813162 # Total number of write requests seen
-system.physmem.cpureqs 218445 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 966479168 # Total number of bytes read from memory
-system.physmem.bytesWritten 52042368 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 129468752 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 6801288 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 279 # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite 4676 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 944611 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 944270 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 944423 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 944612 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 943754 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 943694 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 943515 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 943302 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 944002 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 943653 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 943221 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 942812 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 943924 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 943688 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 943784 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 943693 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 49130 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 48913 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2 50969 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 51083 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 51011 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5 51261 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6 51258 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 51200 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 51354 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 51098 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 50757 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11 50407 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12 51356 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13 50977 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14 51264 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15 51124 # Track writes on a per bank basis
+system.physmem.bw_total::cpu.inst 315575 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 4797367 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 53967730 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 15096835 # Total number of read requests accepted by DRAM controller
+system.physmem.writeReqs 813136 # Total number of write requests accepted by DRAM controller
+system.physmem.readBursts 15096835 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
+system.physmem.writeBursts 813136 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
+system.physmem.bytesRead 966197440 # Total number of bytes read from memory
+system.physmem.bytesWritten 52040704 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 129431632 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 6799624 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 6192 # Number of DRAM read bursts serviced by write Q
+system.physmem.neitherReadNorWrite 4675 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 943576 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 943244 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 943285 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 942562 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 943112 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 943339 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 943114 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 941930 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 944001 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 943651 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 943211 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 941608 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 943926 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 943681 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 943781 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 942622 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 6701 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 6473 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 6622 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 6647 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 6560 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 6809 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 6802 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 6725 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 7149 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 6889 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 6554 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 6197 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 7152 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 6775 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 7049 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 6917 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
-system.physmem.numWrRetry 32457 # Number of times wr buffer was full causing retry
-system.physmem.totGap 2534332242000 # Total gap between requests
+system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
+system.physmem.totGap 2524308440000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 36 # Categorize read packet sizes
-system.physmem.readPktSize::3 14946576 # Categorize read packet sizes
+system.physmem.readPktSize::3 14942208 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 154625 # Categorize read packet sizes
+system.physmem.readPktSize::6 154591 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
system.physmem.writePktSize::2 754018 # Categorize write packet sizes
system.physmem.writePktSize::3 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
-system.physmem.writePktSize::6 59144 # Categorize write packet sizes
-system.physmem.rdQLenPdf::0 1052232 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 984006 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 974713 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 3682136 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 2757823 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 2756219 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 2725955 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 17025 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 15237 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 28723 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 42159 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11 28643 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12 9083 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13 9038 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14 12526 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15 5326 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16 104 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17 7 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18 2 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 59118 # Categorize write packet sizes
+system.physmem.rdQLenPdf::0 1057147 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 988434 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 981496 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 3682842 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 2771885 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 2756532 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 2709889 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 18251 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 16218 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 29451 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10 42435 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11 28819 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12 1928 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13 1827 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14 1752 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15 1697 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16 27 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17 9 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 2588 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 2654 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 2707 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 2777 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 2803 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 2823 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6 2850 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 2875 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8 2885 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9 35355 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10 35355 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11 35355 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12 35355 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13 35355 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14 35355 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 35355 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 35355 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 35355 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 35355 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 35355 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 35354 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 35354 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 35354 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 32767 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 32701 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 32648 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 32578 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 32552 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 32532 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 32505 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 32480 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 32470 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 42332 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 24053.235566 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 1833.734815 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 32311.504914 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::64-95 8211 19.40% 19.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-159 3440 8.13% 27.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::192-223 2237 5.28% 32.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-287 1775 4.19% 37.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::320-351 1231 2.91% 39.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-415 1031 2.44% 42.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::448-479 888 2.10% 44.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-543 774 1.83% 46.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::576-607 547 1.29% 47.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-671 559 1.32% 48.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::704-735 426 1.01% 49.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-799 432 1.02% 50.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::832-863 287 0.68% 51.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-927 279 0.66% 52.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::960-991 159 0.38% 52.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1055 249 0.59% 53.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1088-1119 131 0.31% 53.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1152-1183 141 0.33% 53.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1216-1247 101 0.24% 54.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1280-1311 136 0.32% 54.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1344-1375 82 0.19% 54.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1408-1439 379 0.90% 55.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1472-1503 1813 4.28% 59.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1536-1567 447 1.06% 60.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1600-1631 86 0.20% 61.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1664-1695 158 0.37% 61.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1728-1759 41 0.10% 61.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1792-1823 104 0.25% 61.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1856-1887 37 0.09% 61.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1920-1951 64 0.15% 62.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1984-2015 25 0.06% 62.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2048-2079 71 0.17% 62.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2112-2143 17 0.04% 62.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2176-2207 45 0.11% 62.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2240-2271 11 0.03% 62.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2304-2335 40 0.09% 62.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2368-2399 10 0.02% 62.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2432-2463 26 0.06% 62.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2496-2527 12 0.03% 62.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2560-2591 19 0.04% 62.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2624-2655 3 0.01% 62.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2688-2719 16 0.04% 62.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2752-2783 8 0.02% 62.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2816-2847 18 0.04% 62.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2880-2911 12 0.03% 62.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2944-2975 13 0.03% 62.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3008-3039 6 0.01% 62.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3072-3103 25 0.06% 62.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3136-3167 6 0.01% 62.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3200-3231 6 0.01% 62.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3264-3295 9 0.02% 62.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3328-3359 13 0.03% 62.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3392-3423 6 0.01% 62.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3456-3487 6 0.01% 63.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3520-3551 2 0.00% 63.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3584-3615 9 0.02% 63.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3648-3679 6 0.01% 63.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3712-3743 8 0.02% 63.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3776-3807 5 0.01% 63.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3840-3871 1 0.00% 63.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3904-3935 4 0.01% 63.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3968-3999 6 0.01% 63.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4032-4063 4 0.01% 63.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4096-4127 43 0.10% 63.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4160-4191 2 0.00% 63.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4224-4255 3 0.01% 63.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4288-4319 7 0.02% 63.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4352-4383 8 0.02% 63.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4416-4447 8 0.02% 63.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4480-4511 6 0.01% 63.29% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4544-4575 4 0.01% 63.29% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4608-4639 7 0.02% 63.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4736-4767 4 0.01% 63.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4864-4895 2 0.00% 63.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4928-4959 3 0.01% 63.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4992-5023 2 0.00% 63.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5120-5151 10 0.02% 63.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5184-5215 3 0.01% 63.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5248-5279 2 0.00% 63.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5312-5343 1 0.00% 63.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5376-5407 2 0.00% 63.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5440-5471 1 0.00% 63.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5632-5663 1 0.00% 63.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5696-5727 1 0.00% 63.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5760-5791 1 0.00% 63.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5824-5855 3 0.01% 63.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5888-5919 5 0.01% 63.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5952-5983 1 0.00% 63.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6016-6047 1 0.00% 63.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6080-6111 1 0.00% 63.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6144-6175 7 0.02% 63.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6208-6239 1 0.00% 63.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6272-6303 1 0.00% 63.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6464-6495 2 0.00% 63.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6528-6559 4 0.01% 63.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6592-6623 3 0.01% 63.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6656-6687 2 0.00% 63.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6720-6751 1 0.00% 63.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6784-6815 20 0.05% 63.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6848-6879 3 0.01% 63.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6912-6943 3 0.01% 63.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6976-7007 1 0.00% 63.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7040-7071 4 0.01% 63.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7104-7135 1 0.00% 63.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7168-7199 4 0.01% 63.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7296-7327 1 0.00% 63.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7360-7391 1 0.00% 63.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7424-7455 4 0.01% 63.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7488-7519 1 0.00% 63.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7552-7583 3 0.01% 63.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7616-7647 1 0.00% 63.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7680-7711 7 0.02% 63.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7744-7775 1 0.00% 63.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7808-7839 3 0.01% 63.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7872-7903 2 0.00% 63.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7936-7967 3 0.01% 63.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8000-8031 3 0.01% 63.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8064-8095 11 0.03% 63.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8128-8159 4 0.01% 63.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8192-8223 322 0.76% 64.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8448-8479 1 0.00% 64.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8704-8735 1 0.00% 64.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8960-8991 1 0.00% 64.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9216-9247 1 0.00% 64.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10240-10271 18 0.04% 64.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10496-10527 2 0.00% 64.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11008-11039 1 0.00% 64.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11264-11295 2 0.00% 64.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11520-11551 1 0.00% 64.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11776-11807 1 0.00% 64.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12288-12319 3 0.01% 64.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12480-12511 1 0.00% 64.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12544-12575 1 0.00% 64.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12800-12831 1 0.00% 64.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13056-13087 1 0.00% 64.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13312-13343 2 0.00% 64.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14336-14367 5 0.01% 64.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14464-14495 1 0.00% 64.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14592-14623 1 0.00% 64.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15360-15391 3 0.01% 64.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15808-15839 1 0.00% 64.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16384-16415 2 0.00% 64.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16960-16991 1 0.00% 64.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::17216-17247 4 0.01% 64.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::17408-17439 5 0.01% 64.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::17920-17951 2 0.00% 64.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::18368-18399 1 0.00% 64.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::18432-18463 1 0.00% 64.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::18688-18719 1 0.00% 64.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::18816-18847 1 0.00% 64.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::18944-18975 1 0.00% 64.58% # Bytes accessed per row activation
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-system.physmem.bytesPerActivate::19456-19487 3 0.01% 64.59% # Bytes accessed per row activation
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-system.physmem.bytesPerActivate::21504-21535 1 0.00% 64.61% # Bytes accessed per row activation
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-system.physmem.bytesPerActivate::23040-23071 1 0.00% 64.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::23552-23583 1 0.00% 64.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::24000-24031 1 0.00% 64.62% # Bytes accessed per row activation
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-system.physmem.bytesPerActivate::24320-24351 2 0.00% 64.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::24576-24607 4 0.01% 64.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::24640-24671 1 0.00% 64.64% # Bytes accessed per row activation
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-system.physmem.bytesPerActivate::24832-24863 1 0.00% 64.65% # Bytes accessed per row activation
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-system.physmem.bytesPerActivate::31744-31775 2 0.00% 64.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::31936-31967 1 0.00% 64.74% # Bytes accessed per row activation
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-system.physmem.bytesPerActivate::33536-33567 6 0.01% 64.77% # Bytes accessed per row activation
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-system.physmem.bytesPerActivate::35200-35231 1 0.00% 64.89% # Bytes accessed per row activation
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-system.physmem.bytesPerActivate::38912-38943 1 0.00% 64.91% # Bytes accessed per row activation
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-system.physmem.bytesPerActivate::40704-40735 1 0.00% 64.91% # Bytes accessed per row activation
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-system.physmem.bytesPerActivate::41984-42015 1 0.00% 64.92% # Bytes accessed per row activation
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-system.physmem.bytesPerActivate::52224-52255 1 0.00% 64.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::52992-53023 1 0.00% 64.94% # Bytes accessed per row activation
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-system.physmem.bytesPerActivate::58368-58399 2 0.00% 64.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::62464-62495 1 0.00% 64.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::62528-62559 1 0.00% 64.96% # Bytes accessed per row activation
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-system.physmem.bytesPerActivate::65280-65311 18 0.04% 65.07% # Bytes accessed per row activation
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-system.physmem.bytesPerActivate::65472-65503 12 0.03% 65.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::65536-65567 14415 34.05% 99.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::130816-130847 1 0.00% 99.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::131072-131103 330 0.78% 99.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::131200-131231 1 0.00% 99.96% # Bytes accessed per row activation
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-system.physmem.bytesPerActivate::136576-136607 1 0.00% 99.97% # Bytes accessed per row activation
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-system.physmem.bytesPerActivate::160704-160735 1 0.00% 99.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::160768-160799 1 0.00% 99.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::192512-192543 1 0.00% 99.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::196416-196447 1 0.00% 99.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::196608-196639 8 0.02% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 42332 # Bytes accessed per row activation
-system.physmem.totQLat 352162436750 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 443380465500 # Sum of mem lat for all requests
-system.physmem.totBusLat 75504790000 # Total cycles spent in databus access
-system.physmem.totBankLat 15713238750 # Total cycles spent in bank access
-system.physmem.avgQLat 23320.54 # Average queueing delay per request
-system.physmem.avgBankLat 1040.55 # Average bank access latency per request
+system.physmem.wrQLenPdf::0 4688 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::24 2 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples 39039 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 24916.423474 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 2046.440838 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 31393.496682 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::64-79 6673 17.09% 17.09% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-143 3432 8.79% 25.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::192-207 2242 5.74% 31.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-271 1810 4.64% 36.26% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::320-335 1230 3.15% 39.41% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-399 1032 2.64% 42.06% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::448-463 839 2.15% 44.21% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-527 821 2.10% 46.31% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::576-591 572 1.47% 47.78% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-655 506 1.30% 49.07% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::704-719 409 1.05% 50.12% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-783 444 1.14% 51.26% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::832-847 300 0.77% 52.02% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-911 247 0.63% 52.66% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::960-975 176 0.45% 53.11% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1039 206 0.53% 53.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1088-1103 143 0.37% 54.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1152-1167 146 0.37% 54.38% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1216-1231 98 0.25% 54.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1280-1295 114 0.29% 54.92% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1344-1359 72 0.18% 55.10% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1408-1423 399 1.02% 56.13% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1472-1487 280 0.72% 56.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1536-1551 475 1.22% 58.06% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1600-1615 79 0.20% 58.26% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1664-1679 157 0.40% 58.66% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1728-1743 41 0.11% 58.77% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1792-1807 100 0.26% 59.03% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1856-1871 28 0.07% 59.10% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1920-1935 78 0.20% 59.30% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1984-1999 27 0.07% 59.37% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2048-2063 49 0.13% 59.49% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2112-2127 25 0.06% 59.56% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2176-2191 51 0.13% 59.69% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2240-2255 21 0.05% 59.74% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2304-2319 30 0.08% 59.82% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::total 39039 # Bytes accessed per row activation
+system.physmem.totQLat 291463008250 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 382223273250 # Sum of mem lat for all requests
+system.physmem.totBusLat 75453215000 # Total cycles spent in databus access
+system.physmem.totBankLat 15307050000 # Total cycles spent in bank access
+system.physmem.avgQLat 19314.15 # Average queueing delay per request
+system.physmem.avgBankLat 1014.34 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 29361.08 # Average memory access latency
-system.physmem.avgRdBW 381.35 # Average achieved read bandwidth in MB/s
-system.physmem.avgWrBW 20.53 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 51.09 # Average consumed read bandwidth in MB/s
-system.physmem.avgConsumedWrBW 2.68 # Average consumed write bandwidth in MB/s
+system.physmem.avgMemAccLat 25328.49 # Average memory access latency
+system.physmem.avgRdBW 382.76 # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW 20.62 # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW 51.27 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedWrBW 2.69 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
-system.physmem.busUtil 3.14 # Data bus utilization in percentage
-system.physmem.avgRdQLen 0.17 # Average read queue length over time
-system.physmem.avgWrQLen 10.77 # Average write queue length over time
-system.physmem.readRowHits 15074158 # Number of row buffer hits during reads
-system.physmem.writeRowHits 797610 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 99.82 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 98.09 # Row buffer hit rate for writes
-system.physmem.avgGap 159247.75 # Average gap between requests
+system.physmem.busUtil 3.15 # Data bus utilization in percentage
+system.physmem.avgRdQLen 0.15 # Average read queue length over time
+system.physmem.avgWrQLen 14.41 # Average write queue length over time
+system.physmem.readRowHits 15065383 # Number of row buffer hits during reads
+system.physmem.writeRowHits 94229 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 99.83 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 11.59 # Row buffer hit rate for writes
+system.physmem.avgGap 158662.04 # Average gap between requests
system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory
system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput 54715776 # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq 16153842 # Transaction distribution
-system.membus.trans_dist::ReadResp 16153842 # Transaction distribution
-system.membus.trans_dist::WriteReq 763336 # Transaction distribution
-system.membus.trans_dist::WriteResp 763336 # Transaction distribution
-system.membus.trans_dist::Writeback 59144 # Transaction distribution
+system.membus.throughput 54917647 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 16149440 # Transaction distribution
+system.membus.trans_dist::ReadResp 16149440 # Transaction distribution
+system.membus.trans_dist::WriteReq 763332 # Transaction distribution
+system.membus.trans_dist::WriteResp 763332 # Transaction distribution
+system.membus.trans_dist::Writeback 59118 # Transaction distribution
system.membus.trans_dist::UpgradeReq 4673 # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 4676 # Transaction distribution
-system.membus.trans_dist::ReadExReq 131438 # Transaction distribution
-system.membus.trans_dist::ReadExResp 131438 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2382948 # Packet count per connected master and slave (bytes)
+system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 4675 # Transaction distribution
+system.membus.trans_dist::ReadExReq 131433 # Transaction distribution
+system.membus.trans_dist::ReadExResp 131433 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2382940 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1885854 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3770 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3760 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4272576 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 29893152 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total 29893152 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::system.bridge.slave 2382948 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::system.physmem.port 31779006 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::system.realview.gic.pio 3770 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 34165728 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390313 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1885758 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4272462 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 29884416 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total 29884416 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 34156878 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390297 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16697432 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7540 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7520 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19095353 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 119572608 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.iocache.mem_side::total 119572608 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::system.bridge.slave 2390313 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::system.physmem.port 136270040 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::system.realview.gic.pio 7540 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 138667961 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 138667961 # Total data (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16693592 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19091477 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 119537664 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.iocache.mem_side::total 119537664 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total 138629141 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 138629141 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy 1475262000 # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy 1475500000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.membus.reqLayer1.occupancy 1000 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 17374745000 # Layer occupancy (ticks)
-system.membus.reqLayer2.utilization 0.7 # Layer utilization (%)
-system.membus.reqLayer3.occupancy 3634500 # Layer occupancy (ticks)
-system.membus.reqLayer3.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer5.occupancy 1500 # Layer occupancy (ticks)
-system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer1.occupancy 4718589198 # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy 3702500 # Layer occupancy (ticks)
+system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
+system.membus.reqLayer4.occupancy 1500 # Layer occupancy (ticks)
+system.membus.reqLayer4.utilization 0.0 # Layer utilization (%)
+system.membus.reqLayer6.occupancy 17367026000 # Layer occupancy (ticks)
+system.membus.reqLayer6.utilization 0.7 # Layer utilization (%)
+system.membus.respLayer1.occupancy 4748565769 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
-system.membus.respLayer2.occupancy 33742309741 # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy 33728733739 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 1.3 # Layer utilization (%)
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
-system.iobus.throughput 48124265 # Throughput (bytes/s)
-system.iobus.trans_dist::ReadReq 16129900 # Transaction distribution
-system.iobus.trans_dist::ReadResp 16129887 # Transaction distribution
-system.iobus.trans_dist::WriteReq 8158 # Transaction distribution
-system.iobus.trans_dist::WriteResp 8158 # Transaction distribution
+system.iobus.throughput 48301509 # Throughput (bytes/s)
+system.iobus.trans_dist::ReadReq 16125521 # Transaction distribution
+system.iobus.trans_dist::ReadResp 16125521 # Transaction distribution
+system.iobus.trans_dist::WriteReq 8157 # Transaction distribution
+system.iobus.trans_dist::WriteResp 8157 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7938 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 518 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1026 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7934 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 516 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1024 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 2382948 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 29893155 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.clcd.dma::total 29893155 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.realview_io.pio 7938 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.timer0.pio 518 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.timer1.pio 1026 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.iocache.cpu_side 29893155 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 32276103 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 2382940 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 29884416 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.clcd.dma::total 29884416 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 32267356 # Packet count per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15876 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1036 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2052 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15868 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1032 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2048 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::total 2390313 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 119572568 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.realview.clcd.dma::total 119572568 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.realview_io.pio 15876 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.timer0.pio 1036 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.timer1.pio 2052 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.iocache.cpu_side 119572568 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::total 121962881 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.data_through_bus 121962881 # Total data (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::total 2390297 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 119537664 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.realview.clcd.dma::total 119537664 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::total 121927961 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.data_through_bus 121927961 # Total data (bytes)
system.iobus.reqLayer0.occupancy 21043000 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer1.occupancy 3974000 # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy 3972000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer2.occupancy 518000 # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy 516000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer3.occupancy 519000 # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy 518000 # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer25.occupancy 14946584000 # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy 14942208000 # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%)
-system.iobus.respLayer0.occupancy 2374790000 # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy 2374783000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.1 # Layer utilization (%)
-system.iobus.respLayer1.occupancy 40962341509 # Layer occupancy (ticks)
+system.iobus.respLayer1.occupancy 40954817261 # Layer occupancy (ticks)
system.iobus.respLayer1.utilization 1.6 # Layer utilization (%)
-system.cpu.branchPred.lookups 14663186 # Number of BP lookups
-system.cpu.branchPred.condPredicted 11751443 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 703165 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 9748962 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 7940354 # Number of BTB hits
+system.cpu.branchPred.lookups 14390442 # Number of BP lookups
+system.cpu.branchPred.condPredicted 11476977 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 705087 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 9493942 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 7662575 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 81.448199 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 1396465 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 72132 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 80.710152 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 1400623 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 72808 # Number of incorrect RAS predictions.
system.cpu.checker.dtb.inst_hits 0 # ITB inst hits
system.cpu.checker.dtb.inst_misses 0 # ITB inst misses
-system.cpu.checker.dtb.read_hits 14987443 # DTB read hits
-system.cpu.checker.dtb.read_misses 7307 # DTB read misses
-system.cpu.checker.dtb.write_hits 11227745 # DTB write hits
+system.cpu.checker.dtb.read_hits 14986742 # DTB read hits
+system.cpu.checker.dtb.read_misses 7308 # DTB read misses
+system.cpu.checker.dtb.write_hits 11227334 # DTB write hits
system.cpu.checker.dtb.write_misses 2189 # DTB write misses
system.cpu.checker.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.checker.dtb.prefetch_faults 178 # Number of TLB faults due to prefetch
system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.checker.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions
-system.cpu.checker.dtb.read_accesses 14994750 # DTB read accesses
-system.cpu.checker.dtb.write_accesses 11229934 # DTB write accesses
+system.cpu.checker.dtb.read_accesses 14994050 # DTB read accesses
+system.cpu.checker.dtb.write_accesses 11229523 # DTB write accesses
system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.checker.dtb.hits 26215188 # DTB hits
-system.cpu.checker.dtb.misses 9496 # DTB misses
-system.cpu.checker.dtb.accesses 26224684 # DTB accesses
-system.cpu.checker.itb.inst_hits 61481774 # ITB inst hits
+system.cpu.checker.dtb.hits 26214076 # DTB hits
+system.cpu.checker.dtb.misses 9497 # DTB misses
+system.cpu.checker.dtb.accesses 26223573 # DTB accesses
+system.cpu.checker.itb.inst_hits 61479547 # ITB inst hits
system.cpu.checker.itb.inst_misses 4471 # ITB inst misses
system.cpu.checker.itb.read_hits 0 # DTB read hits
system.cpu.checker.itb.read_misses 0 # DTB read misses
system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.checker.itb.read_accesses 0 # DTB read accesses
system.cpu.checker.itb.write_accesses 0 # DTB write accesses
-system.cpu.checker.itb.inst_accesses 61486245 # ITB inst accesses
-system.cpu.checker.itb.hits 61481774 # DTB hits
+system.cpu.checker.itb.inst_accesses 61484018 # ITB inst accesses
+system.cpu.checker.itb.hits 61479547 # DTB hits
system.cpu.checker.itb.misses 4471 # DTB misses
-system.cpu.checker.itb.accesses 61486245 # DTB accesses
-system.cpu.checker.numCycles 77885129 # number of cpu cycles simulated
+system.cpu.checker.itb.accesses 61484018 # DTB accesses
+system.cpu.checker.numCycles 77882185 # number of cpu cycles simulated
system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.read_hits 51389107 # DTB read hits
-system.cpu.dtb.read_misses 64168 # DTB read misses
-system.cpu.dtb.write_hits 11699261 # DTB write hits
-system.cpu.dtb.write_misses 15977 # DTB write misses
+system.cpu.dtb.read_hits 51188083 # DTB read hits
+system.cpu.dtb.read_misses 64353 # DTB read misses
+system.cpu.dtb.write_hits 11697459 # DTB write hits
+system.cpu.dtb.write_misses 15788 # DTB write misses
system.cpu.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries 6541 # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults 2439 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults 422 # Number of TLB faults due to prefetch
+system.cpu.dtb.flush_entries 6547 # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults 2446 # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults 415 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults 1367 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses 51453275 # DTB read accesses
-system.cpu.dtb.write_accesses 11715238 # DTB write accesses
+system.cpu.dtb.perms_faults 1347 # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses 51252436 # DTB read accesses
+system.cpu.dtb.write_accesses 11713247 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.dtb.hits 63088368 # DTB hits
-system.cpu.dtb.misses 80145 # DTB misses
-system.cpu.dtb.accesses 63168513 # DTB accesses
-system.cpu.itb.inst_hits 12244686 # ITB inst hits
-system.cpu.itb.inst_misses 11272 # ITB inst misses
+system.cpu.dtb.hits 62885542 # DTB hits
+system.cpu.dtb.misses 80141 # DTB misses
+system.cpu.dtb.accesses 62965683 # DTB accesses
+system.cpu.itb.inst_hits 11520428 # ITB inst hits
+system.cpu.itb.inst_misses 11439 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries 4958 # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_entries 4968 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults 2937 # Number of TLB faults due to permissions restrictions
+system.cpu.itb.perms_faults 2948 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.inst_accesses 12255958 # ITB inst accesses
-system.cpu.itb.hits 12244686 # DTB hits
-system.cpu.itb.misses 11272 # DTB misses
-system.cpu.itb.accesses 12255958 # DTB accesses
-system.cpu.numCycles 475312551 # number of cpu cycles simulated
+system.cpu.itb.inst_accesses 11531867 # ITB inst accesses
+system.cpu.itb.hits 11520428 # DTB hits
+system.cpu.itb.misses 11439 # DTB misses
+system.cpu.itb.accesses 11531867 # DTB accesses
+system.cpu.numCycles 473080437 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 30486466 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 96013812 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 14663186 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 9336819 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 21137847 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 5287329 # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles 121734 # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.BlockedCycles 94652697 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 3821 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 86418 # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles 2672948 # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles 439 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 12241258 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 862361 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes 5349 # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples 152790281 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 0.777398 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.141854 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 29726178 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 90285458 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 14390442 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 9063198 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 20148067 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 4655224 # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles 122776 # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.BlockedCycles 94622822 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 2576 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 87000 # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles 2672031 # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles 423 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 11516980 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 710202 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes 5463 # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples 150589774 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 0.747645 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.103384 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 131667661 86.18% 86.18% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 1302340 0.85% 87.03% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 1711403 1.12% 88.15% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 2491779 1.63% 89.78% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 2204039 1.44% 91.22% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 1109873 0.73% 91.95% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 2734812 1.79% 93.74% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 742969 0.49% 94.22% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 8825405 5.78% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 130457024 86.63% 86.63% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 1304262 0.87% 87.50% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 1711201 1.14% 88.63% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 2296542 1.53% 90.16% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 2101589 1.40% 91.55% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 1109749 0.74% 92.29% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 2556764 1.70% 93.99% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 745428 0.50% 94.48% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 8307215 5.52% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 152790281 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.030850 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.202001 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 32434469 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 96765795 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 19163623 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 968040 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 3458354 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 1955309 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 172027 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 112442167 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 568180 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 3458354 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 34339332 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 38106819 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 52671042 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 18167139 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 6047595 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 106212332 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 20597 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 1004586 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 4065982 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 631 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 110697957 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 485950395 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 485859311 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 91084 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 78390094 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 32307862 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 830633 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 736877 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 12210661 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 20268413 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 13492534 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 1964739 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 2435625 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 97824738 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 1983401 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 124295624 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 165509 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 21636439 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 56320984 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 501000 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 152790281 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.813505 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.528895 # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total 150589774 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.030419 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.190846 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 31488393 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 96724206 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 18371972 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 966714 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 3038489 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 1954982 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 171905 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 107292337 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 568657 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 3038489 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 33240542 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 38064536 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 52670739 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 17528991 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 6046477 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 102291911 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 20574 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 1004468 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 4066422 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents 675 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 106031051 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 466975975 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 466885287 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 90688 # Number of floating rename lookups
+system.cpu.rename.CommittedMaps 78387144 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 27643906 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 830126 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 736572 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 12200321 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 19725062 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 13304379 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 1973962 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 2485771 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 95123211 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 1983556 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 122912009 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 167105 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 18943027 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 47293965 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 501256 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 150589774 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.816204 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.532969 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 108515921 71.02% 71.02% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 13589329 8.89% 79.92% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 7066338 4.62% 84.54% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 5978859 3.91% 88.45% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 12565558 8.22% 96.68% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 2772936 1.81% 98.49% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 1725765 1.13% 99.62% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 449060 0.29% 99.92% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 126515 0.08% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 106863631 70.96% 70.96% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 13450296 8.93% 79.90% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 6941050 4.61% 84.50% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 5871130 3.90% 88.40% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 12365050 8.21% 96.61% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 2809227 1.87% 98.48% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 1693786 1.12% 99.60% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 467660 0.31% 99.92% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 127944 0.08% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 152790281 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 150589774 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 62738 0.71% 0.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 4 0.00% 0.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 62506 0.71% 0.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 5 0.00% 0.71% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 0.71% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.71% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 8365929 94.58% 95.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 416628 4.71% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 8370674 94.63% 95.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 412716 4.67% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass 363666 0.29% 0.29% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 58652585 47.19% 47.48% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 93247 0.08% 47.56% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.56% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.56% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.56% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.56% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.56% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.56% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 21 0.00% 47.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 2 0.00% 47.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 14 0.00% 47.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 2114 0.00% 47.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 14 0.00% 47.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.56% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 52864927 42.53% 90.09% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 12319034 9.91% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass 363666 0.30% 0.30% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 57621227 46.88% 47.18% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 93185 0.08% 47.25% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.25% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.25% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.25% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.25% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.25% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.25% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 21 0.00% 47.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 3 0.00% 47.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 15 0.00% 47.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 2113 0.00% 47.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 15 0.00% 47.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.25% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 52514471 42.73% 89.98% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 12317293 10.02% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 124295624 # Type of FU issued
-system.cpu.iq.rate 0.261503 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 8845299 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.071163 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 410448757 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 121460975 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 86059539 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 23386 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 12542 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 10302 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 132764827 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 12430 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 625909 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 122912009 # Type of FU issued
+system.cpu.iq.rate 0.259812 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 8845901 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.071969 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 405483238 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 116066435 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 85469374 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 23342 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 12510 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 10296 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 131381798 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 12446 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 624501 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 4613851 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 6375 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 30092 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 1760453 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 4071224 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 6576 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 30290 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 1572736 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 34107892 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 916935 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 34107774 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 679836 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 3458354 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 29328857 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 436741 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 100030676 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 203650 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 20268413 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 13492534 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 1410837 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 115234 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 3326 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 30092 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 349264 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 268145 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 617409 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 121630045 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 52076046 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 2665579 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 3038489 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 29300006 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 434231 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 97327801 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 206590 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 19725062 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 13304379 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 1410590 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 113060 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 3500 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 30290 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 351701 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 268555 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 620256 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 120832629 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 51875152 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 2079380 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 222537 # number of nop insts executed
-system.cpu.iew.exec_refs 64287237 # number of memory reference insts executed
-system.cpu.iew.exec_branches 11556571 # Number of branches executed
-system.cpu.iew.exec_stores 12211191 # Number of stores executed
-system.cpu.iew.exec_rate 0.255895 # Inst execution rate
-system.cpu.iew.wb_sent 120479293 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 86069841 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 47268516 # num instructions producing a value
-system.cpu.iew.wb_consumers 88195904 # num instructions consuming a value
+system.cpu.iew.exec_nop 221034 # number of nop insts executed
+system.cpu.iew.exec_refs 64084349 # number of memory reference insts executed
+system.cpu.iew.exec_branches 11474602 # Number of branches executed
+system.cpu.iew.exec_stores 12209197 # Number of stores executed
+system.cpu.iew.exec_rate 0.255417 # Inst execution rate
+system.cpu.iew.wb_sent 119890042 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 85479670 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 47030253 # num instructions producing a value
+system.cpu.iew.wb_consumers 87881540 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 0.181081 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.535949 # average fanout of values written-back
+system.cpu.iew.wb_rate 0.180687 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.535155 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 21374007 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 1482401 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 533608 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 149331927 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.520650 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.508241 # Number of insts commited each cycle
+system.cpu.commit.commitSquashedInsts 18673473 # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls 1482300 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts 535675 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 147551285 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.526914 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.516633 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 121887208 81.62% 81.62% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 13290460 8.90% 90.52% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 3923979 2.63% 93.15% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 2130804 1.43% 94.58% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 1950357 1.31% 95.88% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 968781 0.65% 96.53% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 1543061 1.03% 97.56% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 783043 0.52% 98.09% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 2854234 1.91% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 120109216 81.40% 81.40% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 13315885 9.02% 90.43% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 3896468 2.64% 93.07% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 2118661 1.44% 94.50% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 1945134 1.32% 95.82% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 977268 0.66% 96.48% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 1587082 1.08% 97.56% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 719968 0.49% 98.05% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 2881603 1.95% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 149331927 # Number of insts commited each cycle
-system.cpu.commit.committedInsts 60458154 # Number of instructions committed
-system.cpu.commit.committedOps 77749702 # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total 147551285 # Number of insts commited each cycle
+system.cpu.commit.committedInsts 60455941 # Number of instructions committed
+system.cpu.commit.committedOps 77746772 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.refs 27386643 # Number of memory references committed
-system.cpu.commit.loads 15654562 # Number of loads committed
-system.cpu.commit.membars 403601 # Number of memory barriers committed
-system.cpu.commit.branches 9961356 # Number of branches committed
+system.cpu.commit.refs 27385481 # Number of memory references committed
+system.cpu.commit.loads 15653838 # Number of loads committed
+system.cpu.commit.membars 403568 # Number of memory barriers committed
+system.cpu.commit.branches 9961054 # Number of branches committed
system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 68854920 # Number of committed integer instructions.
-system.cpu.commit.function_calls 991265 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 2854234 # number cycles where commit BW limit reached
+system.cpu.commit.int_insts 68852229 # Number of committed integer instructions.
+system.cpu.commit.function_calls 991205 # Number of function calls committed.
+system.cpu.commit.bw_lim_events 2881603 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 243752783 # The number of ROB reads
-system.cpu.rob.rob_writes 201807644 # The number of ROB writes
-system.cpu.timesIdled 1781061 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 322522270 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles 4593269077 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts 60307773 # Number of Instructions Simulated
-system.cpu.committedOps 77599321 # Number of Ops (including micro ops) Simulated
-system.cpu.committedInsts_total 60307773 # Number of Instructions Simulated
-system.cpu.cpi 7.881448 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 7.881448 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.126880 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.126880 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 550637147 # number of integer regfile reads
-system.cpu.int_regfile_writes 88566596 # number of integer regfile writes
-system.cpu.fp_regfile_reads 8370 # number of floating regfile reads
-system.cpu.fp_regfile_writes 2906 # number of floating regfile writes
-system.cpu.misc_regfile_reads 30124157 # number of misc regfile reads
-system.cpu.misc_regfile_writes 831896 # number of misc regfile writes
-system.cpu.toL2Bus.throughput 58663468 # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq 2657447 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 2657446 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteReq 763336 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteResp 763336 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback 607541 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq 2966 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::SCUpgradeReq 17 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp 2983 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 245999 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 245999 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1961368 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 5795761 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma 30461 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma 126683 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count 7914273 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 62726656 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 85494329 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma 41328 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma 209684 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size 148471997 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus 148471997 # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus 200728 # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy 3128200875 # Layer occupancy (ticks)
+system.cpu.rob.rob_reads 239241509 # The number of ROB reads
+system.cpu.rob.rob_writes 195965670 # The number of ROB writes
+system.cpu.timesIdled 1778644 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 322490663 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles 4575455632 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts 60305560 # Number of Instructions Simulated
+system.cpu.committedOps 77596391 # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total 60305560 # Number of Instructions Simulated
+system.cpu.cpi 7.844723 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 7.844723 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.127474 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.127474 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 547265504 # number of integer regfile reads
+system.cpu.int_regfile_writes 87536110 # number of integer regfile writes
+system.cpu.fp_regfile_reads 8349 # number of floating regfile reads
+system.cpu.fp_regfile_writes 2916 # number of floating regfile writes
+system.cpu.misc_regfile_reads 30123194 # number of misc regfile reads
+system.cpu.misc_regfile_writes 831835 # number of misc regfile writes
+system.cpu.toL2Bus.throughput 58892076 # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq 2657368 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 2657367 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteReq 763332 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteResp 763332 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 607864 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq 2955 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::SCUpgradeReq 11 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp 2966 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 246095 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 246095 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1959479 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5796858 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 30970 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 126903 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 7914210 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 62665920 # Cumulative packet size per connected master and slave (bytes)
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+system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 42108 # Cumulative packet size per connected master and slave (bytes)
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
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+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024355 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047482 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047482 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000044 # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025684 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.025684 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025684 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.025684 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12827.329206 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12827.329206 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42620.110106 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42620.110106 # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11911.365878 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11911.365878 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13272.545455 # average StoreCondReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13272.545455 # average StoreCondReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24509.154272 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 24509.154272 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24509.154272 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 24509.154272 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.iocache.tags.replacements 0 # number of replacements
-system.iocache.tags.tagsinuse 0 # Cycle average of tags in use
-system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks.
-system.iocache.tags.avg_refs nan # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.iocache.tags.replacements 0 # number of replacements
+system.iocache.tags.tagsinuse 0 # Cycle average of tags in use
+system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
+system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks.
+system.iocache.tags.avg_refs nan # Average number of references to valid blocks.
+system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1486035968259 # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 1486035968259 # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1486035968259 # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 1486035968259 # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1424415639261 # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 1424415639261 # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1424415639261 # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 1424415639261 # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.kern.inst.arm 0 # number of arm instructions executed
-system.cpu.kern.inst.quiesce 83045 # number of quiesce instructions executed
+system.cpu.kern.inst.quiesce 83035 # number of quiesce instructions executed
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 1.114023 # Number of seconds simulated
-sim_ticks 1114022852000 # Number of ticks simulated
-final_tick 1114022852000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 1.104038 # Number of seconds simulated
+sim_ticks 1104038330000 # Number of ticks simulated
+final_tick 1104038330000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 79652 # Simulator instruction rate (inst/s)
-host_op_rate 102538 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1440387686 # Simulator tick rate (ticks/s)
-host_mem_usage 404604 # Number of bytes of host memory used
-host_seconds 773.42 # Real time elapsed on the host
-sim_insts 61604368 # Number of instructions simulated
-sim_ops 79304455 # Number of ops (including micro ops) simulated
+host_inst_rate 80920 # Simulator instruction rate (inst/s)
+host_op_rate 104171 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1450259542 # Simulator tick rate (ticks/s)
+host_mem_usage 402880 # Number of bytes of host memory used
+host_seconds 761.27 # Real time elapsed on the host
+sim_insts 61602211 # Number of instructions simulated
+sim_ops 79302243 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::realview.clcd 48758784 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.dtb.walker 1024 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst 409408 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 4367220 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.dtb.walker 768 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst 410368 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 4366772 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker 896 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 406208 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 5247536 # Number of bytes read from this memory
-system.physmem.bytes_read::total 59191204 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 409408 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 406208 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 815616 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 4263872 # Number of bytes written to this memory
+system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst 405824 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 5250416 # Number of bytes read from this memory
+system.physmem.bytes_read::total 59194084 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 410368 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 405824 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 816192 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 4267200 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory
-system.physmem.bytes_written::total 7291216 # Number of bytes written to this memory
+system.physmem.bytes_written::total 7294544 # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd 6094848 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.dtb.walker 16 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst 6397 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 68310 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.dtb.walker 12 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst 6412 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 68303 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker 14 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 6347 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 82019 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 6257953 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 66623 # Number of write requests responded to by this memory
+system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst 6341 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 82064 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 6257998 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 66675 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 823459 # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd 43768208 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.dtb.walker 919 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker 115 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst 367504 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 3920225 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker 804 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 364632 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 4710438 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 53132845 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 367504 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 364632 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 732136 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 3827455 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data 15260 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1.data 2702228 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 6544943 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 3827455 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd 43768208 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker 919 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker 115 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 367504 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 3935485 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker 804 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 364632 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 7412667 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 59677788 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 6257953 # Total number of read requests seen
-system.physmem.writeReqs 823459 # Total number of write requests seen
-system.physmem.cpureqs 242171 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 400508992 # Total number of bytes read from memory
-system.physmem.bytesWritten 52701376 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 59191204 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 7291216 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 127 # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite 12548 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 391121 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 391049 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 391102 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 391240 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 391825 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 391535 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 391243 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 391065 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 391488 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 391482 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 390728 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 390299 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 390904 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 390678 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 391045 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 391022 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 49919 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 49928 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2 51967 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 51963 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 52290 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5 51965 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6 51872 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 51692 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 51908 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 51949 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 51308 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11 51011 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12 51439 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13 51134 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14 51585 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15 51529 # Track writes on a per bank basis
+system.physmem.num_writes::total 823511 # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd 44164032 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.dtb.walker 696 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker 174 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst 371697 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 3955272 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker 812 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.itb.walker 58 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 367581 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 4755646 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 53615968 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 371697 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 367581 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 739279 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 3865083 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data 15398 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1.data 2726666 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 6607147 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 3865083 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd 44164032 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker 696 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker 174 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 371697 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 3970670 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker 812 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.itb.walker 58 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 367581 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 7482313 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 60223116 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 6257998 # Total number of read requests accepted by DRAM controller
+system.physmem.writeReqs 823511 # Total number of write requests accepted by DRAM controller
+system.physmem.readBursts 6257998 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
+system.physmem.writeBursts 823511 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
+system.physmem.bytesRead 400511872 # Total number of bytes read from memory
+system.physmem.bytesWritten 52704704 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 59194084 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 7294544 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 4191 # Number of DRAM read bursts serviced by write Q
+system.physmem.neitherReadNorWrite 12574 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 391107 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 391051 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 391031 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 390511 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 391821 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 391470 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 391242 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 390250 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 391441 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 391418 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 390570 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 389084 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 390982 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 390746 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 391146 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 389937 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 7175 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 7210 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 7320 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 7294 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 7815 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 7419 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 7389 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 7204 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 7511 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 7529 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 6860 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 6626 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 7171 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 6832 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 7294 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 7205 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
-system.physmem.numWrRetry 32580 # Number of times wr buffer was full causing retry
-system.physmem.totGap 1114021721000 # Total gap between requests
+system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
+system.physmem.totGap 1104037196000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 105 # Categorize read packet sizes
system.physmem.readPktSize::3 6094848 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 163000 # Categorize read packet sizes
+system.physmem.readPktSize::6 163045 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
system.physmem.writePktSize::2 756836 # Categorize write packet sizes
system.physmem.writePktSize::3 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
-system.physmem.writePktSize::6 66623 # Categorize write packet sizes
-system.physmem.rdQLenPdf::0 508306 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 436400 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 409055 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 1494610 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 1111724 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 1109849 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 1096192 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 9300 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 6855 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 11963 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 16960 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11 11777 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12 8816 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13 8727 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14 12128 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15 5024 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16 119 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17 13 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18 5 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19 3 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 66675 # Categorize write packet sizes
+system.physmem.rdQLenPdf::0 510579 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 438231 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 410611 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 1497375 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 1129368 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 1114937 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 1085131 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 10318 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 7846 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 12945 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10 17928 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11 12334 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12 1651 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13 1534 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14 1452 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15 1390 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16 94 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17 72 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18 6 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19 4 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 2907 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 2970 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 3010 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 3064 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 3094 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 3130 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6 3162 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 3189 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8 3206 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9 35803 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10 35803 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11 35803 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12 35803 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13 35802 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14 35802 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 35802 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 35802 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 35802 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 35802 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 35802 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 35802 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 35802 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 35802 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 32896 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 32833 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 32793 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 32739 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 32709 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 32673 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 32641 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 32614 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 32597 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 38811 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 11677.106800 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 598.829081 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 25969.144286 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::64-95 10478 27.00% 27.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-159 4256 10.97% 37.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::192-223 2718 7.00% 44.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-287 2024 5.22% 50.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::320-351 1422 3.66% 53.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-415 1213 3.13% 56.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::448-479 997 2.57% 59.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-543 905 2.33% 61.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::576-607 654 1.69% 63.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-671 573 1.48% 65.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::704-735 456 1.17% 66.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-799 470 1.21% 67.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::832-863 308 0.79% 68.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-927 261 0.67% 68.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::960-991 192 0.49% 69.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1055 284 0.73% 70.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1088-1119 136 0.35% 70.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1152-1183 144 0.37% 70.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1216-1247 111 0.29% 71.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1280-1311 147 0.38% 71.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1344-1375 83 0.21% 71.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1408-1439 412 1.06% 72.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1472-1503 1956 5.04% 77.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1536-1567 510 1.31% 79.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1600-1631 94 0.24% 79.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1664-1695 178 0.46% 79.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1728-1759 53 0.14% 79.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1792-1823 122 0.31% 80.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1856-1887 38 0.10% 80.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1920-1951 83 0.21% 80.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1984-2015 40 0.10% 80.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2048-2079 68 0.18% 80.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2112-2143 23 0.06% 80.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2176-2207 47 0.12% 81.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2240-2271 17 0.04% 81.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2304-2335 43 0.11% 81.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2368-2399 13 0.03% 81.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2432-2463 28 0.07% 81.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2496-2527 13 0.03% 81.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2560-2591 25 0.06% 81.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2624-2655 10 0.03% 81.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2688-2719 18 0.05% 81.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2752-2783 7 0.02% 81.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2816-2847 19 0.05% 81.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2880-2911 4 0.01% 81.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2944-2975 20 0.05% 81.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3008-3039 6 0.02% 81.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3072-3103 20 0.05% 81.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3136-3167 6 0.02% 81.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3200-3231 9 0.02% 81.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3264-3295 7 0.02% 81.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3328-3359 18 0.05% 81.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3392-3423 3 0.01% 81.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3456-3487 11 0.03% 81.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3520-3551 6 0.02% 81.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3584-3615 12 0.03% 81.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3648-3679 6 0.02% 81.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3712-3743 2 0.01% 81.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3776-3807 6 0.02% 81.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3840-3871 7 0.02% 81.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3904-3935 5 0.01% 81.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3968-3999 10 0.03% 81.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4032-4063 2 0.01% 81.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4096-4127 40 0.10% 82.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4160-4191 1 0.00% 82.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4224-4255 7 0.02% 82.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4288-4319 2 0.01% 82.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4352-4383 5 0.01% 82.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4416-4447 3 0.01% 82.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4480-4511 4 0.01% 82.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4544-4575 3 0.01% 82.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4608-4639 9 0.02% 82.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4672-4703 1 0.00% 82.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4736-4767 2 0.01% 82.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4800-4831 2 0.01% 82.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4864-4895 2 0.01% 82.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4928-4959 2 0.01% 82.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4992-5023 5 0.01% 82.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5056-5087 1 0.00% 82.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5120-5151 7 0.02% 82.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5184-5215 4 0.01% 82.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5248-5279 2 0.01% 82.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5312-5343 2 0.01% 82.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5376-5407 2 0.01% 82.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5440-5471 2 0.01% 82.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5504-5535 2 0.01% 82.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5568-5599 3 0.01% 82.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5632-5663 3 0.01% 82.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5696-5727 2 0.01% 82.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5760-5791 1 0.00% 82.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5824-5855 1 0.00% 82.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5888-5919 2 0.01% 82.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5952-5983 2 0.01% 82.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6016-6047 3 0.01% 82.29% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6080-6111 2 0.01% 82.29% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6144-6175 5 0.01% 82.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6208-6239 3 0.01% 82.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6272-6303 4 0.01% 82.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6336-6367 2 0.01% 82.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6400-6431 4 0.01% 82.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6464-6495 1 0.00% 82.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6528-6559 1 0.00% 82.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6592-6623 1 0.00% 82.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6656-6687 2 0.01% 82.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6720-6751 2 0.01% 82.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6784-6815 14 0.04% 82.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6848-6879 3 0.01% 82.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6912-6943 3 0.01% 82.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6976-7007 2 0.01% 82.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7040-7071 2 0.01% 82.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7168-7199 3 0.01% 82.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7232-7263 1 0.00% 82.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7296-7327 1 0.00% 82.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7424-7455 6 0.02% 82.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7488-7519 1 0.00% 82.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7552-7583 4 0.01% 82.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7680-7711 6 0.02% 82.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7744-7775 2 0.01% 82.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7808-7839 2 0.01% 82.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7872-7903 2 0.01% 82.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7936-7967 7 0.02% 82.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8000-8031 1 0.00% 82.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8064-8095 7 0.02% 82.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8128-8159 4 0.01% 82.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8192-8223 316 0.81% 83.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8256-8287 1 0.00% 83.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8960-8991 2 0.01% 83.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9216-9247 5 0.01% 83.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9344-9375 1 0.00% 83.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9472-9503 1 0.00% 83.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9664-9695 1 0.00% 83.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9984-10015 2 0.01% 83.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10240-10271 15 0.04% 83.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10368-10399 1 0.00% 83.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10496-10527 1 0.00% 83.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10752-10783 1 0.00% 83.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11008-11039 3 0.01% 83.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11264-11295 3 0.01% 83.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11520-11551 1 0.00% 83.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11776-11807 2 0.01% 83.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12032-12063 1 0.00% 83.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12288-12319 5 0.01% 83.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12544-12575 1 0.00% 83.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12800-12831 2 0.01% 83.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12864-12895 1 0.00% 83.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13056-13087 1 0.00% 83.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13312-13343 2 0.01% 83.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13504-13535 1 0.00% 83.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13568-13599 1 0.00% 83.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14336-14367 4 0.01% 83.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15104-15135 3 0.01% 83.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15360-15391 1 0.00% 83.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15424-15455 1 0.00% 83.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15744-15775 1 0.00% 83.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16640-16671 3 0.01% 83.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16896-16927 1 0.00% 83.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::17152-17183 1 0.00% 83.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::17216-17247 1 0.00% 83.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::17344-17375 1 0.00% 83.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::17408-17439 2 0.01% 83.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::17664-17695 2 0.01% 83.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::17728-17759 1 0.00% 83.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::17984-18015 1 0.00% 83.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::18176-18207 3 0.01% 83.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::18432-18463 1 0.00% 83.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::18560-18591 1 0.00% 83.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::18688-18719 2 0.01% 83.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::18944-18975 2 0.01% 83.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::19200-19231 1 0.00% 83.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::19456-19487 4 0.01% 83.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::19584-19615 1 0.00% 83.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::19968-19999 3 0.01% 83.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::20096-20127 1 0.00% 83.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::20224-20255 1 0.00% 83.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::20480-20511 12 0.03% 83.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::20736-20767 1 0.00% 83.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::21248-21279 1 0.00% 83.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::21504-21535 2 0.01% 83.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::21760-21791 1 0.00% 83.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::21952-21983 2 0.01% 83.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::22016-22047 1 0.00% 83.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::22528-22559 4 0.01% 83.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::22656-22687 1 0.00% 83.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::22784-22815 3 0.01% 83.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::23296-23327 1 0.00% 83.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::23552-23583 1 0.00% 83.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::24000-24031 1 0.00% 83.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::24064-24095 2 0.01% 83.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::24192-24223 1 0.00% 83.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::24320-24351 1 0.00% 83.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::24576-24607 2 0.01% 83.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::24704-24735 2 0.01% 83.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::25344-25375 1 0.00% 83.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::25408-25439 1 0.00% 83.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::25600-25631 2 0.01% 83.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::25856-25887 1 0.00% 83.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::26048-26079 1 0.00% 83.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::26112-26143 4 0.01% 83.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::26304-26335 1 0.00% 83.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::26368-26399 1 0.00% 83.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::26624-26655 1 0.00% 83.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::27136-27167 3 0.01% 83.75% # Bytes accessed per row activation
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-system.physmem.bytesPerActivate::27456-27487 1 0.00% 83.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::27648-27679 2 0.01% 83.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::27904-27935 1 0.00% 83.76% # Bytes accessed per row activation
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-system.physmem.bytesPerActivate::28928-28959 1 0.00% 83.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::29440-29471 2 0.01% 83.78% # Bytes accessed per row activation
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-system.physmem.bytesPerActivate::30720-30751 3 0.01% 83.79% # Bytes accessed per row activation
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-system.physmem.bytesPerActivate::31040-31071 1 0.00% 83.80% # Bytes accessed per row activation
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-system.physmem.bytesPerActivate::65152-65183 6 0.02% 84.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::65280-65311 6 0.02% 84.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::65408-65439 1 0.00% 84.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::65536-65567 5797 14.94% 99.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::129920-129951 1 0.00% 99.11% # Bytes accessed per row activation
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-system.physmem.bytesPerActivate::130944-130975 1 0.00% 99.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::131072-131103 326 0.84% 99.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::131200-131231 1 0.00% 99.96% # Bytes accessed per row activation
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-system.physmem.bytesPerActivate::total 38811 # Bytes accessed per row activation
-system.physmem.totQLat 182252409750 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 221627859750 # Sum of mem lat for all requests
-system.physmem.totBusLat 31289130000 # Total cycles spent in databus access
-system.physmem.totBankLat 8086320000 # Total cycles spent in bank access
-system.physmem.avgQLat 29123.92 # Average queueing delay per request
-system.physmem.avgBankLat 1292.19 # Average bank access latency per request
+system.physmem.wrQLenPdf::0 5005 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::24 2 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples 35262 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 11560.822642 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 608.575977 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 24356.197009 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::64-79 8749 24.81% 24.81% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-143 4356 12.35% 37.16% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::192-207 2652 7.52% 44.69% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-271 2010 5.70% 50.39% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::384-399 1214 3.44% 57.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::448-463 927 2.63% 60.53% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-527 1120 3.18% 63.71% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::576-591 659 1.87% 65.58% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-655 617 1.75% 67.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::704-719 450 1.28% 68.60% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-783 454 1.29% 69.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::832-847 302 0.86% 70.75% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-911 302 0.86% 71.60% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::960-975 179 0.51% 72.11% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1039 219 0.62% 72.73% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1088-1103 133 0.38% 73.11% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1152-1167 156 0.44% 73.55% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1216-1231 97 0.28% 73.83% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1280-1295 134 0.38% 74.21% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1344-1359 73 0.21% 74.41% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1408-1423 395 1.12% 75.53% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1472-1487 262 0.74% 76.28% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1536-1551 538 1.53% 77.80% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1600-1615 109 0.31% 78.11% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1664-1679 178 0.50% 78.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1728-1743 51 0.14% 78.76% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1792-1807 128 0.36% 79.12% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1856-1871 49 0.14% 79.26% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1920-1935 68 0.19% 79.46% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1984-1999 39 0.11% 79.57% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2048-2063 74 0.21% 79.78% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2112-2127 17 0.05% 79.83% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2176-2191 56 0.16% 79.98% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2240-2255 22 0.06% 80.05% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2304-2319 30 0.09% 80.13% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::2432-2447 29 0.08% 80.25% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2496-2511 10 0.03% 80.28% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2560-2575 19 0.05% 80.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2624-2639 9 0.03% 80.36% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2688-2703 17 0.05% 80.41% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2752-2767 7 0.02% 80.43% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2816-2831 14 0.04% 80.47% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2880-2895 6 0.02% 80.48% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2944-2959 10 0.03% 80.51% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3008-3023 4 0.01% 80.52% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3072-3087 17 0.05% 80.57% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3136-3151 3 0.01% 80.58% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3200-3215 15 0.04% 80.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3264-3279 4 0.01% 80.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3328-3343 7 0.02% 80.65% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3392-3407 9 0.03% 80.68% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3456-3471 11 0.03% 80.71% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3520-3535 3 0.01% 80.72% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3584-3599 7 0.02% 80.74% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3648-3663 3 0.01% 80.75% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3712-3727 11 0.03% 80.78% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3776-3791 3 0.01% 80.79% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3840-3855 4 0.01% 80.80% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3904-3919 5 0.01% 80.81% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::4160-4175 4 0.01% 80.95% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::4864-4879 4 0.01% 81.06% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::total 35262 # Bytes accessed per row activation
+system.physmem.totQLat 121597245250 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 160506894000 # Sum of mem lat for all requests
+system.physmem.totBusLat 31269035000 # Total cycles spent in databus access
+system.physmem.totBankLat 7640613750 # Total cycles spent in bank access
+system.physmem.avgQLat 19443.72 # Average queueing delay per request
+system.physmem.avgBankLat 1221.75 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 35416.11 # Average memory access latency
-system.physmem.avgRdBW 359.52 # Average achieved read bandwidth in MB/s
-system.physmem.avgWrBW 47.31 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 53.13 # Average consumed read bandwidth in MB/s
-system.physmem.avgConsumedWrBW 6.54 # Average consumed write bandwidth in MB/s
+system.physmem.avgMemAccLat 25665.47 # Average memory access latency
+system.physmem.avgRdBW 362.77 # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW 47.74 # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW 53.62 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedWrBW 6.61 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
-system.physmem.busUtil 3.18 # Data bus utilization in percentage
-system.physmem.avgRdQLen 0.20 # Average read queue length over time
-system.physmem.avgWrQLen 11.52 # Average write queue length over time
-system.physmem.readRowHits 6237911 # Number of row buffer hits during reads
-system.physmem.writeRowHits 804550 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 99.68 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 97.70 # Row buffer hit rate for writes
-system.physmem.avgGap 157316.33 # Average gap between requests
+system.physmem.busUtil 3.21 # Data bus utilization in percentage
+system.physmem.avgRdQLen 0.15 # Average read queue length over time
+system.physmem.avgWrQLen 12.74 # Average write queue length over time
+system.physmem.readRowHits 6235456 # Number of row buffer hits during reads
+system.physmem.writeRowHits 98940 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 99.71 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 12.01 # Row buffer hit rate for writes
+system.physmem.avgGap 155904.23 # Average gap between requests
system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst 384 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst 6 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 7 # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu0.inst 57 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::cpu1.inst 345 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total 402 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu0.inst 57 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu1.inst 345 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total 402 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu0.inst 57 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu1.inst 345 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total 402 # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput 61845817 # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq 7306747 # Transaction distribution
-system.membus.trans_dist::ReadResp 7306747 # Transaction distribution
-system.membus.trans_dist::WriteReq 767893 # Transaction distribution
-system.membus.trans_dist::WriteResp 767893 # Transaction distribution
-system.membus.trans_dist::Writeback 66623 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 33809 # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq 17757 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 12548 # Transaction distribution
-system.membus.trans_dist::ReadExReq 138043 # Transaction distribution
-system.membus.trans_dist::ReadExResp 137663 # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382510 # Packet count per connected master and slave (bytes)
+system.realview.nvmem.bw_read::cpu0.inst 58 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::cpu1.inst 348 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total 406 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu0.inst 58 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu1.inst 348 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total 406 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu0.inst 58 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu1.inst 348 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total 406 # Total bandwidth to/from this memory (bytes/s)
+system.membus.throughput 62410733 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 7306749 # Transaction distribution
+system.membus.trans_dist::ReadResp 7306749 # Transaction distribution
+system.membus.trans_dist::WriteReq 767894 # Transaction distribution
+system.membus.trans_dist::WriteResp 767894 # Transaction distribution
+system.membus.trans_dist::Writeback 66675 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 33869 # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq 17715 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 12574 # Transaction distribution
+system.membus.trans_dist::ReadExReq 138085 # Transaction distribution
+system.membus.trans_dist::ReadExResp 137703 # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382522 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 14 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1970999 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 11650 # Packet count per connected master and slave (bytes)
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system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes)
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-system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000469 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015959 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036657 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000451 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010581 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.030436 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total 0.017618 # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.793661 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.837317 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total 0.811564 # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.751773 # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.735915 # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.745403 # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.567096 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.567450 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total 0.567290 # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000724 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000469 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015959 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data 0.244583 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000451 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010581 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data 0.244687 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total 0.098671 # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000724 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000469 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015959 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data 0.244583 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000451 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010581 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data 0.244687 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total 0.098671 # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 84656.250000 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 52875 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 60670.132250 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 61029.875296 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 103785.714286 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 64637.823054 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 65172.040849 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 62905.227161 # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10022.604692 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10028.486386 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10025.093278 # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10037.941824 # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10042.858852 # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10039.891841 # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 54677.242037 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 59038.145621 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 57070.582409 # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 84656.250000 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 52875 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 60670.132250 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 55256.139729 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 103785.714286 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 64637.823054 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 59496.725662 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 57958.733083 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 84656.250000 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 52875 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 60670.132250 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 55256.139729 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 103785.714286 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 64637.823054 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 59496.725662 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 57958.733083 # average overall mshr miss latency
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data 171096604501 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total 184511569236 # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000549 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000708 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.016019 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036682 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000453 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000203 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010596 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.030402 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total 0.017650 # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.793822 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.835801 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total 0.811091 # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.758084 # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.750442 # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.755000 # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.567102 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.567702 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total 0.567431 # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000549 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000708 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst 0.016019 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data 0.244763 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000453 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000203 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010596 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data 0.244675 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total 0.098854 # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000549 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000708 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst 0.016019 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data 0.244763 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000453 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000203 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010596 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data 0.244675 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total 0.098854 # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 67125 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 60666.666667 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 60320.259100 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 61034.531536 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 76732.142857 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 76250 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 64543.088399 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 63333.601415 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 62313.837775 # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10026.084436 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10043.826811 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10033.605358 # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10042.261792 # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10017.551561 # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 54626.471718 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 59325.717217 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 57205.767923 # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 67125 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 60666.666667 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 60320.259100 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 55210.093446 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 76732.142857 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 76250 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 64543.088399 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 59625.117816 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 57983.064782 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 67125 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 60666.666667 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 60320.259100 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 55210.093446 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 76732.142857 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 76250 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 64543.088399 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 59625.117816 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 57983.064782 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
-system.toL2Bus.throughput 135543504 # Throughput (bytes/s)
-system.toL2Bus.trans_dist::ReadReq 2708876 # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp 2708875 # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq 767893 # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp 767893 # Transaction distribution
-system.toL2Bus.trans_dist::Writeback 581377 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq 33332 # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq 18117 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp 51449 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 258856 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 258856 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 787342 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 1073883 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma 13468 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma 55968 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.icache.mem_side 1192763 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side 4801194 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma 14594 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma 72477 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count 8011689 # Packet count per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 25176640 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 34854805 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma 17052 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma 88352 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side 38149824 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side 47763808 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma 20036 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma 124096 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size 146194613 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.data_through_bus 146194613 # Total data (bytes)
-system.toL2Bus.snoop_data_through_bus 4803948 # Total snoop data (bytes)
-system.toL2Bus.reqLayer0.occupancy 4894718895 # Layer occupancy (ticks)
+system.toL2Bus.throughput 136659470 # Throughput (bytes/s)
+system.toL2Bus.trans_dist::ReadReq 2706207 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 2706206 # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq 767894 # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp 767894 # Transaction distribution
+system.toL2Bus.trans_dist::Writeback 581263 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 33352 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq 18058 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 51410 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 258939 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 258939 # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 786305 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1073575 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 13268 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 55413 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1190023 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 4801593 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side 14394 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 72130 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 8006701 # Packet count per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 25142464 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 34843867 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 16960 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 87488 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 38062080 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 47776006 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side 19732 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 123572 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size::total 146072169 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.data_through_bus 146072169 # Total data (bytes)
+system.toL2Bus.snoop_data_through_bus 4805124 # Total snoop data (bytes)
+system.toL2Bus.reqLayer0.occupancy 4892877936 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy 1774755611 # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy 1772488367 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy 1516721983 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy 1516304011 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy 9224710 # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy 9043467 # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy 34035182 # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy 33687702 # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer4.occupancy 2687171756 # Layer occupancy (ticks)
+system.toL2Bus.respLayer4.occupancy 2681029210 # Layer occupancy (ticks)
system.toL2Bus.respLayer4.utilization 0.2 # Layer utilization (%)
-system.toL2Bus.respLayer5.occupancy 3246383092 # Layer occupancy (ticks)
+system.toL2Bus.respLayer5.occupancy 3243394678 # Layer occupancy (ticks)
system.toL2Bus.respLayer5.utilization 0.3 # Layer utilization (%)
-system.toL2Bus.respLayer6.occupancy 9605952 # Layer occupancy (ticks)
+system.toL2Bus.respLayer6.occupancy 9483701 # Layer occupancy (ticks)
system.toL2Bus.respLayer6.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer7.occupancy 41732428 # Layer occupancy (ticks)
+system.toL2Bus.respLayer7.occupancy 41522672 # Layer occupancy (ticks)
system.toL2Bus.respLayer7.utilization 0.0 # Layer utilization (%)
-system.iobus.throughput 45913386 # Throughput (bytes/s)
-system.iobus.trans_dist::ReadReq 7278157 # Transaction distribution
-system.iobus.trans_dist::ReadResp 7278157 # Transaction distribution
-system.iobus.trans_dist::WriteReq 7946 # Transaction distribution
-system.iobus.trans_dist::WriteResp 7946 # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30448 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8024 # Packet count per connected master and slave (bytes)
+system.iobus.throughput 46328621 # Throughput (bytes/s)
+system.iobus.trans_dist::ReadReq 7278159 # Transaction distribution
+system.iobus.trans_dist::ReadResp 7278159 # Transaction distribution
+system.iobus.trans_dist::WriteReq 7950 # Transaction distribution
+system.iobus.trans_dist::WriteResp 7950 # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30460 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8026 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 726 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 724 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 494 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 2382510 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 2382522 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 12189696 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.clcd.dma::total 12189696 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.uart.pio 30448 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.realview_io.pio 8024 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.timer1.pio 726 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.kmi1.pio 494 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.iocache.cpu_side 12189696 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 14572206 # Packet count per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 40166 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 16048 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count::total 14572218 # Packet count per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 40178 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 16052 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 1452 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 1448 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 271 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::total 2389777 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::total 2389789 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 48758784 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.realview.clcd.dma::total 48758784 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.uart.pio 40166 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.realview_io.pio 16048 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.timer1.pio 1452 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.kmi1.pio 271 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.iocache.cpu_side 48758784 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::total 51148561 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.data_through_bus 51148561 # Total data (bytes)
-system.iobus.reqLayer0.occupancy 21350000 # Layer occupancy (ticks)
+system.iobus.tot_pkt_size::total 51148573 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.data_through_bus 51148573 # Total data (bytes)
+system.iobus.reqLayer0.occupancy 21360000 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer1.occupancy 4018000 # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy 4019000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.occupancy 34000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer3.occupancy 369000 # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy 368000 # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer25.occupancy 6094848000 # Layer occupancy (ticks)
-system.iobus.reqLayer25.utilization 0.5 # Layer utilization (%)
-system.iobus.respLayer0.occupancy 2374564000 # Layer occupancy (ticks)
+system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%)
+system.iobus.respLayer0.occupancy 2374572000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.2 # Layer utilization (%)
-system.iobus.respLayer1.occupancy 16693526268 # Layer occupancy (ticks)
+system.iobus.respLayer1.occupancy 16699589511 # Layer occupancy (ticks)
system.iobus.respLayer1.utilization 1.5 # Layer utilization (%)
-system.cpu0.branchPred.lookups 6007013 # Number of BP lookups
-system.cpu0.branchPred.condPredicted 4581243 # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect 296095 # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups 3784394 # Number of BTB lookups
-system.cpu0.branchPred.BTBHits 2916091 # Number of BTB hits
+system.cpu0.branchPred.lookups 6002321 # Number of BP lookups
+system.cpu0.branchPred.condPredicted 4576737 # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect 295742 # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups 3785758 # Number of BTB lookups
+system.cpu0.branchPred.BTBHits 2914394 # Number of BTB hits
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct 77.055692 # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS 673819 # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect 28621 # Number of incorrect RAS predictions.
+system.cpu0.branchPred.BTBHitPct 76.983104 # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS 673290 # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect 28745 # Number of incorrect RAS predictions.
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
-system.cpu0.dtb.read_hits 8911671 # DTB read hits
-system.cpu0.dtb.read_misses 28579 # DTB read misses
-system.cpu0.dtb.write_hits 5140325 # DTB write hits
-system.cpu0.dtb.write_misses 5457 # DTB write misses
+system.cpu0.dtb.read_hits 8907919 # DTB read hits
+system.cpu0.dtb.read_misses 28331 # DTB read misses
+system.cpu0.dtb.write_hits 5140728 # DTB write hits
+system.cpu0.dtb.write_misses 5464 # DTB write misses
system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries 1825 # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults 935 # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults 297 # Number of TLB faults due to prefetch
+system.cpu0.dtb.flush_entries 1828 # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults 958 # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults 306 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults 555 # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses 8940250 # DTB read accesses
-system.cpu0.dtb.write_accesses 5145782 # DTB write accesses
+system.cpu0.dtb.perms_faults 551 # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses 8936250 # DTB read accesses
+system.cpu0.dtb.write_accesses 5146192 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu0.dtb.hits 14051996 # DTB hits
-system.cpu0.dtb.misses 34036 # DTB misses
-system.cpu0.dtb.accesses 14086032 # DTB accesses
-system.cpu0.itb.inst_hits 4224524 # ITB inst hits
-system.cpu0.itb.inst_misses 5106 # ITB inst misses
+system.cpu0.dtb.hits 14048647 # DTB hits
+system.cpu0.dtb.misses 33795 # DTB misses
+system.cpu0.dtb.accesses 14082442 # DTB accesses
+system.cpu0.itb.inst_hits 4222709 # ITB inst hits
+system.cpu0.itb.inst_misses 5005 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries 1346 # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_entries 1348 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults 1478 # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.perms_faults 1494 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
-system.cpu0.itb.inst_accesses 4229630 # ITB inst accesses
-system.cpu0.itb.hits 4224524 # DTB hits
-system.cpu0.itb.misses 5106 # DTB misses
-system.cpu0.itb.accesses 4229630 # DTB accesses
-system.cpu0.numCycles 69191123 # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses 4227714 # ITB inst accesses
+system.cpu0.itb.hits 4222709 # DTB hits
+system.cpu0.itb.misses 5005 # DTB misses
+system.cpu0.itb.accesses 4227714 # DTB accesses
+system.cpu0.numCycles 69175889 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.fetch.icacheStallCycles 11726999 # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts 32040106 # Number of instructions fetch has processed
-system.cpu0.fetch.Branches 6007013 # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches 3589910 # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles 7522223 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles 1454890 # Number of cycles fetch has spent squashing
-system.cpu0.fetch.TlbCycles 60839 # Number of cycles fetch has spent waiting for tlb
-system.cpu0.fetch.BlockedCycles 19594371 # Number of cycles fetch has spent blocked
-system.cpu0.fetch.MiscStallCycles 4906 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingTrapStallCycles 47034 # Number of stall cycles due to pending traps
-system.cpu0.fetch.PendingQuiesceStallCycles 1322790 # Number of stall cycles due to pending quiesce instructions
-system.cpu0.fetch.IcacheWaitRetryStallCycles 216 # Number of stall cycles due to full MSHR
-system.cpu0.fetch.CacheLines 4222942 # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes 157135 # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.ItlbSquashes 2060 # Number of outstanding ITLB misses that were squashed
-system.cpu0.fetch.rateDist::samples 41323427 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean 1.001891 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev 2.382270 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.icacheStallCycles 11717201 # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts 32026454 # Number of instructions fetch has processed
+system.cpu0.fetch.Branches 6002321 # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches 3587684 # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles 7519324 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles 1452827 # Number of cycles fetch has spent squashing
+system.cpu0.fetch.TlbCycles 60860 # Number of cycles fetch has spent waiting for tlb
+system.cpu0.fetch.BlockedCycles 19607589 # Number of cycles fetch has spent blocked
+system.cpu0.fetch.MiscStallCycles 5035 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu0.fetch.PendingTrapStallCycles 47006 # Number of stall cycles due to pending traps
+system.cpu0.fetch.PendingQuiesceStallCycles 1325879 # Number of stall cycles due to pending quiesce instructions
+system.cpu0.fetch.IcacheWaitRetryStallCycles 324 # Number of stall cycles due to full MSHR
+system.cpu0.fetch.CacheLines 4221110 # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes 157905 # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.ItlbSquashes 2000 # Number of outstanding ITLB misses that were squashed
+system.cpu0.fetch.rateDist::samples 41325646 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean 1.001484 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev 2.381957 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0 33808589 81.81% 81.81% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1 565594 1.37% 83.18% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2 817189 1.98% 85.16% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3 676917 1.64% 86.80% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::4 774557 1.87% 88.67% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::5 561158 1.36% 90.03% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::6 668023 1.62% 91.65% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::7 352527 0.85% 92.50% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::8 3098873 7.50% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0 33813760 81.82% 81.82% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1 565868 1.37% 83.19% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2 817164 1.98% 85.17% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3 676151 1.64% 86.81% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::4 772838 1.87% 88.68% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::5 560246 1.36% 90.03% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::6 669817 1.62% 91.65% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::7 351583 0.85% 92.50% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::8 3098219 7.50% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total 41323427 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate 0.086818 # Number of branch fetches per cycle
-system.cpu0.fetch.rate 0.463067 # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles 12228313 # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles 20776644 # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles 6830919 # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles 507068 # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles 980483 # Number of cycles decode is squashing
-system.cpu0.decode.BranchResolved 935966 # Number of times decode resolved a branch
-system.cpu0.decode.BranchMispred 64632 # Number of times decode detected a branch misprediction
-system.cpu0.decode.DecodedInsts 40044073 # Number of instructions handled by decode
-system.cpu0.decode.SquashedInsts 213118 # Number of squashed instructions handled by decode
-system.cpu0.rename.SquashCycles 980483 # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles 12794933 # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles 5974902 # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles 12785484 # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles 6719608 # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles 2068017 # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts 38935181 # Number of instructions processed by rename
-system.cpu0.rename.ROBFullEvents 1840 # Number of times rename has blocked due to ROB full
-system.cpu0.rename.IQFullEvents 426390 # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LSQFullEvents 1152446 # Number of times rename has blocked due to LSQ full
-system.cpu0.rename.FullRegisterEvents 100 # Number of times there has been no free registers
-system.cpu0.rename.RenamedOperands 39283995 # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups 175854037 # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups 175819876 # Number of integer rename lookups
-system.cpu0.rename.fp_rename_lookups 34161 # Number of floating rename lookups
-system.cpu0.rename.CommittedMaps 30939461 # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps 8344533 # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts 411347 # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts 370357 # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts 5351975 # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads 7655764 # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores 5689444 # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads 1124222 # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores 1281984 # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded 36848399 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded 895286 # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued 37254672 # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued 81509 # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined 6299557 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined 13203578 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved 256355 # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples 41323427 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean 0.901539 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev 1.514633 # Number of insts issued each cycle
+system.cpu0.fetch.rateDist::total 41325646 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate 0.086769 # Number of branch fetches per cycle
+system.cpu0.fetch.rate 0.462971 # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles 12221128 # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles 20791110 # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles 6824454 # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles 510238 # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles 978716 # Number of cycles decode is squashing
+system.cpu0.decode.BranchResolved 935346 # Number of times decode resolved a branch
+system.cpu0.decode.BranchMispred 64732 # Number of times decode detected a branch misprediction
+system.cpu0.decode.DecodedInsts 40027040 # Number of instructions handled by decode
+system.cpu0.decode.SquashedInsts 212951 # Number of squashed instructions handled by decode
+system.cpu0.rename.SquashCycles 978716 # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles 12790081 # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles 5972534 # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles 12789547 # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles 6714080 # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles 2080688 # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts 38920228 # Number of instructions processed by rename
+system.cpu0.rename.ROBFullEvents 1875 # Number of times rename has blocked due to ROB full
+system.cpu0.rename.IQFullEvents 436221 # Number of times rename has blocked due to IQ full
+system.cpu0.rename.LSQFullEvents 1152507 # Number of times rename has blocked due to LSQ full
+system.cpu0.rename.FullRegisterEvents 84 # Number of times there has been no free registers
+system.cpu0.rename.RenamedOperands 39264921 # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups 175790758 # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups 175756522 # Number of integer rename lookups
+system.cpu0.rename.fp_rename_lookups 34236 # Number of floating rename lookups
+system.cpu0.rename.CommittedMaps 30938700 # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps 8326220 # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts 411215 # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts 370279 # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts 5370420 # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads 7651291 # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores 5689186 # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads 1120456 # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores 1254854 # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded 36835170 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded 895288 # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued 37251130 # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued 81272 # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined 6287660 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined 13163035 # Number of squashed operands that are examined and possibly removed from graph
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system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
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-system.cpu0.iq.issued_per_cycle::2 3115322 7.54% 84.81% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3 2467752 5.97% 90.78% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4 2139591 5.18% 95.96% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5 926164 2.24% 98.20% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::6 502996 1.22% 99.42% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::7 185723 0.45% 99.87% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::8 53691 0.13% 100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0 26248472 63.52% 63.52% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1 5690851 13.77% 77.29% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2 3114453 7.54% 84.82% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3 2470786 5.98% 90.80% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4 2128163 5.15% 95.95% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5 926108 2.24% 98.19% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::6 506651 1.23% 99.42% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::7 185379 0.45% 99.87% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::8 54783 0.13% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total 41323427 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total 41325646 # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu 27493 2.57% 2.57% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult 452 0.04% 2.61% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.61% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.61% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.61% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.61% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.61% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.61% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.61% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.61% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.61% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.61% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.61% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.61% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.61% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.61% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.61% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.61% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.61% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.61% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.61% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.61% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.61% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.61% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.61% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.61% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.61% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.61% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.61% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead 842638 78.71% 81.32% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite 200034 18.68% 100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu 27685 2.59% 2.59% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult 452 0.04% 2.63% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.63% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.63% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.63% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.63% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.63% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.63% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.63% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.63% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.63% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.63% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.63% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.63% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.63% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.63% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.63% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.63% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.63% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.63% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.63% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.63% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.63% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.63% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.63% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.63% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.63% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.63% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.63% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead 842164 78.64% 81.27% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite 200566 18.73% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass 52214 0.14% 0.14% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu 22336809 59.96% 60.10% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult 46914 0.13% 60.22% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.22% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.22% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.22% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.22% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.22% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.22% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.22% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.22% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.22% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAlu 1 0.00% 60.22% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.22% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.22% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMisc 6 0.00% 60.22% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.22% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.22% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 60.22% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShiftAcc 3 0.00% 60.22% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.22% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.22% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.22% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.22% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.22% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.22% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu 22335497 59.96% 60.10% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult 46969 0.13% 60.23% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.23% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.23% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.23% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.23% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.23% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.23% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.23% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.23% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.23% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAlu 1 0.00% 60.23% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.23% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.23% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMisc 7 0.00% 60.23% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.23% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.23% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShift 1 0.00% 60.23% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShiftAcc 5 0.00% 60.23% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.23% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.23% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.23% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.23% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.23% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc 704 0.00% 60.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.23% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMultAcc 3 0.00% 60.23% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMultAcc 5 0.00% 60.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.23% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead 9369783 25.15% 85.38% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite 5448235 14.62% 100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead 9366005 25.14% 85.37% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite 5449722 14.63% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total 37254672 # Type of FU issued
-system.cpu0.iq.rate 0.538431 # Inst issue rate
-system.cpu0.iq.fu_busy_cnt 1070617 # FU busy when requested
-system.cpu0.iq.fu_busy_rate 0.028738 # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads 117010237 # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes 44051144 # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses 34347967 # Number of integer instruction queue wakeup accesses
-system.cpu0.iq.fp_inst_queue_reads 8478 # Number of floating instruction queue reads
-system.cpu0.iq.fp_inst_queue_writes 4654 # Number of floating instruction queue writes
-system.cpu0.iq.fp_inst_queue_wakeup_accesses 3872 # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses 38268613 # Number of integer alu accesses
-system.cpu0.iq.fp_alu_accesses 4462 # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads 307627 # Number of loads that had data forwarded from stores
+system.cpu0.iq.FU_type_0::total 37251130 # Type of FU issued
+system.cpu0.iq.rate 0.538499 # Inst issue rate
+system.cpu0.iq.fu_busy_cnt 1070867 # FU busy when requested
+system.cpu0.iq.fu_busy_rate 0.028747 # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads 117005145 # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes 44025943 # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses 34344840 # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.fp_inst_queue_reads 8484 # Number of floating instruction queue reads
+system.cpu0.iq.fp_inst_queue_writes 4662 # Number of floating instruction queue writes
+system.cpu0.iq.fp_inst_queue_wakeup_accesses 3874 # Number of floating instruction queue wakeup accesses
+system.cpu0.iq.int_alu_accesses 38265319 # Number of integer alu accesses
+system.cpu0.iq.fp_alu_accesses 4464 # Number of floating point alu accesses
+system.cpu0.iew.lsq.thread0.forwLoads 307168 # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads 1377452 # Number of loads squashed
-system.cpu0.iew.lsq.thread0.ignoredResponses 2519 # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread0.memOrderViolation 13094 # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores 537577 # Number of stores squashed
+system.cpu0.iew.lsq.thread0.squashedLoads 1372814 # Number of loads squashed
+system.cpu0.iew.lsq.thread0.ignoredResponses 2493 # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread0.memOrderViolation 13018 # Number of memory ordering violations
+system.cpu0.iew.lsq.thread0.squashedStores 537400 # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu0.iew.lsq.thread0.rescheduledLoads 2192819 # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked 5737 # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread0.rescheduledLoads 2192818 # Number of loads that were rescheduled
+system.cpu0.iew.lsq.thread0.cacheBlocked 5781 # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles 980483 # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles 4321779 # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles 103852 # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts 37861161 # Number of instructions dispatched to IQ
-system.cpu0.iew.iewDispSquashedInsts 83824 # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts 7655764 # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts 5689444 # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts 571291 # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents 39684 # Number of times the IQ has become full, causing a stall
-system.cpu0.iew.iewLSQFullEvents 13815 # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.memOrderViolationEvents 13094 # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect 150380 # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect 118124 # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts 268504 # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts 36875907 # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts 9227090 # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts 378765 # Number of squashed instructions skipped in execute
+system.cpu0.iew.iewSquashCycles 978716 # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles 4319425 # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles 103424 # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts 37848942 # Number of instructions dispatched to IQ
+system.cpu0.iew.iewDispSquashedInsts 83231 # Number of squashed instructions skipped by dispatch
+system.cpu0.iew.iewDispLoadInsts 7651291 # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts 5689186 # Number of dispatched store instructions
+system.cpu0.iew.iewDispNonSpecInsts 571145 # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewIQFullEvents 39872 # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewLSQFullEvents 13404 # Number of times the LSQ has become full, causing a stall
+system.cpu0.iew.memOrderViolationEvents 13018 # Number of memory order violations
+system.cpu0.iew.predictedTakenIncorrect 150227 # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedNotTakenIncorrect 117595 # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts 267822 # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewExecutedInsts 36871306 # Number of executed instructions
+system.cpu0.iew.iewExecLoadInsts 9223534 # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts 379824 # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp 0 # number of swp insts executed
-system.cpu0.iew.exec_nop 117476 # number of nop insts executed
-system.cpu0.iew.exec_refs 14627584 # number of memory reference insts executed
-system.cpu0.iew.exec_branches 4856181 # Number of branches executed
-system.cpu0.iew.exec_stores 5400494 # Number of stores executed
-system.cpu0.iew.exec_rate 0.532957 # Inst execution rate
-system.cpu0.iew.wb_sent 36680744 # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count 34351839 # cumulative count of insts written-back
-system.cpu0.iew.wb_producers 18317228 # num instructions producing a value
-system.cpu0.iew.wb_consumers 35218038 # num instructions consuming a value
+system.cpu0.iew.exec_nop 118484 # number of nop insts executed
+system.cpu0.iew.exec_refs 14624342 # number of memory reference insts executed
+system.cpu0.iew.exec_branches 4855002 # Number of branches executed
+system.cpu0.iew.exec_stores 5400808 # Number of stores executed
+system.cpu0.iew.exec_rate 0.533008 # Inst execution rate
+system.cpu0.iew.wb_sent 36677174 # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count 34348714 # cumulative count of insts written-back
+system.cpu0.iew.wb_producers 18316479 # num instructions producing a value
+system.cpu0.iew.wb_consumers 35213732 # num instructions consuming a value
system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu0.iew.wb_rate 0.496478 # insts written-back per cycle
-system.cpu0.iew.wb_fanout 0.520109 # average fanout of values written-back
+system.cpu0.iew.wb_rate 0.496542 # insts written-back per cycle
+system.cpu0.iew.wb_fanout 0.520152 # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu0.commit.commitSquashedInsts 6105741 # The number of squashed insts skipped by commit
-system.cpu0.commit.commitNonSpecStalls 638931 # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts 232529 # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples 40342944 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean 0.775737 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev 1.743782 # Number of insts commited each cycle
+system.cpu0.commit.commitSquashedInsts 6093987 # The number of squashed insts skipped by commit
+system.cpu0.commit.commitNonSpecStalls 638923 # The number of times commit has been forced to stall to communicate backwards
+system.cpu0.commit.branchMispredicts 232030 # The number of times a branch was mispredicted
+system.cpu0.commit.committed_per_cycle::samples 40346930 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean 0.775643 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev 1.740681 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0 28719843 71.19% 71.19% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1 5706970 14.15% 85.34% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2 1863125 4.62% 89.95% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3 981446 2.43% 92.39% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4 776304 1.92% 94.31% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5 515472 1.28% 95.59% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6 394004 0.98% 96.57% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7 214891 0.53% 97.10% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8 1170889 2.90% 100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0 28704762 71.14% 71.14% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1 5702920 14.13% 85.28% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2 1886389 4.68% 89.95% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3 981050 2.43% 92.39% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4 790069 1.96% 94.34% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5 509429 1.26% 95.61% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6 395100 0.98% 96.59% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7 219754 0.54% 97.13% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8 1157457 2.87% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total 40342944 # Number of insts commited each cycle
-system.cpu0.commit.committedInsts 23687602 # Number of instructions committed
-system.cpu0.commit.committedOps 31295507 # Number of ops (including micro ops) committed
+system.cpu0.commit.committed_per_cycle::total 40346930 # Number of insts commited each cycle
+system.cpu0.commit.committedInsts 23686340 # Number of instructions committed
+system.cpu0.commit.committedOps 31294803 # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu0.commit.refs 11430179 # Number of memory references committed
-system.cpu0.commit.loads 6278312 # Number of loads committed
-system.cpu0.commit.membars 229695 # Number of memory barriers committed
-system.cpu0.commit.branches 4246577 # Number of branches committed
+system.cpu0.commit.refs 11430263 # Number of memory references committed
+system.cpu0.commit.loads 6278477 # Number of loads committed
+system.cpu0.commit.membars 229716 # Number of memory barriers committed
+system.cpu0.commit.branches 4246456 # Number of branches committed
system.cpu0.commit.fp_insts 3838 # Number of committed floating point instructions.
-system.cpu0.commit.int_insts 27650890 # Number of committed integer instructions.
-system.cpu0.commit.function_calls 489495 # Number of function calls committed.
-system.cpu0.commit.bw_lim_events 1170889 # number cycles where commit BW limit reached
+system.cpu0.commit.int_insts 27650320 # Number of committed integer instructions.
+system.cpu0.commit.function_calls 489514 # Number of function calls committed.
+system.cpu0.commit.bw_lim_events 1157457 # number cycles where commit BW limit reached
system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu0.rob.rob_reads 75722045 # The number of ROB reads
-system.cpu0.rob.rob_writes 75784919 # The number of ROB writes
-system.cpu0.timesIdled 368023 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu0.idleCycles 27867696 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.quiesceCycles 2158812857 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.committedInsts 23606860 # Number of Instructions Simulated
-system.cpu0.committedOps 31214765 # Number of Ops (including micro ops) Simulated
-system.cpu0.committedInsts_total 23606860 # Number of Instructions Simulated
-system.cpu0.cpi 2.930975 # CPI: Cycles Per Instruction
-system.cpu0.cpi_total 2.930975 # CPI: Total CPI of All Threads
-system.cpu0.ipc 0.341183 # IPC: Instructions Per Cycle
-system.cpu0.ipc_total 0.341183 # IPC: Total IPC of All Threads
-system.cpu0.int_regfile_reads 171887932 # number of integer regfile reads
-system.cpu0.int_regfile_writes 34101589 # number of integer regfile writes
-system.cpu0.fp_regfile_reads 3230 # number of floating regfile reads
-system.cpu0.fp_regfile_writes 874 # number of floating regfile writes
-system.cpu0.misc_regfile_reads 12983242 # number of misc regfile reads
-system.cpu0.misc_regfile_writes 451267 # number of misc regfile writes
-system.cpu0.icache.tags.replacements 393301 # number of replacements
-system.cpu0.icache.tags.tagsinuse 511.011114 # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs 3798020 # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs 393813 # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs 9.644222 # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle 6979217250 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.011114 # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998069 # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total 0.998069 # Average percentage of cache occupancy
-system.cpu0.icache.ReadReq_hits::cpu0.inst 3798020 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total 3798020 # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst 3798020 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total 3798020 # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst 3798020 # number of overall hits
-system.cpu0.icache.overall_hits::total 3798020 # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst 424793 # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total 424793 # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst 424793 # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total 424793 # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst 424793 # number of overall misses
-system.cpu0.icache.overall_misses::total 424793 # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5908836480 # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total 5908836480 # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst 5908836480 # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total 5908836480 # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst 5908836480 # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total 5908836480 # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst 4222813 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total 4222813 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst 4222813 # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total 4222813 # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst 4222813 # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total 4222813 # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.100595 # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total 0.100595 # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst 0.100595 # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total 0.100595 # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst 0.100595 # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total 0.100595 # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13909.919608 # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 13909.919608 # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13909.919608 # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 13909.919608 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13909.919608 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 13909.919608 # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs 3571 # number of cycles access was blocked
+system.cpu0.rob.rob_reads 75726854 # The number of ROB reads
+system.cpu0.rob.rob_writes 75758265 # The number of ROB writes
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+system.cpu0.idleCycles 27850243 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu0.quiesceCycles 2138859041 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.committedInsts 23605598 # Number of Instructions Simulated
+system.cpu0.committedOps 31214061 # Number of Ops (including micro ops) Simulated
+system.cpu0.committedInsts_total 23605598 # Number of Instructions Simulated
+system.cpu0.cpi 2.930487 # CPI: Cycles Per Instruction
+system.cpu0.cpi_total 2.930487 # CPI: Total CPI of All Threads
+system.cpu0.ipc 0.341240 # IPC: Instructions Per Cycle
+system.cpu0.ipc_total 0.341240 # IPC: Total IPC of All Threads
+system.cpu0.int_regfile_reads 171860544 # number of integer regfile reads
+system.cpu0.int_regfile_writes 34096305 # number of integer regfile writes
+system.cpu0.fp_regfile_reads 3262 # number of floating regfile reads
+system.cpu0.fp_regfile_writes 892 # number of floating regfile writes
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+system.cpu0.misc_regfile_writes 451140 # number of misc regfile writes
+system.cpu0.icache.tags.replacements 392795 # number of replacements
+system.cpu0.icache.tags.tagsinuse 511.002835 # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs 3796668 # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs 393307 # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs 9.653192 # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle 6982777250 # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.002835 # Average occupied blocks per requestor
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+system.cpu0.icache.tags.occ_percent::total 0.998052 # Average percentage of cache occupancy
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+system.cpu0.icache.overall_hits::total 3796668 # number of overall hits
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+system.cpu0.icache.ReadReq_misses::total 424314 # number of ReadReq misses
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+system.cpu0.icache.overall_misses::total 424314 # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5901888496 # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total 5901888496 # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst 5901888496 # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total 5901888496 # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst 5901888496 # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total 5901888496 # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst 4220982 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total 4220982 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst 4220982 # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total 4220982 # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst 4220982 # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total 4220982 # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.100525 # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total 0.100525 # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst 0.100525 # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total 0.100525 # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst 0.100525 # miss rate for overall accesses
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system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
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+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051744 # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051744 # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data 0.181048 # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total 0.181048 # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data 0.181048 # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total 0.181048 # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14099.137760 # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 14099.137760 # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 48784.818359 # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 48784.818359 # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10080.728895 # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10080.728895 # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6139.656283 # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6139.656283 # average StoreCondReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 41909.682874 # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 41909.682874 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 41909.682874 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 41909.682874 # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs 11704 # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets 6407 # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs 613 # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets 131 # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs 19.092985 # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets 48.908397 # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks 256588 # number of writebacks
-system.cpu0.dcache.writebacks::total 256588 # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 203202 # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total 203202 # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1454368 # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total 1454368 # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 460 # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total 460 # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data 1657570 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total 1657570 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data 1657570 # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total 1657570 # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 188820 # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total 188820 # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 130419 # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total 130419 # number of WriteReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8297 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8297 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7522 # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total 7522 # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data 319239 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total 319239 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data 319239 # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total 319239 # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2408343372 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2408343372 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5110867707 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5110867707 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 66642015 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 66642015 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 31254873 # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 31254873 # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 3000 # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 3000 # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7519211079 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total 7519211079 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7519211079 # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total 7519211079 # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13504631783 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13504631783 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1180253969 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1180253969 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14684885752 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14684885752 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030571 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030571 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027491 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027491 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.056028 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.056028 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.052006 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.052006 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029233 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total 0.029233 # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029233 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total 0.029233 # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12754.704862 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12754.704862 # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 39188.060842 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 39188.060842 # average WriteReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8032.061589 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8032.061589 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4155.128024 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4155.128024 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23553.547903 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23553.547903 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23553.547903 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23553.547903 # average overall mshr miss latency
+system.cpu0.dcache.writebacks::writebacks 256512 # number of writebacks
+system.cpu0.dcache.writebacks::total 256512 # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 203095 # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total 203095 # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1454344 # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total 1454344 # number of WriteReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 453 # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total 453 # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data 1657439 # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total 1657439 # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data 1657439 # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total 1657439 # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 188695 # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total 188695 # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 130482 # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total 130482 # number of WriteReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8289 # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8289 # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7480 # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total 7480 # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data 319177 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total 319177 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data 319177 # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total 319177 # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2406687867 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2406687867 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5110325446 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5110325446 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 66640768 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 66640768 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 30961371 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 30961371 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7517013313 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total 7517013313 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7517013313 # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total 7517013313 # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13504611525 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13504611525 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1131834379 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1131834379 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14636445904 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14636445904 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030566 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030566 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027503 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027503 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.056049 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.056049 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051744 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051744 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029235 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total 0.029235 # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029235 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total 0.029235 # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12754.380704 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12754.380704 # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 39164.984028 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 39164.984028 # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8039.663168 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8039.663168 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4139.220722 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4139.220722 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23551.237442 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23551.237442 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23551.237442 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23551.237442 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.branchPred.lookups 9066954 # Number of BP lookups
-system.cpu1.branchPred.condPredicted 7451944 # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect 406719 # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups 6049384 # Number of BTB lookups
-system.cpu1.branchPred.BTBHits 5236824 # Number of BTB hits
+system.cpu1.branchPred.lookups 8782132 # Number of BP lookups
+system.cpu1.branchPred.condPredicted 7168426 # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect 407819 # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups 5819499 # Number of BTB lookups
+system.cpu1.branchPred.BTBHits 4955017 # Number of BTB hits
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct 86.567889 # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS 772531 # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect 42321 # Number of incorrect RAS predictions.
+system.cpu1.branchPred.BTBHitPct 85.145079 # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS 773793 # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect 42171 # Number of incorrect RAS predictions.
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 42909677 # DTB read hits
-system.cpu1.dtb.read_misses 36560 # DTB read misses
-system.cpu1.dtb.write_hits 6823585 # DTB write hits
-system.cpu1.dtb.write_misses 10691 # DTB write misses
+system.cpu1.dtb.read_hits 42691295 # DTB read hits
+system.cpu1.dtb.read_misses 36496 # DTB read misses
+system.cpu1.dtb.write_hits 6824033 # DTB write hits
+system.cpu1.dtb.write_misses 10597 # DTB write misses
system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries 2017 # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults 2608 # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults 306 # Number of TLB faults due to prefetch
+system.cpu1.dtb.flush_entries 2020 # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults 2612 # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults 305 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults 688 # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses 42946237 # DTB read accesses
-system.cpu1.dtb.write_accesses 6834276 # DTB write accesses
+system.cpu1.dtb.perms_faults 657 # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses 42727791 # DTB read accesses
+system.cpu1.dtb.write_accesses 6834630 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dtb.hits 49733262 # DTB hits
-system.cpu1.dtb.misses 47251 # DTB misses
-system.cpu1.dtb.accesses 49780513 # DTB accesses
-system.cpu1.itb.inst_hits 8323198 # ITB inst hits
-system.cpu1.itb.inst_misses 5400 # ITB inst misses
+system.cpu1.dtb.hits 49515328 # DTB hits
+system.cpu1.dtb.misses 47093 # DTB misses
+system.cpu1.dtb.accesses 49562421 # DTB accesses
+system.cpu1.itb.inst_hits 7577708 # ITB inst hits
+system.cpu1.itb.inst_misses 5297 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults 1523 # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.perms_faults 1545 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.inst_accesses 8328598 # ITB inst accesses
-system.cpu1.itb.hits 8323198 # DTB hits
-system.cpu1.itb.misses 5400 # DTB misses
-system.cpu1.itb.accesses 8328598 # DTB accesses
-system.cpu1.numCycles 410695591 # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses 7583005 # ITB inst accesses
+system.cpu1.itb.hits 7577708 # DTB hits
+system.cpu1.itb.misses 5297 # DTB misses
+system.cpu1.itb.accesses 7583005 # DTB accesses
+system.cpu1.numCycles 408491180 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.fetch.icacheStallCycles 19628666 # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts 66104666 # Number of instructions fetch has processed
-system.cpu1.fetch.Branches 9066954 # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches 6009355 # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles 14131573 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles 3952223 # Number of cycles fetch has spent squashing
-system.cpu1.fetch.TlbCycles 62853 # Number of cycles fetch has spent waiting for tlb
-system.cpu1.fetch.BlockedCycles 77248707 # Number of cycles fetch has spent blocked
-system.cpu1.fetch.MiscStallCycles 4835 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.PendingTrapStallCycles 42228 # Number of stall cycles due to pending traps
-system.cpu1.fetch.PendingQuiesceStallCycles 1436171 # Number of stall cycles due to pending quiesce instructions
-system.cpu1.fetch.IcacheWaitRetryStallCycles 176 # Number of stall cycles due to full MSHR
-system.cpu1.fetch.CacheLines 8321388 # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes 704092 # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.ItlbSquashes 2736 # Number of outstanding ITLB misses that were squashed
-system.cpu1.fetch.rateDist::samples 115246116 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean 0.694374 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev 2.038205 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.icacheStallCycles 18854224 # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts 60287918 # Number of instructions fetch has processed
+system.cpu1.fetch.Branches 8782132 # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches 5728810 # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles 13124144 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles 3307681 # Number of cycles fetch has spent squashing
+system.cpu1.fetch.TlbCycles 62009 # Number of cycles fetch has spent waiting for tlb
+system.cpu1.fetch.BlockedCycles 77240238 # Number of cycles fetch has spent blocked
+system.cpu1.fetch.MiscStallCycles 4754 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.PendingTrapStallCycles 42673 # Number of stall cycles due to pending traps
+system.cpu1.fetch.PendingQuiesceStallCycles 1437796 # Number of stall cycles due to pending quiesce instructions
+system.cpu1.fetch.IcacheWaitRetryStallCycles 160 # Number of stall cycles due to full MSHR
+system.cpu1.fetch.CacheLines 7575877 # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes 546214 # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.ItlbSquashes 2648 # Number of outstanding ITLB misses that were squashed
+system.cpu1.fetch.rateDist::samples 113028448 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean 0.652235 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev 1.978835 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0 101121884 87.74% 87.74% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1 796637 0.69% 88.44% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2 937162 0.81% 89.25% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3 1885853 1.64% 90.89% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::4 1499695 1.30% 92.19% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::5 570142 0.49% 92.68% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::6 2110638 1.83% 94.51% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::7 410756 0.36% 94.87% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::8 5913349 5.13% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0 99911588 88.40% 88.40% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1 796149 0.70% 89.10% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2 938672 0.83% 89.93% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3 1688468 1.49% 91.42% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::4 1396344 1.24% 92.66% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::5 570472 0.50% 93.16% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::6 1929580 1.71% 94.87% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::7 410359 0.36% 95.23% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::8 5386816 4.77% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total 115246116 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate 0.022077 # Number of branch fetches per cycle
-system.cpu1.fetch.rate 0.160958 # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles 21155925 # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles 78195753 # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles 12775663 # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles 524358 # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles 2594417 # Number of cycles decode is squashing
-system.cpu1.decode.BranchResolved 1105836 # Number of times decode resolved a branch
-system.cpu1.decode.BranchMispred 98153 # Number of times decode detected a branch misprediction
-system.cpu1.decode.DecodedInsts 75067660 # Number of instructions handled by decode
-system.cpu1.decode.SquashedInsts 326745 # Number of squashed instructions handled by decode
-system.cpu1.rename.SquashCycles 2594417 # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles 22501379 # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles 33242741 # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles 40762154 # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles 11860446 # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles 4284979 # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts 69913296 # Number of instructions processed by rename
-system.cpu1.rename.ROBFullEvents 18816 # Number of times rename has blocked due to ROB full
-system.cpu1.rename.IQFullEvents 670004 # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LSQFullEvents 3042907 # Number of times rename has blocked due to LSQ full
-system.cpu1.rename.FullRegisterEvents 379 # Number of times there has been no free registers
-system.cpu1.rename.RenamedOperands 73978163 # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups 321899381 # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups 321840484 # Number of integer rename lookups
-system.cpu1.rename.fp_rename_lookups 58897 # Number of floating rename lookups
-system.cpu1.rename.CommittedMaps 49060581 # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps 24917582 # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts 444517 # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts 387690 # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts 7870912 # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads 13163327 # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores 8127092 # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads 1028302 # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores 1543452 # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded 63442447 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded 1157372 # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued 89134089 # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued 93553 # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined 16181139 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined 45168283 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved 276533 # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples 115246116 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean 0.773424 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev 1.513958 # Number of insts issued each cycle
+system.cpu1.fetch.rateDist::total 113028448 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate 0.021499 # Number of branch fetches per cycle
+system.cpu1.fetch.rate 0.147587 # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles 20182430 # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles 78186513 # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles 11968696 # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles 524734 # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles 2166075 # Number of cycles decode is squashing
+system.cpu1.decode.BranchResolved 1104186 # Number of times decode resolved a branch
+system.cpu1.decode.BranchMispred 97997 # Number of times decode detected a branch misprediction
+system.cpu1.decode.DecodedInsts 69821372 # Number of instructions handled by decode
+system.cpu1.decode.SquashedInsts 325725 # Number of squashed instructions handled by decode
+system.cpu1.rename.SquashCycles 2166075 # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles 21372370 # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles 33233612 # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles 40763249 # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles 11209012 # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles 4284130 # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts 65907040 # Number of instructions processed by rename
+system.cpu1.rename.ROBFullEvents 18855 # Number of times rename has blocked due to ROB full
+system.cpu1.rename.IQFullEvents 668466 # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LSQFullEvents 3042854 # Number of times rename has blocked due to LSQ full
+system.cpu1.rename.FullRegisterEvents 1130 # Number of times there has been no free registers
+system.cpu1.rename.RenamedOperands 69218982 # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups 302521919 # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups 302462653 # Number of integer rename lookups
+system.cpu1.rename.fp_rename_lookups 59266 # Number of floating rename lookups
+system.cpu1.rename.CommittedMaps 49058929 # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps 20160053 # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts 444772 # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts 387840 # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts 7873214 # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads 12591353 # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores 7935523 # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads 1036537 # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores 1457992 # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded 60681374 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded 1157953 # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued 87712578 # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued 93570 # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined 13421216 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined 35924412 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved 277156 # Number of squashed non-spec instructions that were removed
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+system.cpu1.iq.issued_per_cycle::mean 0.776022 # Number of insts issued each cycle
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system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
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-system.cpu1.iq.issued_per_cycle::2 4255514 3.69% 84.63% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3 3817238 3.31% 87.94% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4 10566074 9.17% 97.11% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5 1932638 1.68% 98.78% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::6 1074262 0.93% 99.71% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::7 253370 0.22% 99.93% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::8 75482 0.07% 100.00% # Number of insts issued each cycle
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+system.cpu1.iq.issued_per_cycle::6 1039899 0.92% 99.69% # Number of insts issued each cycle
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system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total 115246116 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total 113028448 # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu 32069 0.41% 0.41% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu 32070 0.41% 0.41% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult 996 0.01% 0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.42% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead 7550960 95.79% 96.21% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite 298953 3.79% 100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead 7550021 95.87% 96.29% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite 292311 3.71% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu1.iq.FU_type_0::No_OpClass 314062 0.35% 0.35% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu 37650996 42.24% 42.59% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult 59191 0.07% 42.66% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.66% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.66% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.66% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 42.66% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 42.66% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 42.66% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 42.66% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 42.66% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.66% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.66% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.66% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.66% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc 11 0.00% 42.66% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.66% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.66% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 42.66% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc 8 0.00% 42.66% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.66% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.66% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.66% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.66% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.66% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.66% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc 1510 0.00% 42.66% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.66% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 42.66% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.66% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead 43937068 49.29% 91.95% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite 7171235 8.05% 100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::No_OpClass 314062 0.36% 0.36% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu 36603154 41.73% 42.09% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult 59244 0.07% 42.16% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.16% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.16% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.16% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 42.16% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 42.16% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 42.16% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 42.16% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 42.16% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.16% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.16% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.16% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.16% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc 8 0.00% 42.16% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.16% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.16% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 42.16% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc 6 0.00% 42.16% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.16% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.16% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.16% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.16% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.16% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.16% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc 1508 0.00% 42.16% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.16% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 42.16% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.16% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead 43563118 49.67% 91.82% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite 7171472 8.18% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total 89134089 # Type of FU issued
-system.cpu1.iq.rate 0.217032 # Inst issue rate
-system.cpu1.iq.fu_busy_cnt 7882978 # FU busy when requested
-system.cpu1.iq.fu_busy_rate 0.088440 # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads 301522554 # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes 80789150 # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses 53744584 # Number of integer instruction queue wakeup accesses
-system.cpu1.iq.fp_inst_queue_reads 15343 # Number of floating instruction queue reads
-system.cpu1.iq.fp_inst_queue_writes 8026 # Number of floating instruction queue writes
-system.cpu1.iq.fp_inst_queue_wakeup_accesses 6801 # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses 96694852 # Number of integer alu accesses
-system.cpu1.iq.fp_alu_accesses 8153 # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads 340284 # Number of loads that had data forwarded from stores
+system.cpu1.iq.FU_type_0::total 87712578 # Type of FU issued
+system.cpu1.iq.rate 0.214723 # Inst issue rate
+system.cpu1.iq.fu_busy_cnt 7875398 # FU busy when requested
+system.cpu1.iq.fu_busy_rate 0.089786 # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads 296453915 # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes 75268930 # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses 53141218 # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.fp_inst_queue_reads 15550 # Number of floating instruction queue reads
+system.cpu1.iq.fp_inst_queue_writes 8086 # Number of floating instruction queue writes
+system.cpu1.iq.fp_inst_queue_wakeup_accesses 6819 # Number of floating instruction queue wakeup accesses
+system.cpu1.iq.int_alu_accesses 95265602 # Number of integer alu accesses
+system.cpu1.iq.fp_alu_accesses 8312 # Number of floating point alu accesses
+system.cpu1.iew.lsq.thread0.forwLoads 341261 # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads 3407112 # Number of loads squashed
+system.cpu1.iew.lsq.thread0.squashedLoads 2835568 # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses 3737 # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation 16742 # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores 1286559 # Number of stores squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation 17004 # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores 1095143 # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu1.iew.lsq.thread0.rescheduledLoads 31912923 # Number of loads that were rescheduled
-system.cpu1.iew.lsq.thread0.cacheBlocked 915604 # Number of times an access to memory failed due to the cache being blocked
+system.cpu1.iew.lsq.thread0.rescheduledLoads 31913350 # Number of loads that were rescheduled
+system.cpu1.iew.lsq.thread0.cacheBlocked 674872 # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles 2594417 # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles 25467221 # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles 361914 # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts 64703269 # Number of instructions dispatched to IQ
-system.cpu1.iew.iewDispSquashedInsts 112618 # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts 13163327 # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts 8127092 # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts 869000 # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents 64609 # Number of times the IQ has become full, causing a stall
-system.cpu1.iew.iewLSQFullEvents 6290 # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents 16742 # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect 200151 # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect 154994 # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts 355145 # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts 86813167 # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts 43279828 # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts 2320922 # Number of squashed instructions skipped in execute
+system.cpu1.iew.iewSquashCycles 2166075 # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles 25455774 # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles 362563 # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts 61943028 # Number of instructions dispatched to IQ
+system.cpu1.iew.iewDispSquashedInsts 112233 # Number of squashed instructions skipped by dispatch
+system.cpu1.iew.iewDispLoadInsts 12591353 # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts 7935523 # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts 869270 # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents 64753 # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewLSQFullEvents 6199 # Number of times the LSQ has become full, causing a stall
+system.cpu1.iew.memOrderViolationEvents 17004 # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect 201423 # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect 154723 # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts 356146 # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts 85989556 # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts 43061283 # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts 1723022 # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp 0 # number of swp insts executed
-system.cpu1.iew.exec_nop 103450 # number of nop insts executed
-system.cpu1.iew.exec_refs 50389574 # number of memory reference insts executed
-system.cpu1.iew.exec_branches 6997831 # Number of branches executed
-system.cpu1.iew.exec_stores 7109746 # Number of stores executed
-system.cpu1.iew.exec_rate 0.211381 # Inst execution rate
-system.cpu1.iew.wb_sent 85834090 # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count 53751385 # cumulative count of insts written-back
-system.cpu1.iew.wb_producers 29958578 # num instructions producing a value
-system.cpu1.iew.wb_consumers 53322000 # num instructions consuming a value
+system.cpu1.iew.exec_nop 103701 # number of nop insts executed
+system.cpu1.iew.exec_refs 50171461 # number of memory reference insts executed
+system.cpu1.iew.exec_branches 6912906 # Number of branches executed
+system.cpu1.iew.exec_stores 7110178 # Number of stores executed
+system.cpu1.iew.exec_rate 0.210505 # Inst execution rate
+system.cpu1.iew.wb_sent 85230378 # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count 53148037 # cumulative count of insts written-back
+system.cpu1.iew.wb_producers 29710424 # num instructions producing a value
+system.cpu1.iew.wb_consumers 52969976 # num instructions consuming a value
system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu1.iew.wb_rate 0.130879 # insts written-back per cycle
-system.cpu1.iew.wb_fanout 0.561843 # average fanout of values written-back
+system.cpu1.iew.wb_rate 0.130108 # insts written-back per cycle
+system.cpu1.iew.wb_fanout 0.560892 # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu1.commit.commitSquashedInsts 16054832 # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls 880839 # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts 310229 # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples 112651699 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean 0.427506 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev 1.393608 # Number of insts commited each cycle
+system.cpu1.commit.commitSquashedInsts 13294883 # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls 880797 # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts 311444 # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples 110862373 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean 0.434393 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev 1.404754 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0 95929787 85.16% 85.16% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1 8195439 7.28% 92.43% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2 2121242 1.88% 94.31% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3 1255081 1.11% 95.43% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4 1260461 1.12% 96.55% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5 575308 0.51% 97.06% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6 943355 0.84% 97.90% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7 590559 0.52% 98.42% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8 1780467 1.58% 100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0 94147475 84.92% 84.92% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1 8220753 7.42% 92.34% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2 2089215 1.88% 94.22% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3 1249683 1.13% 95.35% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4 1247924 1.13% 96.48% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5 575753 0.52% 96.99% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6 991767 0.89% 97.89% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7 529898 0.48% 98.37% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8 1809905 1.63% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total 112651699 # Number of insts commited each cycle
-system.cpu1.commit.committedInsts 38067147 # Number of instructions committed
-system.cpu1.commit.committedOps 48159329 # Number of ops (including micro ops) committed
+system.cpu1.commit.committed_per_cycle::total 110862373 # Number of insts commited each cycle
+system.cpu1.commit.committedInsts 38066252 # Number of instructions committed
+system.cpu1.commit.committedOps 48157821 # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu1.commit.refs 16596748 # Number of memory references committed
-system.cpu1.commit.loads 9756215 # Number of loads committed
-system.cpu1.commit.membars 190139 # Number of memory barriers committed
-system.cpu1.commit.branches 5967970 # Number of branches committed
+system.cpu1.commit.refs 16596165 # Number of memory references committed
+system.cpu1.commit.loads 9755785 # Number of loads committed
+system.cpu1.commit.membars 190126 # Number of memory barriers committed
+system.cpu1.commit.branches 5967905 # Number of branches committed
system.cpu1.commit.fp_insts 6758 # Number of committed floating point instructions.
-system.cpu1.commit.int_insts 42694003 # Number of committed integer instructions.
-system.cpu1.commit.function_calls 534679 # Number of function calls committed.
-system.cpu1.commit.bw_lim_events 1780467 # number cycles where commit BW limit reached
+system.cpu1.commit.int_insts 42692526 # Number of committed integer instructions.
+system.cpu1.commit.function_calls 534650 # Number of function calls committed.
+system.cpu1.commit.bw_lim_events 1809905 # number cycles where commit BW limit reached
system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu1.rob.rob_reads 174041277 # The number of ROB reads
-system.cpu1.rob.rob_writes 131120872 # The number of ROB writes
-system.cpu1.timesIdled 1414866 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles 295449475 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.quiesceCycles 1816711228 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts 37997508 # Number of Instructions Simulated
-system.cpu1.committedOps 48089690 # Number of Ops (including micro ops) Simulated
-system.cpu1.committedInsts_total 37997508 # Number of Instructions Simulated
-system.cpu1.cpi 10.808488 # CPI: Cycles Per Instruction
-system.cpu1.cpi_total 10.808488 # CPI: Total CPI of All Threads
-system.cpu1.ipc 0.092520 # IPC: Instructions Per Cycle
-system.cpu1.ipc_total 0.092520 # IPC: Total IPC of All Threads
-system.cpu1.int_regfile_reads 388394171 # number of integer regfile reads
-system.cpu1.int_regfile_writes 56329363 # number of integer regfile writes
-system.cpu1.fp_regfile_reads 5049 # number of floating regfile reads
-system.cpu1.fp_regfile_writes 2330 # number of floating regfile writes
-system.cpu1.misc_regfile_reads 18495746 # number of misc regfile reads
-system.cpu1.misc_regfile_writes 405487 # number of misc regfile writes
-system.cpu1.icache.tags.replacements 596092 # number of replacements
-system.cpu1.icache.tags.tagsinuse 480.837460 # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs 7679654 # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs 596604 # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs 12.872280 # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle 74828235500 # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst 480.837460 # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst 0.939136 # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total 0.939136 # Average percentage of cache occupancy
-system.cpu1.icache.ReadReq_hits::cpu1.inst 7679654 # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total 7679654 # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst 7679654 # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total 7679654 # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst 7679654 # number of overall hits
-system.cpu1.icache.overall_hits::total 7679654 # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst 641686 # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total 641686 # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst 641686 # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total 641686 # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst 641686 # number of overall misses
-system.cpu1.icache.overall_misses::total 641686 # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8725652874 # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total 8725652874 # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst 8725652874 # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total 8725652874 # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst 8725652874 # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total 8725652874 # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst 8321340 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total 8321340 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst 8321340 # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total 8321340 # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst 8321340 # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total 8321340 # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.077113 # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total 0.077113 # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst 0.077113 # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total 0.077113 # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst 0.077113 # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total 0.077113 # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13598.010357 # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 13598.010357 # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13598.010357 # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 13598.010357 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13598.010357 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 13598.010357 # average overall miss latency
-system.cpu1.icache.blocked_cycles::no_mshrs 3474 # number of cycles access was blocked
+system.cpu1.rob.rob_reads 169461098 # The number of ROB reads
+system.cpu1.rob.rob_writes 125154390 # The number of ROB writes
+system.cpu1.timesIdled 1414583 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu1.idleCycles 295462732 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu1.quiesceCycles 1798949280 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.committedInsts 37996613 # Number of Instructions Simulated
+system.cpu1.committedOps 48088182 # Number of Ops (including micro ops) Simulated
+system.cpu1.committedInsts_total 37996613 # Number of Instructions Simulated
+system.cpu1.cpi 10.750726 # CPI: Cycles Per Instruction
+system.cpu1.cpi_total 10.750726 # CPI: Total CPI of All Threads
+system.cpu1.ipc 0.093017 # IPC: Instructions Per Cycle
+system.cpu1.ipc_total 0.093017 # IPC: Total IPC of All Threads
+system.cpu1.int_regfile_reads 384900722 # number of integer regfile reads
+system.cpu1.int_regfile_writes 55276259 # number of integer regfile writes
+system.cpu1.fp_regfile_reads 5045 # number of floating regfile reads
+system.cpu1.fp_regfile_writes 2312 # number of floating regfile writes
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+system.cpu1.misc_regfile_writes 405460 # number of misc regfile writes
+system.cpu1.icache.tags.replacements 594712 # number of replacements
+system.cpu1.icache.tags.tagsinuse 480.460982 # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs 6935744 # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs 595224 # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs 11.652326 # Average number of references to valid blocks.
+system.cpu1.icache.tags.warmup_cycle 74833132000 # Cycle when the warmup percentage was hit.
+system.cpu1.icache.tags.occ_blocks::cpu1.inst 480.460982 # Average occupied blocks per requestor
+system.cpu1.icache.tags.occ_percent::cpu1.inst 0.938400 # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_percent::total 0.938400 # Average percentage of cache occupancy
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+system.cpu1.icache.overall_hits::total 6935744 # number of overall hits
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+system.cpu1.icache.ReadReq_miss_latency::total 8700934064 # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst 8700934064 # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total 8700934064 # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst 8700934064 # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total 8700934064 # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst 7575829 # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total 7575829 # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst 7575829 # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total 7575829 # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst 7575829 # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total 7575829 # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.084490 # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total 0.084490 # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst 0.084490 # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total 0.084490 # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst 0.084490 # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total 0.084490 # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13593.404101 # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total 13593.404101 # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13593.404101 # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total 13593.404101 # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13593.404101 # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total 13593.404101 # average overall miss latency
+system.cpu1.icache.blocked_cycles::no_mshrs 2623 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu1.icache.blocked::no_mshrs 210 # number of cycles access was blocked
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system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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-system.cpu1.icache.ReadReq_mshr_misses::total 596626 # number of ReadReq MSHR misses
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-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11935.710532 # average overall mshr miss latency
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+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9275.508240 # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9275.508240 # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5022.341712 # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5022.341712 # average StoreCondReq miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 42004.345406 # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 42004.345406 # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 42004.345406 # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 42004.345406 # average overall miss latency
+system.cpu1.dcache.blocked_cycles::no_mshrs 29557 # number of cycles access was blocked
+system.cpu1.dcache.blocked_cycles::no_targets 18184 # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_mshrs 3279 # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_targets 168 # number of cycles access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_mshrs 9.014029 # average number of cycles each access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_targets 108.238095 # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks 324789 # number of writebacks
-system.cpu1.dcache.writebacks::total 324789 # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 170095 # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total 170095 # number of ReadReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1396532 # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::total 1396532 # number of WriteReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1437 # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1437 # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits::cpu1.data 1566627 # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_hits::total 1566627 # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.data 1566627 # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total 1566627 # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 228081 # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total 228081 # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 161620 # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total 161620 # number of WriteReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12503 # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12503 # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10598 # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total 10598 # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data 389701 # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total 389701 # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data 389701 # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total 389701 # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2839406051 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2839406051 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 6490016907 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total 6490016907 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 88435503 # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 88435503 # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 32057085 # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 32057085 # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 9329422958 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total 9329422958 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 9329422958 # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total 9329422958 # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168915044006 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168915044006 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 34787133815 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 34787133815 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 203702177821 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total 203702177821 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026187 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.026187 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028369 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028369 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.112123 # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.112123 # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100477 # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100477 # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027050 # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total 0.027050 # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.027050 # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total 0.027050 # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12449.112600 # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12449.112600 # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 40156.025906 # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 40156.025906 # average WriteReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7073.142686 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7073.142686 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3024.824023 # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3024.824023 # average StoreCondReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 23939.951291 # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 23939.951291 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 23939.951291 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 23939.951291 # average overall mshr miss latency
+system.cpu1.dcache.writebacks::writebacks 324751 # number of writebacks
+system.cpu1.dcache.writebacks::total 324751 # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 168850 # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total 168850 # number of ReadReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1396175 # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::total 1396175 # number of WriteReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1447 # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1447 # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.demand_mshr_hits::cpu1.data 1565025 # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_hits::total 1565025 # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits::cpu1.data 1565025 # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_hits::total 1565025 # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 228268 # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total 228268 # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 161652 # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total 161652 # number of WriteReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12509 # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12509 # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10578 # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total 10578 # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data 389920 # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total 389920 # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data 389920 # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total 389920 # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2830993566 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2830993566 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 6516328872 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total 6516328872 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 88639506 # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 88639506 # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 31988580 # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 31988580 # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 9347322438 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total 9347322438 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 9347322438 # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total 9347322438 # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168914513007 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168914513007 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 25825904490 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 25825904490 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 194740417497 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total 194740417497 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026212 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.026212 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028376 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028376 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.112187 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.112187 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100283 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100283 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027068 # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total 0.027068 # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.027068 # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total 0.027068 # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12402.060587 # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12402.060587 # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 40310.845965 # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 40310.845965 # average WriteReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7086.058518 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7086.058518 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3024.066931 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3024.066931 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 23972.410848 # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 23972.410848 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 23972.410848 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 23972.410848 # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.iocache.tags.replacements 0 # number of replacements
-system.iocache.tags.tagsinuse 0 # Cycle average of tags in use
-system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks.
-system.iocache.tags.avg_refs nan # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.iocache.tags.replacements 0 # number of replacements
+system.iocache.tags.tagsinuse 0 # Cycle average of tags in use
+system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
+system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks.
+system.iocache.tags.avg_refs nan # Average number of references to valid blocks.
+system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 644226028268 # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 644226028268 # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 644226028268 # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 644226028268 # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 582931892511 # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 582931892511 # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 582931892511 # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 582931892511 # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.quiesce 41725 # number of quiesce instructions executed
+system.cpu0.kern.inst.quiesce 41731 # number of quiesce instructions executed
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
-system.cpu1.kern.inst.quiesce 48857 # number of quiesce instructions executed
+system.cpu1.kern.inst.quiesce 48858 # number of quiesce instructions executed
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 2.534332 # Number of seconds simulated
-sim_ticks 2534332336000 # Number of ticks simulated
-final_tick 2534332336000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 2.524310 # Number of seconds simulated
+sim_ticks 2524309551500 # Number of ticks simulated
+final_tick 2524309551500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 60160 # Simulator instruction rate (inst/s)
-host_op_rate 77409 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2528112838 # Simulator tick rate (ticks/s)
-host_mem_usage 401532 # Number of bytes of host memory used
-host_seconds 1002.46 # Real time elapsed on the host
-sim_insts 60307773 # Number of instructions simulated
-sim_ops 77599321 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::realview.clcd 119572608 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.dtb.walker 2816 # Number of bytes read from this memory
+host_inst_rate 81082 # Simulator instruction rate (inst/s)
+host_op_rate 104330 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 3394002800 # Simulator tick rate (ticks/s)
+host_mem_usage 397632 # Number of bytes of host memory used
+host_seconds 743.76 # Real time elapsed on the host
+sim_insts 60305560 # Number of instructions simulated
+sim_ops 77596391 # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.dtb.walker 3264 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst 798144 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 9095056 # Number of bytes read from this memory
-system.physmem.bytes_read::total 129468752 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 798144 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 798144 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 3785216 # Number of bytes written to this memory
+system.physmem.bytes_read::cpu.inst 796608 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 9093968 # Number of bytes read from this memory
+system.physmem.bytes_read::total 129431632 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 796608 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 796608 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 3783552 # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory
-system.physmem.bytes_written::total 6801288 # Number of bytes written to this memory
-system.physmem.num_reads::realview.clcd 14946576 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.dtb.walker 44 # Number of read requests responded to by this memory
+system.physmem.bytes_written::total 6799624 # Number of bytes written to this memory
+system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.dtb.walker 51 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst 12471 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 142144 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 15101237 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 59144 # Number of write requests responded to by this memory
+system.physmem.num_reads::cpu.inst 12447 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 142127 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 15096835 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 59118 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 813162 # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd 47181108 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.dtb.walker 1111 # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total 813136 # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd 47354598 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.dtb.walker 1293 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker 51 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst 314933 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 3588738 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 51085941 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 314933 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 314933 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1493575 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data 1190085 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 2683661 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1493575 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd 47181108 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker 1111 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 315575 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 3602557 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 51274073 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 315575 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 315575 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 1498846 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data 1194811 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 2693657 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 1498846 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd 47354598 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker 1293 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker 51 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 314933 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 4778824 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 53769602 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 15101237 # Total number of read requests seen
-system.physmem.writeReqs 813162 # Total number of write requests seen
-system.physmem.cpureqs 218445 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 966479168 # Total number of bytes read from memory
-system.physmem.bytesWritten 52042368 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 129468752 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 6801288 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 279 # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite 4676 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 944611 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 944270 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 944423 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 944612 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 943754 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 943694 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 943515 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 943302 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 944002 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 943653 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 943221 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 942812 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 943924 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 943688 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 943784 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 943693 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 49130 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 48913 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2 50969 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 51083 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 51011 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5 51261 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6 51258 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 51200 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 51354 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 51098 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 50757 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11 50407 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12 51356 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13 50977 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14 51264 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15 51124 # Track writes on a per bank basis
+system.physmem.bw_total::cpu.inst 315575 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 4797367 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 53967730 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 15096835 # Total number of read requests accepted by DRAM controller
+system.physmem.writeReqs 813136 # Total number of write requests accepted by DRAM controller
+system.physmem.readBursts 15096835 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
+system.physmem.writeBursts 813136 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
+system.physmem.bytesRead 966197440 # Total number of bytes read from memory
+system.physmem.bytesWritten 52040704 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 129431632 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 6799624 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 6192 # Number of DRAM read bursts serviced by write Q
+system.physmem.neitherReadNorWrite 4675 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 943576 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 943244 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 943285 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 942562 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 943112 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 943339 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 943114 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 941930 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 944001 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 943651 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 943211 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 941608 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 943926 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 943681 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 943781 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 942622 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 6701 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 6473 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 6622 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 6647 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 6560 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 6809 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 6802 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 6725 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 7149 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 6889 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 6554 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 6197 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 7152 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 6775 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 7049 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 6917 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
-system.physmem.numWrRetry 32457 # Number of times wr buffer was full causing retry
-system.physmem.totGap 2534332242000 # Total gap between requests
+system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
+system.physmem.totGap 2524308440000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 36 # Categorize read packet sizes
-system.physmem.readPktSize::3 14946576 # Categorize read packet sizes
+system.physmem.readPktSize::3 14942208 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 154625 # Categorize read packet sizes
+system.physmem.readPktSize::6 154591 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
system.physmem.writePktSize::2 754018 # Categorize write packet sizes
system.physmem.writePktSize::3 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
-system.physmem.writePktSize::6 59144 # Categorize write packet sizes
-system.physmem.rdQLenPdf::0 1052232 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 984006 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 974713 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 3682136 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 2757823 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 2756219 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 2725955 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 17025 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 15237 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 28723 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 42159 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11 28643 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12 9083 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13 9038 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14 12526 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15 5326 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16 104 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17 7 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18 2 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 59118 # Categorize write packet sizes
+system.physmem.rdQLenPdf::0 1057147 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 988434 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 981496 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 3682842 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 2771885 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 2756532 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 2709889 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 18251 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 16218 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 29451 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10 42435 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11 28819 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12 1928 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13 1827 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14 1752 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15 1697 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16 27 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17 9 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 2588 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 2654 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 2707 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 2777 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 2803 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 2823 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6 2850 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 2875 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8 2885 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9 35355 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10 35355 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11 35355 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12 35355 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13 35355 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14 35355 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 35355 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 35355 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 35355 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 35355 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 35355 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 35354 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 35354 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 35354 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 32767 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 32701 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 32648 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 32578 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 32552 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 32532 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 32505 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 32480 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 32470 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 42332 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 24053.235566 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 1833.734815 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 32311.504914 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::64-95 8211 19.40% 19.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-159 3440 8.13% 27.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::192-223 2237 5.28% 32.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-287 1775 4.19% 37.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::320-351 1231 2.91% 39.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-415 1031 2.44% 42.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::448-479 888 2.10% 44.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-543 774 1.83% 46.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::576-607 547 1.29% 47.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-671 559 1.32% 48.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::704-735 426 1.01% 49.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-799 432 1.02% 50.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::832-863 287 0.68% 51.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-927 279 0.66% 52.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::960-991 159 0.38% 52.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1055 249 0.59% 53.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1088-1119 131 0.31% 53.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1152-1183 141 0.33% 53.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1216-1247 101 0.24% 54.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1280-1311 136 0.32% 54.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1344-1375 82 0.19% 54.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1408-1439 379 0.90% 55.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1472-1503 1813 4.28% 59.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1536-1567 447 1.06% 60.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1600-1631 86 0.20% 61.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1664-1695 158 0.37% 61.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1728-1759 41 0.10% 61.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1792-1823 104 0.25% 61.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1856-1887 37 0.09% 61.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1920-1951 64 0.15% 62.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1984-2015 25 0.06% 62.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2048-2079 71 0.17% 62.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2112-2143 17 0.04% 62.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2176-2207 45 0.11% 62.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2240-2271 11 0.03% 62.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2304-2335 40 0.09% 62.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2368-2399 10 0.02% 62.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2432-2463 26 0.06% 62.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2496-2527 12 0.03% 62.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2560-2591 19 0.04% 62.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2624-2655 3 0.01% 62.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2688-2719 16 0.04% 62.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2752-2783 8 0.02% 62.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2816-2847 18 0.04% 62.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2880-2911 12 0.03% 62.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2944-2975 13 0.03% 62.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3008-3039 6 0.01% 62.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3072-3103 25 0.06% 62.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3136-3167 6 0.01% 62.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3200-3231 6 0.01% 62.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3264-3295 9 0.02% 62.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3328-3359 13 0.03% 62.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3392-3423 6 0.01% 62.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3456-3487 6 0.01% 63.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3520-3551 2 0.00% 63.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3584-3615 9 0.02% 63.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3648-3679 6 0.01% 63.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3712-3743 8 0.02% 63.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3776-3807 5 0.01% 63.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3840-3871 1 0.00% 63.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3904-3935 4 0.01% 63.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3968-3999 6 0.01% 63.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4032-4063 4 0.01% 63.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4096-4127 43 0.10% 63.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4160-4191 2 0.00% 63.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4224-4255 3 0.01% 63.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4288-4319 7 0.02% 63.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4352-4383 8 0.02% 63.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4416-4447 8 0.02% 63.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4480-4511 6 0.01% 63.29% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4544-4575 4 0.01% 63.29% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4608-4639 7 0.02% 63.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4736-4767 4 0.01% 63.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4864-4895 2 0.00% 63.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4928-4959 3 0.01% 63.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4992-5023 2 0.00% 63.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5120-5151 10 0.02% 63.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5184-5215 3 0.01% 63.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5248-5279 2 0.00% 63.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5312-5343 1 0.00% 63.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5376-5407 2 0.00% 63.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5440-5471 1 0.00% 63.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5632-5663 1 0.00% 63.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5696-5727 1 0.00% 63.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5760-5791 1 0.00% 63.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5824-5855 3 0.01% 63.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5888-5919 5 0.01% 63.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5952-5983 1 0.00% 63.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6016-6047 1 0.00% 63.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6080-6111 1 0.00% 63.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6144-6175 7 0.02% 63.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6208-6239 1 0.00% 63.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6272-6303 1 0.00% 63.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6464-6495 2 0.00% 63.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6528-6559 4 0.01% 63.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6592-6623 3 0.01% 63.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6656-6687 2 0.00% 63.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6720-6751 1 0.00% 63.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6784-6815 20 0.05% 63.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6848-6879 3 0.01% 63.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6912-6943 3 0.01% 63.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6976-7007 1 0.00% 63.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7040-7071 4 0.01% 63.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7104-7135 1 0.00% 63.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7168-7199 4 0.01% 63.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7296-7327 1 0.00% 63.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7360-7391 1 0.00% 63.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7424-7455 4 0.01% 63.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7488-7519 1 0.00% 63.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7552-7583 3 0.01% 63.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7616-7647 1 0.00% 63.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7680-7711 7 0.02% 63.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7744-7775 1 0.00% 63.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7808-7839 3 0.01% 63.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7872-7903 2 0.00% 63.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7936-7967 3 0.01% 63.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8000-8031 3 0.01% 63.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8064-8095 11 0.03% 63.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8128-8159 4 0.01% 63.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8192-8223 322 0.76% 64.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8448-8479 1 0.00% 64.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8704-8735 1 0.00% 64.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8960-8991 1 0.00% 64.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9216-9247 1 0.00% 64.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10240-10271 18 0.04% 64.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10496-10527 2 0.00% 64.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11008-11039 1 0.00% 64.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11264-11295 2 0.00% 64.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11520-11551 1 0.00% 64.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11776-11807 1 0.00% 64.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12288-12319 3 0.01% 64.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12480-12511 1 0.00% 64.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12544-12575 1 0.00% 64.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12800-12831 1 0.00% 64.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13056-13087 1 0.00% 64.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13312-13343 2 0.00% 64.51% # Bytes accessed per row activation
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-system.physmem.bytesPerActivate::14592-14623 1 0.00% 64.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15360-15391 3 0.01% 64.53% # Bytes accessed per row activation
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-system.physmem.bytesPerActivate::16960-16991 1 0.00% 64.54% # Bytes accessed per row activation
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-system.physmem.bytesPerActivate::17408-17439 5 0.01% 64.56% # Bytes accessed per row activation
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-system.physmem.bytesPerActivate::31936-31967 1 0.00% 64.74% # Bytes accessed per row activation
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-system.physmem.bytesPerActivate::40704-40735 1 0.00% 64.91% # Bytes accessed per row activation
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-system.physmem.bytesPerActivate::62464-62495 1 0.00% 64.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::62528-62559 1 0.00% 64.96% # Bytes accessed per row activation
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-system.physmem.bytesPerActivate::65280-65311 18 0.04% 65.07% # Bytes accessed per row activation
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-system.physmem.bytesPerActivate::65472-65503 12 0.03% 65.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::65536-65567 14415 34.05% 99.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::130816-130847 1 0.00% 99.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::131072-131103 330 0.78% 99.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::131200-131231 1 0.00% 99.96% # Bytes accessed per row activation
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-system.physmem.bytesPerActivate::136576-136607 1 0.00% 99.97% # Bytes accessed per row activation
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-system.physmem.bytesPerActivate::160704-160735 1 0.00% 99.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::160768-160799 1 0.00% 99.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::192512-192543 1 0.00% 99.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::196416-196447 1 0.00% 99.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::196608-196639 8 0.02% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 42332 # Bytes accessed per row activation
-system.physmem.totQLat 352162436750 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 443380465500 # Sum of mem lat for all requests
-system.physmem.totBusLat 75504790000 # Total cycles spent in databus access
-system.physmem.totBankLat 15713238750 # Total cycles spent in bank access
-system.physmem.avgQLat 23320.54 # Average queueing delay per request
-system.physmem.avgBankLat 1040.55 # Average bank access latency per request
+system.physmem.wrQLenPdf::0 4688 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::24 2 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples 39039 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 24916.423474 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 2046.440838 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 31393.496682 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::64-79 6673 17.09% 17.09% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-143 3432 8.79% 25.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::192-207 2242 5.74% 31.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-271 1810 4.64% 36.26% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::320-335 1230 3.15% 39.41% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-399 1032 2.64% 42.06% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::448-463 839 2.15% 44.21% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-527 821 2.10% 46.31% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::576-591 572 1.47% 47.78% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-655 506 1.30% 49.07% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::704-719 409 1.05% 50.12% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-783 444 1.14% 51.26% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::832-847 300 0.77% 52.02% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-911 247 0.63% 52.66% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::960-975 176 0.45% 53.11% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1039 206 0.53% 53.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1088-1103 143 0.37% 54.00% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::total 39039 # Bytes accessed per row activation
+system.physmem.totQLat 291463008250 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 382223273250 # Sum of mem lat for all requests
+system.physmem.totBusLat 75453215000 # Total cycles spent in databus access
+system.physmem.totBankLat 15307050000 # Total cycles spent in bank access
+system.physmem.avgQLat 19314.15 # Average queueing delay per request
+system.physmem.avgBankLat 1014.34 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 29361.08 # Average memory access latency
-system.physmem.avgRdBW 381.35 # Average achieved read bandwidth in MB/s
-system.physmem.avgWrBW 20.53 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 51.09 # Average consumed read bandwidth in MB/s
-system.physmem.avgConsumedWrBW 2.68 # Average consumed write bandwidth in MB/s
+system.physmem.avgMemAccLat 25328.49 # Average memory access latency
+system.physmem.avgRdBW 382.76 # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW 20.62 # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW 51.27 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedWrBW 2.69 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
-system.physmem.busUtil 3.14 # Data bus utilization in percentage
-system.physmem.avgRdQLen 0.17 # Average read queue length over time
-system.physmem.avgWrQLen 10.77 # Average write queue length over time
-system.physmem.readRowHits 15074158 # Number of row buffer hits during reads
-system.physmem.writeRowHits 797610 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 99.82 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 98.09 # Row buffer hit rate for writes
-system.physmem.avgGap 159247.75 # Average gap between requests
+system.physmem.busUtil 3.15 # Data bus utilization in percentage
+system.physmem.avgRdQLen 0.15 # Average read queue length over time
+system.physmem.avgWrQLen 14.41 # Average write queue length over time
+system.physmem.readRowHits 15065383 # Number of row buffer hits during reads
+system.physmem.writeRowHits 94229 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 99.83 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 11.59 # Row buffer hit rate for writes
+system.physmem.avgGap 158662.04 # Average gap between requests
system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory
system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput 54715776 # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq 16153842 # Transaction distribution
-system.membus.trans_dist::ReadResp 16153842 # Transaction distribution
-system.membus.trans_dist::WriteReq 763336 # Transaction distribution
-system.membus.trans_dist::WriteResp 763336 # Transaction distribution
-system.membus.trans_dist::Writeback 59144 # Transaction distribution
+system.membus.throughput 54917647 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 16149440 # Transaction distribution
+system.membus.trans_dist::ReadResp 16149440 # Transaction distribution
+system.membus.trans_dist::WriteReq 763332 # Transaction distribution
+system.membus.trans_dist::WriteResp 763332 # Transaction distribution
+system.membus.trans_dist::Writeback 59118 # Transaction distribution
system.membus.trans_dist::UpgradeReq 4673 # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 4676 # Transaction distribution
-system.membus.trans_dist::ReadExReq 131438 # Transaction distribution
-system.membus.trans_dist::ReadExResp 131438 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2382948 # Packet count per connected master and slave (bytes)
+system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 4675 # Transaction distribution
+system.membus.trans_dist::ReadExReq 131433 # Transaction distribution
+system.membus.trans_dist::ReadExResp 131433 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2382940 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1885854 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3770 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3760 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4272576 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 29893152 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total 29893152 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::system.bridge.slave 2382948 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::system.physmem.port 31779006 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::system.realview.gic.pio 3770 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 34165728 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390313 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1885758 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4272462 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 29884416 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total 29884416 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 34156878 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390297 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16697432 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7540 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7520 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19095353 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 119572608 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.iocache.mem_side::total 119572608 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::system.bridge.slave 2390313 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::system.physmem.port 136270040 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::system.realview.gic.pio 7540 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 138667961 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 138667961 # Total data (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16693592 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19091477 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 119537664 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.iocache.mem_side::total 119537664 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total 138629141 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 138629141 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy 1475262000 # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy 1475500000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.membus.reqLayer1.occupancy 1000 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 17374745000 # Layer occupancy (ticks)
-system.membus.reqLayer2.utilization 0.7 # Layer utilization (%)
-system.membus.reqLayer3.occupancy 3634500 # Layer occupancy (ticks)
-system.membus.reqLayer3.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer5.occupancy 1500 # Layer occupancy (ticks)
-system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer1.occupancy 4718589198 # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy 3702500 # Layer occupancy (ticks)
+system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
+system.membus.reqLayer4.occupancy 1500 # Layer occupancy (ticks)
+system.membus.reqLayer4.utilization 0.0 # Layer utilization (%)
+system.membus.reqLayer6.occupancy 17367026000 # Layer occupancy (ticks)
+system.membus.reqLayer6.utilization 0.7 # Layer utilization (%)
+system.membus.respLayer1.occupancy 4748565769 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
-system.membus.respLayer2.occupancy 33742309741 # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy 33728733739 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 1.3 # Layer utilization (%)
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
-system.iobus.throughput 48124265 # Throughput (bytes/s)
-system.iobus.trans_dist::ReadReq 16129900 # Transaction distribution
-system.iobus.trans_dist::ReadResp 16129887 # Transaction distribution
-system.iobus.trans_dist::WriteReq 8158 # Transaction distribution
-system.iobus.trans_dist::WriteResp 8158 # Transaction distribution
+system.iobus.throughput 48301509 # Throughput (bytes/s)
+system.iobus.trans_dist::ReadReq 16125521 # Transaction distribution
+system.iobus.trans_dist::ReadResp 16125521 # Transaction distribution
+system.iobus.trans_dist::WriteReq 8157 # Transaction distribution
+system.iobus.trans_dist::WriteResp 8157 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7938 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 518 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1026 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7934 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 516 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1024 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 2382948 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 29893155 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.clcd.dma::total 29893155 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.realview_io.pio 7938 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.timer0.pio 518 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.timer1.pio 1026 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.iocache.cpu_side 29893155 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 32276103 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 2382940 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 29884416 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.clcd.dma::total 29884416 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 32267356 # Packet count per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15876 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1036 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2052 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15868 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1032 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2048 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::total 2390313 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 119572568 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.realview.clcd.dma::total 119572568 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.realview_io.pio 15876 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.timer0.pio 1036 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.timer1.pio 2052 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.iocache.cpu_side 119572568 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::total 121962881 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.data_through_bus 121962881 # Total data (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::total 2390297 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 119537664 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.realview.clcd.dma::total 119537664 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::total 121927961 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.data_through_bus 121927961 # Total data (bytes)
system.iobus.reqLayer0.occupancy 21043000 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer1.occupancy 3974000 # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy 3972000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer2.occupancy 518000 # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy 516000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer3.occupancy 519000 # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy 518000 # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer25.occupancy 14946584000 # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy 14942208000 # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%)
-system.iobus.respLayer0.occupancy 2374790000 # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy 2374783000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.1 # Layer utilization (%)
-system.iobus.respLayer1.occupancy 40962341509 # Layer occupancy (ticks)
+system.iobus.respLayer1.occupancy 40954817261 # Layer occupancy (ticks)
system.iobus.respLayer1.utilization 1.6 # Layer utilization (%)
-system.cpu.branchPred.lookups 14663186 # Number of BP lookups
-system.cpu.branchPred.condPredicted 11751443 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 703165 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 9748962 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 7940354 # Number of BTB hits
+system.cpu.branchPred.lookups 14390442 # Number of BP lookups
+system.cpu.branchPred.condPredicted 11476977 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 705087 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 9493942 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 7662575 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 81.448199 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 1396465 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 72132 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 80.710152 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 1400623 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 72808 # Number of incorrect RAS predictions.
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.read_hits 51389107 # DTB read hits
-system.cpu.dtb.read_misses 64168 # DTB read misses
-system.cpu.dtb.write_hits 11699261 # DTB write hits
-system.cpu.dtb.write_misses 15977 # DTB write misses
+system.cpu.dtb.read_hits 51188083 # DTB read hits
+system.cpu.dtb.read_misses 64353 # DTB read misses
+system.cpu.dtb.write_hits 11697459 # DTB write hits
+system.cpu.dtb.write_misses 15788 # DTB write misses
system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries 3558 # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults 2439 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults 422 # Number of TLB faults due to prefetch
+system.cpu.dtb.flush_entries 3561 # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults 2446 # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults 415 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults 1367 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses 51453275 # DTB read accesses
-system.cpu.dtb.write_accesses 11715238 # DTB write accesses
+system.cpu.dtb.perms_faults 1347 # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses 51252436 # DTB read accesses
+system.cpu.dtb.write_accesses 11713247 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.dtb.hits 63088368 # DTB hits
-system.cpu.dtb.misses 80145 # DTB misses
-system.cpu.dtb.accesses 63168513 # DTB accesses
-system.cpu.itb.inst_hits 12244686 # ITB inst hits
-system.cpu.itb.inst_misses 11272 # ITB inst misses
+system.cpu.dtb.hits 62885542 # DTB hits
+system.cpu.dtb.misses 80141 # DTB misses
+system.cpu.dtb.accesses 62965683 # DTB accesses
+system.cpu.itb.inst_hits 11520428 # ITB inst hits
+system.cpu.itb.inst_misses 11439 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries 2481 # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_entries 2486 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults 2937 # Number of TLB faults due to permissions restrictions
+system.cpu.itb.perms_faults 2948 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.inst_accesses 12255958 # ITB inst accesses
-system.cpu.itb.hits 12244686 # DTB hits
-system.cpu.itb.misses 11272 # DTB misses
-system.cpu.itb.accesses 12255958 # DTB accesses
-system.cpu.numCycles 475312551 # number of cpu cycles simulated
+system.cpu.itb.inst_accesses 11531867 # ITB inst accesses
+system.cpu.itb.hits 11520428 # DTB hits
+system.cpu.itb.misses 11439 # DTB misses
+system.cpu.itb.accesses 11531867 # DTB accesses
+system.cpu.numCycles 473080437 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 30486466 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 96013812 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 14663186 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 9336819 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 21137847 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 5287329 # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles 121734 # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.BlockedCycles 94652697 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 3821 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 86418 # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles 2672948 # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles 439 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 12241258 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 862361 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes 5349 # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples 152790281 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 0.777398 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.141854 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 29726178 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 90285458 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 14390442 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 9063198 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 20148067 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 4655224 # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles 122776 # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.BlockedCycles 94622822 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 2576 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 87000 # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles 2672031 # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles 423 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 11516980 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 710202 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes 5463 # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples 150589774 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 0.747645 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.103384 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 131667661 86.18% 86.18% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 1302340 0.85% 87.03% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 1711403 1.12% 88.15% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 2491779 1.63% 89.78% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 2204039 1.44% 91.22% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 1109873 0.73% 91.95% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 2734812 1.79% 93.74% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 742969 0.49% 94.22% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 8825405 5.78% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 130457024 86.63% 86.63% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 1304262 0.87% 87.50% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 1711201 1.14% 88.63% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 2296542 1.53% 90.16% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 2101589 1.40% 91.55% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 1109749 0.74% 92.29% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 2556764 1.70% 93.99% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 745428 0.50% 94.48% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 8307215 5.52% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 152790281 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.030850 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.202001 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 32434469 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 96765795 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 19163623 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 968040 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 3458354 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 1955309 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 172027 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 112442167 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 568180 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 3458354 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 34339332 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 38106819 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 52671042 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 18167139 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 6047595 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 106212332 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 20597 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 1004586 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 4065982 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 631 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 110697957 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 485950395 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 485859311 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 91084 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 78390094 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 32307862 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 830633 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 736877 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 12210661 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 20268413 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 13492534 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 1964739 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 2435625 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 97824738 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 1983401 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 124295624 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 165509 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 21636439 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 56320984 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 501000 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 152790281 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.813505 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.528895 # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total 150589774 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.030419 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.190846 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 31488393 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 96724206 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 18371972 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 966714 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 3038489 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 1954982 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 171905 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 107292337 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 568657 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 3038489 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 33240542 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 38064536 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 52670739 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 17528991 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 6046477 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 102291911 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 20574 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 1004468 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 4066422 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents 675 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 106031051 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 466975975 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 466885287 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 90688 # Number of floating rename lookups
+system.cpu.rename.CommittedMaps 78387144 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 27643906 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 830126 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 736572 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 12200321 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 19725062 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 13304379 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 1973962 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 2485771 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 95123211 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 1983556 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 122912009 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 167105 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 18943027 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 47293965 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 501256 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 150589774 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.816204 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 108515921 71.02% 71.02% # Number of insts issued each cycle
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-system.cpu.iq.issued_per_cycle::2 7066338 4.62% 84.54% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 5978859 3.91% 88.45% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 12565558 8.22% 96.68% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 2772936 1.81% 98.49% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 1725765 1.13% 99.62% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 449060 0.29% 99.92% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 126515 0.08% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 106863631 70.96% 70.96% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 13450296 8.93% 79.90% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 6941050 4.61% 84.50% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 5871130 3.90% 88.40% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 12365050 8.21% 96.61% # Number of insts issued each cycle
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+system.cpu.iq.issued_per_cycle::6 1693786 1.12% 99.60% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 467660 0.31% 99.92% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 152790281 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 150589774 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 62738 0.71% 0.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 4 0.00% 0.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 62506 0.71% 0.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 5 0.00% 0.71% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 0.71% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.71% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 8365929 94.58% 95.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 416628 4.71% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 8370674 94.63% 95.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 412716 4.67% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass 363666 0.29% 0.29% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 58652585 47.19% 47.48% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 93247 0.08% 47.56% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.56% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.56% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.56% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.56% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.56% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.56% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 21 0.00% 47.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 2 0.00% 47.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 14 0.00% 47.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 2114 0.00% 47.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 14 0.00% 47.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.56% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 52864927 42.53% 90.09% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 12319034 9.91% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass 363666 0.30% 0.30% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 57621227 46.88% 47.18% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 93185 0.08% 47.25% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.25% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.25% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.25% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.25% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.25% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.25% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 21 0.00% 47.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 3 0.00% 47.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 15 0.00% 47.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 2113 0.00% 47.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 15 0.00% 47.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.25% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 52514471 42.73% 89.98% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 12317293 10.02% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 124295624 # Type of FU issued
-system.cpu.iq.rate 0.261503 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 8845299 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.071163 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 410448757 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 121460975 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 86059539 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 23386 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 12542 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 10302 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 132764827 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 12430 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 625909 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 122912009 # Type of FU issued
+system.cpu.iq.rate 0.259812 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 8845901 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.071969 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 405483238 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 116066435 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 85469374 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 23342 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 12510 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 10296 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 131381798 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 12446 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 624501 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 4613851 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 6375 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 30092 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 1760453 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 4071224 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 6576 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 30290 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 1572736 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 34107892 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 916935 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 34107774 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 679836 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 3458354 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 29328857 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 436741 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 100030676 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 203650 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 20268413 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 13492534 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 1410837 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 115234 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 3326 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 30092 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 349264 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 268145 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 617409 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 121630045 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 52076046 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 2665579 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 3038489 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 29300006 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 434231 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 97327801 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 206590 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 19725062 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 13304379 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 1410590 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 113060 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 3500 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 30290 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 351701 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 268555 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 620256 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 120832629 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 51875152 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 2079380 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 222537 # number of nop insts executed
-system.cpu.iew.exec_refs 64287237 # number of memory reference insts executed
-system.cpu.iew.exec_branches 11556571 # Number of branches executed
-system.cpu.iew.exec_stores 12211191 # Number of stores executed
-system.cpu.iew.exec_rate 0.255895 # Inst execution rate
-system.cpu.iew.wb_sent 120479293 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 86069841 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 47268516 # num instructions producing a value
-system.cpu.iew.wb_consumers 88195904 # num instructions consuming a value
+system.cpu.iew.exec_nop 221034 # number of nop insts executed
+system.cpu.iew.exec_refs 64084349 # number of memory reference insts executed
+system.cpu.iew.exec_branches 11474602 # Number of branches executed
+system.cpu.iew.exec_stores 12209197 # Number of stores executed
+system.cpu.iew.exec_rate 0.255417 # Inst execution rate
+system.cpu.iew.wb_sent 119890042 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 85479670 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 47030253 # num instructions producing a value
+system.cpu.iew.wb_consumers 87881540 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 0.181081 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.535949 # average fanout of values written-back
+system.cpu.iew.wb_rate 0.180687 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.535155 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 21374007 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 1482401 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 533608 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 149331927 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.520650 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.508241 # Number of insts commited each cycle
+system.cpu.commit.commitSquashedInsts 18673473 # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls 1482300 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts 535675 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 147551285 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.526914 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.516633 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 121887208 81.62% 81.62% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 13290460 8.90% 90.52% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 3923979 2.63% 93.15% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 2130804 1.43% 94.58% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 1950357 1.31% 95.88% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 968781 0.65% 96.53% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 1543061 1.03% 97.56% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 783043 0.52% 98.09% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 2854234 1.91% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 120109216 81.40% 81.40% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 13315885 9.02% 90.43% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 3896468 2.64% 93.07% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 2118661 1.44% 94.50% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 1945134 1.32% 95.82% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 977268 0.66% 96.48% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 1587082 1.08% 97.56% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 719968 0.49% 98.05% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 2881603 1.95% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 149331927 # Number of insts commited each cycle
-system.cpu.commit.committedInsts 60458154 # Number of instructions committed
-system.cpu.commit.committedOps 77749702 # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total 147551285 # Number of insts commited each cycle
+system.cpu.commit.committedInsts 60455941 # Number of instructions committed
+system.cpu.commit.committedOps 77746772 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.refs 27386643 # Number of memory references committed
-system.cpu.commit.loads 15654562 # Number of loads committed
-system.cpu.commit.membars 403601 # Number of memory barriers committed
-system.cpu.commit.branches 9961356 # Number of branches committed
+system.cpu.commit.refs 27385481 # Number of memory references committed
+system.cpu.commit.loads 15653838 # Number of loads committed
+system.cpu.commit.membars 403568 # Number of memory barriers committed
+system.cpu.commit.branches 9961054 # Number of branches committed
system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 68854920 # Number of committed integer instructions.
-system.cpu.commit.function_calls 991265 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 2854234 # number cycles where commit BW limit reached
+system.cpu.commit.int_insts 68852229 # Number of committed integer instructions.
+system.cpu.commit.function_calls 991205 # Number of function calls committed.
+system.cpu.commit.bw_lim_events 2881603 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 243752783 # The number of ROB reads
-system.cpu.rob.rob_writes 201807644 # The number of ROB writes
-system.cpu.timesIdled 1781061 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 322522270 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles 4593269077 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts 60307773 # Number of Instructions Simulated
-system.cpu.committedOps 77599321 # Number of Ops (including micro ops) Simulated
-system.cpu.committedInsts_total 60307773 # Number of Instructions Simulated
-system.cpu.cpi 7.881448 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 7.881448 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.126880 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.126880 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 550637144 # number of integer regfile reads
-system.cpu.int_regfile_writes 88566595 # number of integer regfile writes
-system.cpu.fp_regfile_reads 8370 # number of floating regfile reads
-system.cpu.fp_regfile_writes 2906 # number of floating regfile writes
-system.cpu.misc_regfile_reads 30124157 # number of misc regfile reads
-system.cpu.misc_regfile_writes 831896 # number of misc regfile writes
-system.cpu.toL2Bus.throughput 58663468 # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq 2657447 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 2657446 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteReq 763336 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteResp 763336 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback 607541 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq 2966 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::SCUpgradeReq 17 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp 2983 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 245999 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 245999 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1961368 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 5795761 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma 30461 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma 126683 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count 7914273 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 62726656 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 85494329 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma 41328 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma 209684 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size 148471997 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus 148471997 # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus 200728 # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy 3128200875 # Layer occupancy (ticks)
+system.cpu.rob.rob_reads 239241509 # The number of ROB reads
+system.cpu.rob.rob_writes 195965670 # The number of ROB writes
+system.cpu.timesIdled 1778644 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 322490663 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles 4575455632 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts 60305560 # Number of Instructions Simulated
+system.cpu.committedOps 77596391 # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total 60305560 # Number of Instructions Simulated
+system.cpu.cpi 7.844723 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 7.844723 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.127474 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.127474 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 547265501 # number of integer regfile reads
+system.cpu.int_regfile_writes 87536109 # number of integer regfile writes
+system.cpu.fp_regfile_reads 8349 # number of floating regfile reads
+system.cpu.fp_regfile_writes 2916 # number of floating regfile writes
+system.cpu.misc_regfile_reads 30123194 # number of misc regfile reads
+system.cpu.misc_regfile_writes 831835 # number of misc regfile writes
+system.cpu.toL2Bus.throughput 58892076 # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq 2657368 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 2657367 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteReq 763332 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteResp 763332 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 607864 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq 2955 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::SCUpgradeReq 11 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp 2966 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 246095 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 246095 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1959479 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5796858 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 30970 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 126903 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 7914210 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 62665920 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 85541397 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 42108 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 209624 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total 148459049 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus 148459049 # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus 202780 # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy 3128672900 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 1474731013 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy 1473318251 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 2562590429 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy 2559248308 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer2.occupancy 20135737 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.occupancy 20450735 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
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-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13619.740921 # average LoadLockedReq miss latency
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+system.cpu.dcache.tags.avg_refs 33.397512 # Average number of references to valid blocks.
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
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+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13272.545455 # average StoreCondReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13272.545455 # average StoreCondReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24509.154272 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 24509.154272 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24509.154272 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 24509.154272 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.iocache.tags.replacements 0 # number of replacements
-system.iocache.tags.tagsinuse 0 # Cycle average of tags in use
-system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks.
-system.iocache.tags.avg_refs nan # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.iocache.tags.replacements 0 # number of replacements
+system.iocache.tags.tagsinuse 0 # Cycle average of tags in use
+system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
+system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks.
+system.iocache.tags.avg_refs nan # Average number of references to valid blocks.
+system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1486035968259 # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 1486035968259 # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1486035968259 # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 1486035968259 # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1424415639261 # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 1424415639261 # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1424415639261 # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 1424415639261 # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.kern.inst.arm 0 # number of arm instructions executed
-system.cpu.kern.inst.quiesce 83045 # number of quiesce instructions executed
+system.cpu.kern.inst.quiesce 83035 # number of quiesce instructions executed
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 2.403594 # Number of seconds simulated
-sim_ticks 2403594294500 # Number of ticks simulated
-final_tick 2403594294500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 2.403596 # Number of seconds simulated
+sim_ticks 2403595690000 # Number of ticks simulated
+final_tick 2403595690000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 127977 # Simulator instruction rate (inst/s)
-host_op_rate 164357 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 5098961801 # Simulator tick rate (ticks/s)
-host_mem_usage 401544 # Number of bytes of host memory used
-host_seconds 471.39 # Real time elapsed on the host
-sim_insts 60327163 # Number of instructions simulated
-sim_ops 77476179 # Number of ops (including micro ops) simulated
+host_inst_rate 160402 # Simulator instruction rate (inst/s)
+host_op_rate 206018 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 6390741250 # Simulator tick rate (ticks/s)
+host_mem_usage 398660 # Number of bytes of host memory used
+host_seconds 376.11 # Real time elapsed on the host
+sim_insts 60328186 # Number of instructions simulated
+sim_ops 77484426 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::realview.clcd 114819072 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst 511136 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 7143248 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst 511520 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 7050896 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 78528 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 688768 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.dtb.walker 384 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.inst 171584 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.data 1244640 # Number of bytes read from this memory
-system.physmem.bytes_read::total 124657616 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 511136 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 78528 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu2.inst 171584 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 761248 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 3742592 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0.data 1523692 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu1.data 157804 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu2.data 1334320 # Number of bytes written to this memory
-system.physmem.bytes_written::total 6758408 # Number of bytes written to this memory
+system.physmem.bytes_read::cpu1.inst 64832 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 677568 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.dtb.walker 448 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.itb.walker 64 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.inst 187392 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.data 1347680 # Number of bytes read from this memory
+system.physmem.bytes_read::total 124659728 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 511520 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 64832 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu2.inst 187392 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 763744 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 3743680 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu0.data 1298324 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu1.data 159300 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu2.data 1558192 # Number of bytes written to this memory
+system.physmem.bytes_written::total 6759496 # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd 14352384 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst 14189 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 111647 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst 14195 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 110204 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 1227 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 10762 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.dtb.walker 6 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.inst 2681 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.data 19455 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 14512355 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 58478 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0.data 380923 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu1.data 39451 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu2.data 333580 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 812432 # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd 47769739 # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_reads::cpu1.inst 1013 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 10587 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.dtb.walker 7 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.itb.walker 1 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.inst 2928 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.data 21065 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 14512388 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 58495 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu0.data 324581 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu1.data 39825 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu2.data 389548 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 812449 # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd 47769711 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.dtb.walker 27 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 53 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst 212655 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 2971903 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst 212814 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 2933478 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker 27 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 32671 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 286558 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.dtb.walker 160 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.inst 71386 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.data 517824 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 51863002 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 212655 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 32671 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu2.inst 71386 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 316712 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1557081 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data 633922 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1.data 65653 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu2.data 555135 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 2811792 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1557081 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd 47769739 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 26973 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 281898 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.dtb.walker 186 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.itb.walker 27 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.inst 77963 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.data 560693 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 51863851 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 212814 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 26973 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu2.inst 77963 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 317751 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 1557533 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data 540159 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1.data 66276 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu2.data 648275 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 2812243 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 1557533 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd 47769711 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker 27 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 53 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 212655 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 3605825 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 212814 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 3473637 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker 27 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 32671 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 352211 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.dtb.walker 160 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.inst 71386 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.data 1072960 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 54674794 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 13478004 # Total number of read requests seen
-system.physmem.writeReqs 390132 # Total number of write requests seen
-system.physmem.cpureqs 53582 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 862592256 # Total number of bytes read from memory
-system.physmem.bytesWritten 24968448 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 109734944 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 2586588 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite 2357 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 837777 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 837385 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 837533 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 838713 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 839756 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 839804 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 839650 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 840522 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 841715 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 844141 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 844930 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 846498 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 848135 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 848079 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 846803 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 846563 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 25455 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 25327 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2 25409 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 25902 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 26300 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5 26088 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6 25421 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 23356 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 23184 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 23261 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 21260 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11 21580 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12 24628 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13 24253 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14 23500 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15 25208 # Track writes on a per bank basis
+system.physmem.bw_total::cpu1.inst 26973 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 348173 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.dtb.walker 186 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.itb.walker 27 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.inst 77963 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.data 1208969 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 54676094 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 13479442 # Total number of read requests accepted by DRAM controller
+system.physmem.writeReqs 446461 # Total number of write requests accepted by DRAM controller
+system.physmem.readBursts 13479442 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
+system.physmem.writeBursts 446461 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
+system.physmem.bytesRead 862684288 # Total number of bytes read from memory
+system.physmem.bytesWritten 28573504 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 109828768 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 2811124 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q
+system.physmem.neitherReadNorWrite 2349 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 837727 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 837365 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 837535 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 838843 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 839834 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 839919 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 839832 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 840753 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 841921 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 844340 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 845026 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 846543 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 848256 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 848014 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 846904 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 846630 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 2743 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 2603 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 2565 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 3057 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 3449 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 3230 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 2572 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 2333 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 2233 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 2428 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 2377 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 2821 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 3826 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 3451 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 2698 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 2556 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
-system.physmem.numWrRetry 14413 # Number of times wr buffer was full causing retry
-system.physmem.totGap 2402559124000 # Total gap between requests
+system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
+system.physmem.totGap 2402560453500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 8 # Categorize read packet sizes
-system.physmem.readPktSize::3 13443872 # Categorize read packet sizes
+system.physmem.readPktSize::3 13443840 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 34124 # Categorize read packet sizes
+system.physmem.readPktSize::6 35594 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
-system.physmem.writePktSize::2 373031 # Categorize write packet sizes
+system.physmem.writePktSize::2 429373 # Categorize write packet sizes
system.physmem.writePktSize::3 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
-system.physmem.writePktSize::6 17101 # Categorize write packet sizes
-system.physmem.rdQLenPdf::0 870514 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 846629 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 868006 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 3320451 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 2492641 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 2492474 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 2466384 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 13873 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 13526 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 25989 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 38321 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11 25827 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12 858 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13 842 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14 831 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15 820 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16 15 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 17088 # Categorize write packet sizes
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system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 2518 # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::22 16918 # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::30 14430 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 14424 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 22008 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 40328.985823 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 6672.817905 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 32794.691650 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::64-95 2992 13.60% 13.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-159 1338 6.08% 19.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::192-223 840 3.82% 23.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-287 568 2.58% 26.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::320-351 356 1.62% 27.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-415 350 1.59% 29.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::448-479 274 1.25% 30.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-543 258 1.17% 31.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::576-607 159 0.72% 32.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-671 152 0.69% 33.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::704-735 129 0.59% 33.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-799 166 0.75% 34.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::832-863 85 0.39% 34.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-927 79 0.36% 35.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::960-991 56 0.25% 35.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1055 66 0.30% 35.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1088-1119 41 0.19% 35.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1152-1183 34 0.15% 36.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1216-1247 24 0.11% 36.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1280-1311 38 0.17% 36.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1344-1375 28 0.13% 36.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1408-1439 94 0.43% 36.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1472-1503 111 0.50% 37.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1536-1567 95 0.43% 37.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1600-1631 19 0.09% 37.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1664-1695 37 0.17% 38.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1728-1759 24 0.11% 38.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1792-1823 40 0.18% 38.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1856-1887 12 0.05% 38.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1920-1951 17 0.08% 38.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1984-2015 8 0.04% 38.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2048-2079 19 0.09% 38.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2112-2143 12 0.05% 38.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2176-2207 11 0.05% 38.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2240-2271 5 0.02% 38.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2304-2335 5 0.02% 38.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2368-2399 3 0.01% 38.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2432-2463 10 0.05% 38.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2496-2527 2 0.01% 38.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2560-2591 1 0.00% 38.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2624-2655 1 0.00% 38.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2688-2719 5 0.02% 38.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2752-2783 5 0.02% 38.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2816-2847 5 0.02% 38.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2880-2911 3 0.01% 38.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2944-2975 1 0.00% 38.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3008-3039 1 0.00% 38.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3072-3103 7 0.03% 39.01% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3136-3167 2 0.01% 39.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3200-3231 3 0.01% 39.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3264-3295 4 0.02% 39.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3328-3359 7 0.03% 39.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3392-3423 2 0.01% 39.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3456-3487 2 0.01% 39.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3584-3615 3 0.01% 39.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3648-3679 2 0.01% 39.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3712-3743 1 0.00% 39.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3776-3807 2 0.01% 39.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3840-3871 3 0.01% 39.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4032-4063 3 0.01% 39.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4096-4127 7 0.03% 39.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4352-4383 3 0.01% 39.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4416-4447 1 0.00% 39.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4672-4703 1 0.00% 39.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4736-4767 2 0.01% 39.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4800-4831 3 0.01% 39.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4864-4895 1 0.00% 39.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4992-5023 1 0.00% 39.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5184-5215 1 0.00% 39.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5376-5407 2 0.01% 39.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5440-5471 1 0.00% 39.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5888-5919 2 0.01% 39.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6144-6175 8 0.04% 39.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6272-6303 1 0.00% 39.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6400-6431 1 0.00% 39.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6528-6559 1 0.00% 39.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6784-6815 4 0.02% 39.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7040-7071 2 0.01% 39.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7360-7391 2 0.01% 39.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7424-7455 1 0.00% 39.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7680-7711 2 0.01% 39.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7808-7839 1 0.00% 39.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7872-7903 1 0.00% 39.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7936-7967 2 0.01% 39.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8064-8095 1 0.00% 39.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8192-8223 3 0.01% 39.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8448-8479 1 0.00% 39.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8576-8607 1 0.00% 39.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8704-8735 1 0.00% 39.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12288-12319 3 0.01% 39.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13312-13343 1 0.00% 39.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13952-13983 1 0.00% 39.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14592-14623 1 0.00% 39.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::19200-19231 1 0.00% 39.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::19456-19487 1 0.00% 39.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::19968-19999 1 0.00% 39.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::21760-21791 1 0.00% 39.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::22528-22559 2 0.01% 39.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::23296-23327 1 0.00% 39.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::23552-23583 1 0.00% 39.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::28160-28191 1 0.00% 39.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::30720-30751 1 0.00% 39.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::32000-32031 2 0.01% 39.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::33024-33055 2 0.01% 39.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::33280-33311 2 0.01% 39.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::33536-33567 2 0.01% 39.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::33792-33823 1 0.00% 39.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::34816-34847 1 0.00% 39.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::35840-35871 1 0.00% 39.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::36864-36895 1 0.00% 39.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::37888-37919 1 0.00% 39.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::38912-38943 1 0.00% 39.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::40960-40991 1 0.00% 39.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::41984-42015 1 0.00% 39.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::42752-42783 1 0.00% 39.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::46080-46111 1 0.00% 39.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::49408-49439 1 0.00% 39.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::50944-50975 1 0.00% 39.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::53248-53279 1 0.00% 39.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::54272-54303 1 0.00% 39.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::54464-54495 1 0.00% 39.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::56576-56607 1 0.00% 39.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::58240-58271 1 0.00% 39.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::58624-58655 1 0.00% 39.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::59392-59423 1 0.00% 39.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::65536-65567 13106 59.55% 99.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::131072-131103 181 0.82% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 22008 # Bytes accessed per row activation
-system.physmem.totQLat 259991264250 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 339839911750 # Sum of mem lat for all requests
-system.physmem.totBusLat 67390020000 # Total cycles spent in databus access
-system.physmem.totBankLat 12458627500 # Total cycles spent in bank access
-system.physmem.avgQLat 19290.04 # Average queueing delay per request
-system.physmem.avgBankLat 924.37 # Average bank access latency per request
+system.physmem.wrQLenPdf::0 2007 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 1997 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 1997 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 1991 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 1988 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 1985 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6 1980 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 1971 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8 1966 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9 1962 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10 1958 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11 1954 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12 1947 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13 1942 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14 1937 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 1934 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 1930 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 1926 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 1922 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 1917 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 1914 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 1909 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 1908 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples 22080 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 39201.023188 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 6463.207550 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 31878.388388 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::64-79 3036 13.75% 13.75% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-143 1347 6.10% 19.85% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::192-207 793 3.59% 23.44% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-271 589 2.67% 26.11% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::320-335 391 1.77% 27.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-399 355 1.61% 29.49% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::448-463 279 1.26% 30.75% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-527 235 1.06% 31.82% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::576-591 172 0.78% 32.60% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-655 146 0.66% 33.26% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::704-719 130 0.59% 33.85% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-783 164 0.74% 34.59% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::832-847 77 0.35% 34.94% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-911 80 0.36% 35.30% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::960-975 63 0.29% 35.58% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1039 74 0.34% 35.92% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1088-1103 30 0.14% 36.06% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1152-1167 39 0.18% 36.23% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1216-1231 22 0.10% 36.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1280-1295 39 0.18% 36.51% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1344-1359 28 0.13% 36.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1408-1423 83 0.38% 37.01% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1472-1487 95 0.43% 37.44% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1536-1551 108 0.49% 37.93% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1600-1615 17 0.08% 38.01% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1664-1679 45 0.20% 38.21% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1728-1743 23 0.10% 38.32% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1792-1807 32 0.14% 38.46% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1856-1871 10 0.05% 38.51% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1920-1935 20 0.09% 38.60% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1984-1999 6 0.03% 38.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2048-2063 23 0.10% 38.73% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2112-2127 8 0.04% 38.76% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2176-2191 15 0.07% 38.83% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2240-2255 1 0.00% 38.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2304-2319 6 0.03% 38.86% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2368-2383 4 0.02% 38.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2432-2447 10 0.05% 38.93% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2496-2511 3 0.01% 38.94% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2560-2575 2 0.01% 38.95% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2624-2639 1 0.00% 38.95% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2688-2703 3 0.01% 38.97% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2752-2767 5 0.02% 38.99% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2816-2831 8 0.04% 39.03% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2880-2895 3 0.01% 39.04% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2944-2959 3 0.01% 39.05% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3008-3023 1 0.00% 39.06% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3072-3087 6 0.03% 39.09% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3136-3151 2 0.01% 39.09% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3200-3215 2 0.01% 39.10% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3264-3279 5 0.02% 39.13% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3328-3343 6 0.03% 39.15% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3392-3407 2 0.01% 39.16% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3456-3471 3 0.01% 39.18% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3520-3535 1 0.00% 39.18% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3584-3599 2 0.01% 39.19% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3648-3663 2 0.01% 39.20% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3712-3727 2 0.01% 39.21% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3776-3791 3 0.01% 39.22% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3840-3855 1 0.00% 39.23% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4032-4047 3 0.01% 39.24% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4096-4111 7 0.03% 39.27% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4352-4367 3 0.01% 39.28% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4416-4431 1 0.00% 39.29% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4672-4687 2 0.01% 39.30% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4800-4815 2 0.01% 39.31% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4928-4943 1 0.00% 39.31% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4992-5007 2 0.01% 39.32% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5120-5135 1 0.00% 39.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5376-5391 2 0.01% 39.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5440-5455 1 0.00% 39.34% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6272-6287 1 0.00% 39.34% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6464-6479 1 0.00% 39.35% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6528-6543 3 0.01% 39.36% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6784-6799 15 0.07% 39.43% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6848-6863 2 0.01% 39.44% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6976-6991 1 0.00% 39.44% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7040-7055 3 0.01% 39.46% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7168-7183 3 0.01% 39.47% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7360-7375 2 0.01% 39.48% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7424-7439 1 0.00% 39.48% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7680-7695 1 0.00% 39.49% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7744-7759 1 0.00% 39.49% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7936-7951 2 0.01% 39.50% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::8064-8079 1 0.00% 39.51% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::8192-8207 3 0.01% 39.52% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::8448-8463 45 0.20% 39.72% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::8512-8527 150 0.68% 40.40% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::8576-8591 12 0.05% 40.46% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::8960-8975 1 0.00% 40.46% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::9216-9231 1 0.00% 40.47% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::9472-9487 1 0.00% 40.47% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::12032-12047 2 0.01% 40.48% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::14848-14863 1 0.00% 40.48% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::16320-16335 1 0.00% 40.49% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::17408-17423 1 0.00% 40.49% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::17664-17679 1 0.00% 40.50% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::20224-20239 1 0.00% 40.50% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::22784-22799 1 0.00% 40.51% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::24576-24591 1 0.00% 40.51% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::25856-25871 1 0.00% 40.52% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::27648-27663 1 0.00% 40.52% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::29440-29455 1 0.00% 40.53% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::30720-30735 2 0.01% 40.53% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::31232-31247 1 0.00% 40.54% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::33024-33039 1 0.00% 40.54% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::33280-33295 3 0.01% 40.56% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::33792-33807 1 0.00% 40.56% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::34304-34319 1 0.00% 40.57% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::34816-34831 1 0.00% 40.57% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::35840-35855 1 0.00% 40.58% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::37888-37903 1 0.00% 40.58% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::38912-38927 1 0.00% 40.58% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::40192-40207 1 0.00% 40.59% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::40960-40975 1 0.00% 40.59% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::41984-41999 1 0.00% 40.60% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::42752-42767 1 0.00% 40.60% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::47872-47887 1 0.00% 40.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::52224-52239 1 0.00% 40.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::53248-53263 1 0.00% 40.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::53504-53519 1 0.00% 40.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::56064-56079 1 0.00% 40.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::59392-59407 1 0.00% 40.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::65536-65551 13109 59.37% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 22080 # Bytes accessed per row activation
+system.physmem.totQLat 259652718750 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 339530350000 # Sum of mem lat for all requests
+system.physmem.totBusLat 67397210000 # Total cycles spent in databus access
+system.physmem.totBankLat 12480421250 # Total cycles spent in bank access
+system.physmem.avgQLat 19262.87 # Average queueing delay per request
+system.physmem.avgBankLat 925.89 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 25214.41 # Average memory access latency
-system.physmem.avgRdBW 358.88 # Average achieved read bandwidth in MB/s
-system.physmem.avgWrBW 10.39 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 45.65 # Average consumed read bandwidth in MB/s
-system.physmem.avgConsumedWrBW 1.08 # Average consumed write bandwidth in MB/s
+system.physmem.avgMemAccLat 25188.75 # Average memory access latency
+system.physmem.avgRdBW 358.91 # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW 11.89 # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW 45.69 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedWrBW 1.17 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
-system.physmem.busUtil 2.88 # Data bus utilization in percentage
+system.physmem.busUtil 2.90 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.14 # Average read queue length over time
-system.physmem.avgWrQLen 0.40 # Average write queue length over time
-system.physmem.readRowHits 13460829 # Number of row buffer hits during reads
-system.physmem.writeRowHits 385299 # Number of row buffer hits during writes
+system.physmem.avgWrQLen 0.39 # Average write queue length over time
+system.physmem.readRowHits 13462207 # Number of row buffer hits during reads
+system.physmem.writeRowHits 40077 # Number of row buffer hits during writes
system.physmem.readRowHitRate 99.87 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 98.76 # Row buffer hit rate for writes
-system.physmem.avgGap 173243.12 # Average gap between requests
+system.physmem.writeRowHitRate 8.98 # Row buffer hit rate for writes
+system.physmem.avgGap 172524.57 # Average gap between requests
system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput 55672102 # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq 13817032 # Transaction distribution
-system.membus.trans_dist::ReadResp 13817032 # Transaction distribution
-system.membus.trans_dist::WriteReq 375870 # Transaction distribution
-system.membus.trans_dist::WriteResp 375870 # Transaction distribution
-system.membus.trans_dist::Writeback 17101 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 2357 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 2357 # Transaction distribution
-system.membus.trans_dist::ReadExReq 26474 # Transaction distribution
-system.membus.trans_dist::ReadExResp 26474 # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 736448 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 836141 # Packet count per connected master and slave (bytes)
+system.membus.throughput 55673401 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 13817014 # Transaction distribution
+system.membus.trans_dist::ReadResp 13817014 # Transaction distribution
+system.membus.trans_dist::WriteReq 432240 # Transaction distribution
+system.membus.trans_dist::WriteResp 432240 # Transaction distribution
+system.membus.trans_dist::Writeback 17088 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 2349 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 2349 # Transaction distribution
+system.membus.trans_dist::ReadExReq 28007 # Transaction distribution
+system.membus.trans_dist::ReadExResp 28007 # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 736658 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 234 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total 1572823 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 26887744 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total 26887744 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::system.bridge.slave 736448 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::system.physmem.port 27723885 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::system.realview.gic.pio 234 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 28460567 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 740396 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 4770556 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 951736 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total 1688628 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 26887680 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total 26887680 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 28576308 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 740538 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 468 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::total 5511420 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 107550976 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.iocache.mem_side::total 107550976 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::system.bridge.slave 740396 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::system.physmem.port 112321532 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::system.realview.gic.pio 468 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 113062396 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 133813146 # Total data (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 5089172 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::total 5830178 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 107550720 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.iocache.mem_side::total 107550720 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total 113380898 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 133816346 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy 415491000 # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy 415555000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 14469192250 # Layer occupancy (ticks)
-system.membus.reqLayer2.utilization 0.6 # Layer utilization (%)
-system.membus.reqLayer3.occupancy 218000 # Layer occupancy (ticks)
-system.membus.reqLayer3.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer1.occupancy 1494318294 # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy 219000 # Layer occupancy (ticks)
+system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
+system.membus.reqLayer6.occupancy 14607219000 # Layer occupancy (ticks)
+system.membus.reqLayer6.utilization 0.6 # Layer utilization (%)
+system.membus.respLayer1.occupancy 1602404901 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
-system.membus.respLayer2.occupancy 30346616000 # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy 30345557250 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 1.3 # Layer utilization (%)
-system.l2c.tags.replacements 63199 # number of replacements
-system.l2c.tags.tagsinuse 50350.442050 # Cycle average of tags in use
-system.l2c.tags.total_refs 1748255 # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs 128595 # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs 13.595046 # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle 2375554811500 # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks 36868.064409 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.000018 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000124 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst 5218.650868 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data 3758.862884 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.993318 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst 721.252750 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data 766.461515 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.dtb.walker 4.929404 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.inst 1435.478788 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.data 1575.747972 # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks 0.562562 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst 0.079630 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data 0.057356 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000015 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst 0.011005 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data 0.011695 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000075 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.inst 0.021904 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.data 0.024044 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total 0.768287 # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::cpu0.dtb.walker 8900 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.itb.walker 3220 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.inst 462102 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data 166367 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.dtb.walker 2587 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.itb.walker 1159 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst 134524 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data 65754 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.dtb.walker 18045 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.itb.walker 4210 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.inst 282039 # number of ReadReq hits
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+system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 65571.038251 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.data 57728.391859 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 56914.939240 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
-system.toL2Bus.throughput 58801079 # Throughput (bytes/s)
-system.toL2Bus.trans_dist::ReadReq 1037457 # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp 1037456 # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq 375870 # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp 375870 # Transaction distribution
-system.toL2Bus.trans_dist::Writeback 275194 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq 1504 # Transaction distribution
+system.toL2Bus.throughput 58805533 # Throughput (bytes/s)
+system.toL2Bus.trans_dist::ReadReq 1021031 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 1021030 # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq 432240 # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp 432240 # Transaction distribution
+system.toL2Bus.trans_dist::Writeback 264941 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 1503 # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq 3 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp 1507 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 80165 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 80165 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 841603 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 2342492 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma 15419 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma 50807 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count 3250321 # Packet count per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 26910144 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 38454204 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma 21476 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma 82556 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size 65468380 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.data_through_bus 141234858 # Total data (bytes)
-system.toL2Bus.snoop_data_through_bus 99080 # Total snoop data (bytes)
-system.toL2Bus.reqLayer0.occupancy 2173969472 # Layer occupancy (ticks)
+system.toL2Bus.trans_dist::UpgradeResp 1506 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 80714 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 80714 # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 830128 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2423683 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 15492 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 51832 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 3321135 # Packet count per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 26541184 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 37337186 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 21748 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 84756 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size::total 63984874 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.data_through_bus 141242678 # Total data (bytes)
+system.toL2Bus.snoop_data_through_bus 102048 # Total snoop data (bytes)
+system.toL2Bus.reqLayer0.occupancy 2176255494 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy 1896208409 # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy 1870489205 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy 1871332229 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy 1849664390 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy 10065963 # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy 10070717 # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy 30326428 # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy 30771737 # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.throughput 48764132 # Throughput (bytes/s)
-system.iobus.trans_dist::ReadReq 13809327 # Transaction distribution
-system.iobus.trans_dist::ReadResp 13809327 # Transaction distribution
-system.iobus.trans_dist::WriteReq 2769 # Transaction distribution
-system.iobus.trans_dist::WriteResp 2769 # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 11368 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 3090 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 20 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 262 # Packet count per connected master and slave (bytes)
+system.iobus.throughput 48764104 # Throughput (bytes/s)
+system.iobus.trans_dist::ReadReq 13809372 # Transaction distribution
+system.iobus.trans_dist::ReadResp 13809372 # Transaction distribution
+system.iobus.trans_dist::WriteReq 2797 # Transaction distribution
+system.iobus.trans_dist::WriteResp 2797 # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 11494 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 3026 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 22 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 258 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 721420 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 721570 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 736448 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 26887744 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.clcd.dma::total 26887744 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.uart.pio 11368 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.realview_io.pio 3090 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.timer0.pio 20 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.timer1.pio 262 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.clcd.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.kmi0.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.kmi1.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.cf_ctrl.pio 721420 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.sp810_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.iocache.cpu_side 26887744 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 27624192 # Packet count per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 15332 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 6180 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 40 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 524 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 736658 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 26887680 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.clcd.dma::total 26887680 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 27624338 # Packet count per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 15458 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 6052 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 44 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 516 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 717744 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 717892 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::total 740396 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 107550976 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.realview.clcd.dma::total 107550976 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.uart.pio 15332 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.realview_io.pio 6180 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.timer0.pio 40 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.timer1.pio 524 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.clcd.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.kmi0.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.kmi1.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.cf_ctrl.pio 717744 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.sp810_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.iocache.cpu_side 107550976 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::total 108291372 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::total 740538 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 107550720 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.realview.clcd.dma::total 107550720 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::total 108291258 # Cumulative packet size per connected master and slave (bytes)
system.iobus.data_through_bus 117209190 # Total data (bytes)
-system.iobus.reqLayer0.occupancy 7942000 # Layer occupancy (ticks)
+system.iobus.reqLayer0.occupancy 8031000 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer1.occupancy 1545000 # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy 1513000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer2.occupancy 20000 # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy 22000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer3.occupancy 131000 # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy 129000 # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer4.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer6.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer7.occupancy 361211000 # Layer occupancy (ticks)
+system.iobus.reqLayer7.occupancy 361287000 # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer25.occupancy 13443872000 # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy 13443840000 # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%)
-system.iobus.respLayer0.occupancy 733679000 # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy 733861000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer1.occupancy 36855511000 # Layer occupancy (ticks)
+system.iobus.respLayer1.occupancy 36856295750 # Layer occupancy (ticks)
system.iobus.respLayer1.utilization 1.5 # Layer utilization (%)
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
-system.cpu0.dtb.read_hits 8066197 # DTB read hits
-system.cpu0.dtb.read_misses 6232 # DTB read misses
-system.cpu0.dtb.write_hits 6664992 # DTB write hits
-system.cpu0.dtb.write_misses 2050 # DTB write misses
+system.cpu0.dtb.read_hits 8004008 # DTB read hits
+system.cpu0.dtb.read_misses 6222 # DTB read misses
+system.cpu0.dtb.write_hits 6595133 # DTB write hits
+system.cpu0.dtb.write_misses 2001 # DTB write misses
system.cpu0.dtb.flush_tlb 279 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid 685 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries 5697 # Number of entries that have been flushed from TLB
+system.cpu0.dtb.flush_entries 5693 # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults 113 # Number of TLB faults due to prefetch
+system.cpu0.dtb.prefetch_faults 118 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults 212 # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses 8072429 # DTB read accesses
-system.cpu0.dtb.write_accesses 6667042 # DTB write accesses
+system.cpu0.dtb.read_accesses 8010230 # DTB read accesses
+system.cpu0.dtb.write_accesses 6597134 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu0.dtb.hits 14731189 # DTB hits
-system.cpu0.dtb.misses 8282 # DTB misses
-system.cpu0.dtb.accesses 14739471 # DTB accesses
-system.cpu0.itb.inst_hits 32886560 # ITB inst hits
-system.cpu0.itb.inst_misses 3493 # ITB inst misses
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system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000012 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.028501 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.025771 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total 0.011936 # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028501 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.025771 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total 0.011936 # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12256.839489 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12923.226949 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12711.800040 # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 29026.695305 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 32109.403745 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 30987.083191 # average WriteReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11123.954267 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 11496.873473 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11369.050086 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.028741 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.024050 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total 0.011496 # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028741 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.024050 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total 0.011496 # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12194.749762 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12898.277013 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12666.674473 # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 29432.525836 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 33228.077598 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31894.621436 # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11128.319861 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 11672.760264 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11486.733281 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 11000 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 17508.465254 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 18105.922075 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17908.414862 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 17508.465254 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 18105.922075 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17908.414862 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 17556.243480 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 18800.305768 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18382.577990 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 17556.243480 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 18800.305768 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18382.577990 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 2159851 # DTB read hits
-system.cpu1.dtb.read_misses 2083 # DTB read misses
-system.cpu1.dtb.write_hits 1460405 # DTB write hits
-system.cpu1.dtb.write_misses 373 # DTB write misses
+system.cpu1.dtb.read_hits 2098287 # DTB read hits
+system.cpu1.dtb.read_misses 2070 # DTB read misses
+system.cpu1.dtb.write_hits 1420937 # DTB write hits
+system.cpu1.dtb.write_misses 371 # DTB write misses
system.cpu1.dtb.flush_tlb 277 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid 233 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 12 # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries 1742 # Number of entries that have been flushed from TLB
+system.cpu1.dtb.flush_entries 1726 # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults 44 # Number of TLB faults due to prefetch
+system.cpu1.dtb.prefetch_faults 38 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults 78 # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses 2161934 # DTB read accesses
-system.cpu1.dtb.write_accesses 1460778 # DTB write accesses
+system.cpu1.dtb.read_accesses 2100357 # DTB read accesses
+system.cpu1.dtb.write_accesses 1421308 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dtb.hits 3620256 # DTB hits
-system.cpu1.dtb.misses 2456 # DTB misses
-system.cpu1.dtb.accesses 3622712 # DTB accesses
-system.cpu1.itb.inst_hits 8340023 # ITB inst hits
+system.cpu1.dtb.hits 3519224 # DTB hits
+system.cpu1.dtb.misses 2441 # DTB misses
+system.cpu1.dtb.accesses 3521665 # DTB accesses
+system.cpu1.itb.inst_hits 8185092 # ITB inst hits
system.cpu1.itb.inst_misses 1172 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.inst_accesses 8341195 # ITB inst accesses
-system.cpu1.itb.hits 8340023 # DTB hits
+system.cpu1.itb.inst_accesses 8186264 # ITB inst accesses
+system.cpu1.itb.hits 8185092 # DTB hits
system.cpu1.itb.misses 1172 # DTB misses
-system.cpu1.itb.accesses 8341195 # DTB accesses
-system.cpu1.numCycles 580203695 # number of cpu cycles simulated
+system.cpu1.itb.accesses 8186264 # DTB accesses
+system.cpu1.numCycles 580203625 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.committedInsts 8134078 # Number of instructions committed
-system.cpu1.committedOps 10379103 # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses 9286356 # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses 2127 # Number of float alu accesses
-system.cpu1.num_func_calls 319009 # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts 1149936 # number of instructions that are conditional controls
-system.cpu1.num_int_insts 9286356 # number of integer instructions
-system.cpu1.num_fp_insts 2127 # number of float instructions
-system.cpu1.num_int_register_reads 53580768 # number of times the integer registers were read
-system.cpu1.num_int_register_writes 10053974 # number of times the integer registers were written
-system.cpu1.num_fp_register_reads 1614 # number of times the floating registers were read
+system.cpu1.committedInsts 7980801 # Number of instructions committed
+system.cpu1.committedOps 10142634 # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses 9072894 # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses 2143 # Number of float alu accesses
+system.cpu1.num_func_calls 304668 # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts 1116676 # number of instructions that are conditional controls
+system.cpu1.num_int_insts 9072894 # number of integer instructions
+system.cpu1.num_fp_insts 2143 # number of float instructions
+system.cpu1.num_int_register_reads 52281658 # number of times the integer registers were read
+system.cpu1.num_int_register_writes 9864872 # number of times the integer registers were written
+system.cpu1.num_fp_register_reads 1630 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 514 # number of times the floating registers were written
-system.cpu1.num_mem_refs 3795930 # number of memory refs
-system.cpu1.num_load_insts 2256544 # Number of load instructions
-system.cpu1.num_store_insts 1539386 # Number of store instructions
-system.cpu1.num_idle_cycles 585938491.751716 # Number of idle cycles
-system.cpu1.num_busy_cycles -5734796.751716 # Number of busy cycles
-system.cpu1.not_idle_fraction -0.009884 # Percentage of non-idle cycles
-system.cpu1.idle_fraction 1.009884 # Percentage of idle cycles
+system.cpu1.num_mem_refs 3686646 # number of memory refs
+system.cpu1.num_load_insts 2191239 # Number of load instructions
+system.cpu1.num_store_insts 1495407 # Number of store instructions
+system.cpu1.num_idle_cycles 544226668.771142 # Number of idle cycles
+system.cpu1.num_busy_cycles 35976956.228858 # Number of busy cycles
+system.cpu1.not_idle_fraction 0.062007 # Percentage of non-idle cycles
+system.cpu1.idle_fraction 0.937993 # Percentage of idle cycles
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
-system.cpu2.branchPred.lookups 4707573 # Number of BP lookups
-system.cpu2.branchPred.condPredicted 3829869 # Number of conditional branches predicted
-system.cpu2.branchPred.condIncorrect 221083 # Number of conditional branches incorrect
-system.cpu2.branchPred.BTBLookups 3125328 # Number of BTB lookups
-system.cpu2.branchPred.BTBHits 2519731 # Number of BTB hits
+system.cpu2.branchPred.lookups 4715473 # Number of BP lookups
+system.cpu2.branchPred.condPredicted 3836739 # Number of conditional branches predicted
+system.cpu2.branchPred.condIncorrect 223495 # Number of conditional branches incorrect
+system.cpu2.branchPred.BTBLookups 3141743 # Number of BTB lookups
+system.cpu2.branchPred.BTBHits 2527502 # Number of BTB hits
system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu2.branchPred.BTBHitPct 80.622930 # BTB Hit Percentage
-system.cpu2.branchPred.usedRAS 410392 # Number of times the RAS was used to get a target.
-system.cpu2.branchPred.RASInCorrect 21556 # Number of incorrect RAS predictions.
+system.cpu2.branchPred.BTBHitPct 80.449037 # BTB Hit Percentage
+system.cpu2.branchPred.usedRAS 411571 # Number of times the RAS was used to get a target.
+system.cpu2.branchPred.RASInCorrect 21589 # Number of incorrect RAS predictions.
system.cpu2.dtb.inst_hits 0 # ITB inst hits
system.cpu2.dtb.inst_misses 0 # ITB inst misses
-system.cpu2.dtb.read_hits 10881991 # DTB read hits
-system.cpu2.dtb.read_misses 22472 # DTB read misses
-system.cpu2.dtb.write_hits 3235005 # DTB write hits
-system.cpu2.dtb.write_misses 5987 # DTB write misses
+system.cpu2.dtb.read_hits 10976033 # DTB read hits
+system.cpu2.dtb.read_misses 22752 # DTB read misses
+system.cpu2.dtb.write_hits 3346841 # DTB write hits
+system.cpu2.dtb.write_misses 6453 # DTB write misses
system.cpu2.dtb.flush_tlb 276 # Number of times complete TLB was flushed
system.cpu2.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu2.dtb.flush_tlb_mva_asid 521 # Number of times TLB was flushed by MVA & ASID
system.cpu2.dtb.flush_tlb_asid 21 # Number of times TLB was flushed by ASID
-system.cpu2.dtb.flush_entries 2290 # Number of entries that have been flushed from TLB
-system.cpu2.dtb.align_faults 674 # Number of TLB faults due to alignment restrictions
-system.cpu2.dtb.prefetch_faults 165 # Number of TLB faults due to prefetch
+system.cpu2.dtb.flush_entries 2303 # Number of entries that have been flushed from TLB
+system.cpu2.dtb.align_faults 671 # Number of TLB faults due to alignment restrictions
+system.cpu2.dtb.prefetch_faults 173 # Number of TLB faults due to prefetch
system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu2.dtb.perms_faults 480 # Number of TLB faults due to permissions restrictions
-system.cpu2.dtb.read_accesses 10904463 # DTB read accesses
-system.cpu2.dtb.write_accesses 3240992 # DTB write accesses
+system.cpu2.dtb.perms_faults 460 # Number of TLB faults due to permissions restrictions
+system.cpu2.dtb.read_accesses 10998785 # DTB read accesses
+system.cpu2.dtb.write_accesses 3353294 # DTB write accesses
system.cpu2.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu2.dtb.hits 14116996 # DTB hits
-system.cpu2.dtb.misses 28459 # DTB misses
-system.cpu2.dtb.accesses 14145455 # DTB accesses
-system.cpu2.itb.inst_hits 3987789 # ITB inst hits
-system.cpu2.itb.inst_misses 4600 # ITB inst misses
+system.cpu2.dtb.hits 14322874 # DTB hits
+system.cpu2.dtb.misses 29205 # DTB misses
+system.cpu2.dtb.accesses 14352079 # DTB accesses
+system.cpu2.itb.inst_hits 4041881 # ITB inst hits
+system.cpu2.itb.inst_misses 4586 # ITB inst misses
system.cpu2.itb.read_hits 0 # DTB read hits
system.cpu2.itb.read_misses 0 # DTB read misses
system.cpu2.itb.write_hits 0 # DTB write hits
system.cpu2.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu2.itb.flush_tlb_mva_asid 521 # Number of times TLB was flushed by MVA & ASID
system.cpu2.itb.flush_tlb_asid 21 # Number of times TLB was flushed by ASID
-system.cpu2.itb.flush_entries 1704 # Number of entries that have been flushed from TLB
+system.cpu2.itb.flush_entries 1634 # Number of entries that have been flushed from TLB
system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu2.itb.perms_faults 1012 # Number of TLB faults due to permissions restrictions
+system.cpu2.itb.perms_faults 1002 # Number of TLB faults due to permissions restrictions
system.cpu2.itb.read_accesses 0 # DTB read accesses
system.cpu2.itb.write_accesses 0 # DTB write accesses
-system.cpu2.itb.inst_accesses 3992389 # ITB inst accesses
-system.cpu2.itb.hits 3987789 # DTB hits
-system.cpu2.itb.misses 4600 # DTB misses
-system.cpu2.itb.accesses 3992389 # DTB accesses
-system.cpu2.numCycles 88356031 # number of cpu cycles simulated
+system.cpu2.itb.inst_accesses 4046467 # ITB inst accesses
+system.cpu2.itb.hits 4041881 # DTB hits
+system.cpu2.itb.misses 4586 # DTB misses
+system.cpu2.itb.accesses 4046467 # DTB accesses
+system.cpu2.numCycles 88343562 # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu2.fetch.icacheStallCycles 9299223 # Number of cycles fetch is stalled on an Icache miss
-system.cpu2.fetch.Insts 32583630 # Number of instructions fetch has processed
-system.cpu2.fetch.Branches 4707573 # Number of branches that fetch encountered
-system.cpu2.fetch.predictedBranches 2930123 # Number of branches that fetch has predicted taken
-system.cpu2.fetch.Cycles 6845670 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu2.fetch.SquashCycles 1836223 # Number of cycles fetch has spent squashing
-system.cpu2.fetch.TlbCycles 50265 # Number of cycles fetch has spent waiting for tlb
-system.cpu2.fetch.BlockedCycles 18768642 # Number of cycles fetch has spent blocked
-system.cpu2.fetch.MiscStallCycles 458 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu2.fetch.PendingDrainCycles 865 # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu2.fetch.PendingTrapStallCycles 32747 # Number of stall cycles due to pending traps
-system.cpu2.fetch.PendingQuiesceStallCycles 722165 # Number of stall cycles due to pending quiesce instructions
-system.cpu2.fetch.IcacheWaitRetryStallCycles 468 # Number of stall cycles due to full MSHR
-system.cpu2.fetch.CacheLines 3986309 # Number of cache lines fetched
-system.cpu2.fetch.IcacheSquashes 272069 # Number of outstanding Icache misses that were squashed
-system.cpu2.fetch.ItlbSquashes 2032 # Number of outstanding ITLB misses that were squashed
-system.cpu2.fetch.rateDist::samples 36980430 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::mean 1.055775 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::stdev 2.444098 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.icacheStallCycles 9345666 # Number of cycles fetch is stalled on an Icache miss
+system.cpu2.fetch.Insts 32463757 # Number of instructions fetch has processed
+system.cpu2.fetch.Branches 4715473 # Number of branches that fetch encountered
+system.cpu2.fetch.predictedBranches 2939073 # Number of branches that fetch has predicted taken
+system.cpu2.fetch.Cycles 6849430 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu2.fetch.SquashCycles 1758819 # Number of cycles fetch has spent squashing
+system.cpu2.fetch.TlbCycles 50954 # Number of cycles fetch has spent waiting for tlb
+system.cpu2.fetch.BlockedCycles 18707448 # Number of cycles fetch has spent blocked
+system.cpu2.fetch.MiscStallCycles 397 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu2.fetch.PendingDrainCycles 820 # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu2.fetch.PendingTrapStallCycles 32452 # Number of stall cycles due to pending traps
+system.cpu2.fetch.PendingQuiesceStallCycles 720275 # Number of stall cycles due to pending quiesce instructions
+system.cpu2.fetch.IcacheWaitRetryStallCycles 489 # Number of stall cycles due to full MSHR
+system.cpu2.fetch.CacheLines 4040467 # Number of cache lines fetched
+system.cpu2.fetch.IcacheSquashes 290046 # Number of outstanding Icache misses that were squashed
+system.cpu2.fetch.ItlbSquashes 2014 # Number of outstanding ITLB misses that were squashed
+system.cpu2.fetch.rateDist::samples 36916106 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::mean 1.056921 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::stdev 2.443441 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::0 30139736 81.50% 81.50% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::1 382786 1.04% 82.54% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::2 509834 1.38% 83.92% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::3 817196 2.21% 86.13% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::4 649833 1.76% 87.88% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::5 340544 0.92% 88.80% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::6 1001875 2.71% 91.51% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::7 233328 0.63% 92.14% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::8 2905298 7.86% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::0 30071749 81.46% 81.46% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::1 384570 1.04% 82.50% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::2 513519 1.39% 83.89% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::3 818109 2.22% 86.11% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::4 634612 1.72% 87.83% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::5 341178 0.92% 88.75% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::6 1041484 2.82% 91.57% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::7 228835 0.62% 92.19% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::8 2882050 7.81% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::total 36980430 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.branchRate 0.053280 # Number of branch fetches per cycle
-system.cpu2.fetch.rate 0.368777 # Number of inst fetches per cycle
-system.cpu2.decode.IdleCycles 9914058 # Number of cycles decode is idle
-system.cpu2.decode.BlockedCycles 19374148 # Number of cycles decode is blocked
-system.cpu2.decode.RunCycles 6194025 # Number of cycles decode is running
-system.cpu2.decode.UnblockCycles 289491 # Number of cycles decode is unblocking
-system.cpu2.decode.SquashCycles 1207748 # Number of cycles decode is squashing
-system.cpu2.decode.BranchResolved 608647 # Number of times decode resolved a branch
-system.cpu2.decode.BranchMispred 53413 # Number of times decode detected a branch misprediction
-system.cpu2.decode.DecodedInsts 36680754 # Number of instructions handled by decode
-system.cpu2.decode.SquashedInsts 180211 # Number of squashed instructions handled by decode
-system.cpu2.rename.SquashCycles 1207748 # Number of cycles rename is squashing
-system.cpu2.rename.IdleCycles 10448619 # Number of cycles rename is idle
-system.cpu2.rename.BlockCycles 6814881 # Number of cycles rename is blocking
-system.cpu2.rename.serializeStallCycles 11054882 # count of cycles rename stalled for serializing inst
-system.cpu2.rename.RunCycles 5930497 # Number of cycles rename is running
-system.cpu2.rename.UnblockCycles 1522855 # Number of cycles rename is unblocking
-system.cpu2.rename.RenamedInsts 34729839 # Number of instructions processed by rename
-system.cpu2.rename.ROBFullEvents 2439 # Number of times rename has blocked due to ROB full
-system.cpu2.rename.IQFullEvents 374808 # Number of times rename has blocked due to IQ full
-system.cpu2.rename.LSQFullEvents 885539 # Number of times rename has blocked due to LSQ full
-system.cpu2.rename.FullRegisterEvents 119 # Number of times there has been no free registers
-system.cpu2.rename.RenamedOperands 37310430 # Number of destination operands rename has renamed
-system.cpu2.rename.RenameLookups 158812282 # Number of register rename lookups that rename has made
-system.cpu2.rename.int_rename_lookups 158784890 # Number of integer rename lookups
-system.cpu2.rename.fp_rename_lookups 27392 # Number of floating rename lookups
-system.cpu2.rename.CommittedMaps 25602072 # Number of HB maps that are committed
-system.cpu2.rename.UndoneMaps 11708357 # Number of HB maps that are undone due to squashing
-system.cpu2.rename.serializingInsts 230914 # count of serializing insts renamed
-system.cpu2.rename.tempSerializingInsts 207478 # count of temporary serializing insts renamed
-system.cpu2.rename.skidInsts 3294482 # count of insts added to the skid buffer
-system.cpu2.memDep0.insertedLoads 6519802 # Number of loads inserted to the mem dependence unit.
-system.cpu2.memDep0.insertedStores 3791560 # Number of stores inserted to the mem dependence unit.
-system.cpu2.memDep0.conflictingLoads 528920 # Number of conflicting loads.
-system.cpu2.memDep0.conflictingStores 689934 # Number of conflicting stores.
-system.cpu2.iq.iqInstsAdded 31598942 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu2.iq.iqNonSpecInstsAdded 510602 # Number of non-speculative instructions added to the IQ
-system.cpu2.iq.iqInstsIssued 34143520 # Number of instructions issued
-system.cpu2.iq.iqSquashedInstsIssued 55455 # Number of squashed instructions issued
-system.cpu2.iq.iqSquashedInstsExamined 7440971 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu2.iq.iqSquashedOperandsExamined 19631999 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu2.iq.iqSquashedNonSpecRemoved 154198 # Number of squashed non-spec instructions that were removed
-system.cpu2.iq.issued_per_cycle::samples 36980430 # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::mean 0.923286 # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::stdev 1.579350 # Number of insts issued each cycle
+system.cpu2.fetch.rateDist::total 36916106 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.branchRate 0.053377 # Number of branch fetches per cycle
+system.cpu2.fetch.rate 0.367472 # Number of inst fetches per cycle
+system.cpu2.decode.IdleCycles 9928442 # Number of cycles decode is idle
+system.cpu2.decode.BlockedCycles 19318553 # Number of cycles decode is blocked
+system.cpu2.decode.RunCycles 6233841 # Number of cycles decode is running
+system.cpu2.decode.UnblockCycles 278394 # Number of cycles decode is unblocking
+system.cpu2.decode.SquashCycles 1155918 # Number of cycles decode is squashing
+system.cpu2.decode.BranchResolved 607967 # Number of times decode resolved a branch
+system.cpu2.decode.BranchMispred 53425 # Number of times decode detected a branch misprediction
+system.cpu2.decode.DecodedInsts 36920328 # Number of instructions handled by decode
+system.cpu2.decode.SquashedInsts 180410 # Number of squashed instructions handled by decode
+system.cpu2.rename.SquashCycles 1155918 # Number of cycles rename is squashing
+system.cpu2.rename.IdleCycles 10478416 # Number of cycles rename is idle
+system.cpu2.rename.BlockCycles 6754031 # Number of cycles rename is blocking
+system.cpu2.rename.serializeStallCycles 11105712 # count of cycles rename stalled for serializing inst
+system.cpu2.rename.RunCycles 5942637 # Number of cycles rename is running
+system.cpu2.rename.UnblockCycles 1478447 # Number of cycles rename is unblocking
+system.cpu2.rename.RenamedInsts 34829842 # Number of instructions processed by rename
+system.cpu2.rename.ROBFullEvents 2448 # Number of times rename has blocked due to ROB full
+system.cpu2.rename.IQFullEvents 324847 # Number of times rename has blocked due to IQ full
+system.cpu2.rename.LSQFullEvents 890462 # Number of times rename has blocked due to LSQ full
+system.cpu2.rename.FullRegisterEvents 131 # Number of times there has been no free registers
+system.cpu2.rename.RenamedOperands 37304234 # Number of destination operands rename has renamed
+system.cpu2.rename.RenameLookups 159387361 # Number of register rename lookups that rename has made
+system.cpu2.rename.int_rename_lookups 159360013 # Number of integer rename lookups
+system.cpu2.rename.fp_rename_lookups 27348 # Number of floating rename lookups
+system.cpu2.rename.CommittedMaps 26430435 # Number of HB maps that are committed
+system.cpu2.rename.UndoneMaps 10873798 # Number of HB maps that are undone due to squashing
+system.cpu2.rename.serializingInsts 231762 # count of serializing insts renamed
+system.cpu2.rename.tempSerializingInsts 208068 # count of temporary serializing insts renamed
+system.cpu2.rename.skidInsts 3242623 # count of insts added to the skid buffer
+system.cpu2.memDep0.insertedLoads 6608021 # Number of loads inserted to the mem dependence unit.
+system.cpu2.memDep0.insertedStores 3899448 # Number of stores inserted to the mem dependence unit.
+system.cpu2.memDep0.conflictingLoads 530191 # Number of conflicting loads.
+system.cpu2.memDep0.conflictingStores 761841 # Number of conflicting stores.
+system.cpu2.iq.iqInstsAdded 32138723 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu2.iq.iqNonSpecInstsAdded 510591 # Number of non-speculative instructions added to the IQ
+system.cpu2.iq.iqInstsIssued 34782251 # Number of instructions issued
+system.cpu2.iq.iqSquashedInstsIssued 56051 # Number of squashed instructions issued
+system.cpu2.iq.iqSquashedInstsExamined 7186073 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu2.iq.iqSquashedOperandsExamined 19057300 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu2.iq.iqSquashedNonSpecRemoved 153940 # Number of squashed non-spec instructions that were removed
+system.cpu2.iq.issued_per_cycle::samples 36916106 # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::mean 0.942197 # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::stdev 1.600639 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::0 24453619 66.13% 66.13% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::1 3907365 10.57% 76.69% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::2 2316831 6.27% 82.96% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::3 2013006 5.44% 88.40% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::4 2745101 7.42% 95.82% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::5 885827 2.40% 98.22% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::6 492123 1.33% 99.55% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::7 131266 0.35% 99.90% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::8 35292 0.10% 100.00% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::0 24329752 65.91% 65.91% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::1 3820331 10.35% 76.25% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::2 2317804 6.28% 82.53% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::3 2003808 5.43% 87.96% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::4 2797781 7.58% 95.54% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::5 970796 2.63% 98.17% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::6 496090 1.34% 99.51% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::7 144708 0.39% 99.91% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::8 35036 0.09% 100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::total 36980430 # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::total 36916106 # Number of insts issued each cycle
system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntAlu 18547 1.21% 1.21% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntMult 1 0.00% 1.21% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntDiv 0 0.00% 1.21% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatAdd 0 0.00% 1.21% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCmp 0 0.00% 1.21% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCvt 0 0.00% 1.21% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatMult 0 0.00% 1.21% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatDiv 0 0.00% 1.21% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 1.21% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAdd 0 0.00% 1.21% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 1.21% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAlu 0 0.00% 1.21% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCmp 0 0.00% 1.21% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCvt 0 0.00% 1.21% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMisc 0 0.00% 1.21% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMult 0 0.00% 1.21% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 1.21% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShift 0 0.00% 1.21% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 1.21% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 1.21% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 1.21% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 1.21% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 1.21% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 1.21% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 1.21% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 1.21% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 1.21% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.21% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 1.21% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemRead 1407485 91.52% 92.73% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemWrite 111832 7.27% 100.00% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntAlu 19314 1.26% 1.26% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntMult 1 0.00% 1.26% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntDiv 0 0.00% 1.26% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatAdd 0 0.00% 1.26% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCmp 0 0.00% 1.26% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCvt 0 0.00% 1.26% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatMult 0 0.00% 1.26% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatDiv 0 0.00% 1.26% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 1.26% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAdd 0 0.00% 1.26% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 1.26% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAlu 0 0.00% 1.26% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCmp 0 0.00% 1.26% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCvt 0 0.00% 1.26% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMisc 0 0.00% 1.26% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMult 0 0.00% 1.26% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 1.26% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShift 0 0.00% 1.26% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 1.26% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 1.26% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 1.26% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 1.26% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 1.26% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 1.26% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 1.26% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 1.26% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 1.26% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.26% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 1.26% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemRead 1407095 91.52% 92.77% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemWrite 111138 7.23% 100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu2.iq.FU_type_0::No_OpClass 61314 0.18% 0.18% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntAlu 19310512 56.56% 56.74% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntMult 26216 0.08% 56.81% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 56.81% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 56.81% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 56.81% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 56.81% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 56.81% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 56.81% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 56.81% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 56.81% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 56.81% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 56.81% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 56.81% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 56.81% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMisc 4 0.00% 56.81% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 56.81% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 56.81% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 56.81% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShiftAcc 4 0.00% 56.81% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 56.81% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.81% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.81% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.81% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.81% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.81% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMisc 372 0.00% 56.81% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 56.81% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 56.81% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.81% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemRead 11345203 33.23% 90.04% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemWrite 3399891 9.96% 100.00% # Type of FU issued
+system.cpu2.iq.FU_type_0::No_OpClass 61377 0.18% 0.18% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntAlu 19718575 56.69% 56.87% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntMult 27760 0.08% 56.95% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 56.95% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 56.95% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 56.95% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 56.95% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 56.95% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 56.95% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 56.95% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 56.95% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 56.95% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 56.95% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 56.95% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 56.95% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMisc 10 0.00% 56.95% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 56.95% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 56.95% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 56.95% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShiftAcc 9 0.00% 56.95% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 56.95% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.95% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.95% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.95% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.95% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.95% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMisc 371 0.00% 56.95% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 56.95% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMultAcc 9 0.00% 56.95% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.95% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemRead 11459171 32.95% 89.89% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemWrite 3514969 10.11% 100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::total 34143520 # Type of FU issued
-system.cpu2.iq.rate 0.386431 # Inst issue rate
-system.cpu2.iq.fu_busy_cnt 1537865 # FU busy when requested
-system.cpu2.iq.fu_busy_rate 0.045041 # FU busy rate (busy events/executed inst)
-system.cpu2.iq.int_inst_queue_reads 106882112 # Number of integer instruction queue reads
-system.cpu2.iq.int_inst_queue_writes 39555566 # Number of integer instruction queue writes
-system.cpu2.iq.int_inst_queue_wakeup_accesses 27370238 # Number of integer instruction queue wakeup accesses
-system.cpu2.iq.fp_inst_queue_reads 7010 # Number of floating instruction queue reads
-system.cpu2.iq.fp_inst_queue_writes 3779 # Number of floating instruction queue writes
-system.cpu2.iq.fp_inst_queue_wakeup_accesses 3144 # Number of floating instruction queue wakeup accesses
-system.cpu2.iq.int_alu_accesses 35616337 # Number of integer alu accesses
-system.cpu2.iq.fp_alu_accesses 3734 # Number of floating point alu accesses
-system.cpu2.iew.lsq.thread0.forwLoads 206224 # Number of loads that had data forwarded from stores
+system.cpu2.iq.FU_type_0::total 34782251 # Type of FU issued
+system.cpu2.iq.rate 0.393716 # Inst issue rate
+system.cpu2.iq.fu_busy_cnt 1537548 # FU busy when requested
+system.cpu2.iq.fu_busy_rate 0.044205 # FU busy rate (busy events/executed inst)
+system.cpu2.iq.int_inst_queue_reads 108096303 # Number of integer instruction queue reads
+system.cpu2.iq.int_inst_queue_writes 39840742 # Number of integer instruction queue writes
+system.cpu2.iq.int_inst_queue_wakeup_accesses 28020326 # Number of integer instruction queue wakeup accesses
+system.cpu2.iq.fp_inst_queue_reads 6981 # Number of floating instruction queue reads
+system.cpu2.iq.fp_inst_queue_writes 3693 # Number of floating instruction queue writes
+system.cpu2.iq.fp_inst_queue_wakeup_accesses 3127 # Number of floating instruction queue wakeup accesses
+system.cpu2.iq.int_alu_accesses 36254698 # Number of integer alu accesses
+system.cpu2.iq.fp_alu_accesses 3724 # Number of floating point alu accesses
+system.cpu2.iew.lsq.thread0.forwLoads 204617 # Number of loads that had data forwarded from stores
system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu2.iew.lsq.thread0.squashedLoads 1563789 # Number of loads squashed
-system.cpu2.iew.lsq.thread0.ignoredResponses 2001 # Number of memory responses ignored because the instruction is squashed
-system.cpu2.iew.lsq.thread0.memOrderViolation 9138 # Number of memory ordering violations
-system.cpu2.iew.lsq.thread0.squashedStores 567371 # Number of stores squashed
+system.cpu2.iew.lsq.thread0.squashedLoads 1527306 # Number of loads squashed
+system.cpu2.iew.lsq.thread0.ignoredResponses 1908 # Number of memory responses ignored because the instruction is squashed
+system.cpu2.iew.lsq.thread0.memOrderViolation 9375 # Number of memory ordering violations
+system.cpu2.iew.lsq.thread0.squashedStores 562929 # Number of stores squashed
system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu2.iew.lsq.thread0.rescheduledLoads 5351721 # Number of loads that were rescheduled
-system.cpu2.iew.lsq.thread0.cacheBlocked 380538 # Number of times an access to memory failed due to the cache being blocked
+system.cpu2.iew.lsq.thread0.rescheduledLoads 5348773 # Number of loads that were rescheduled
+system.cpu2.iew.lsq.thread0.cacheBlocked 344308 # Number of times an access to memory failed due to the cache being blocked
system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu2.iew.iewSquashCycles 1207748 # Number of cycles IEW is squashing
-system.cpu2.iew.iewBlockCycles 5118466 # Number of cycles IEW is blocking
-system.cpu2.iew.iewUnblockCycles 92736 # Number of cycles IEW is unblocking
-system.cpu2.iew.iewDispatchedInsts 32192718 # Number of instructions dispatched to IQ
-system.cpu2.iew.iewDispSquashedInsts 58170 # Number of squashed instructions skipped by dispatch
-system.cpu2.iew.iewDispLoadInsts 6519802 # Number of dispatched load instructions
-system.cpu2.iew.iewDispStoreInsts 3791560 # Number of dispatched store instructions
-system.cpu2.iew.iewDispNonSpecInsts 368228 # Number of dispatched non-speculative instructions
-system.cpu2.iew.iewIQFullEvents 31927 # Number of times the IQ has become full, causing a stall
-system.cpu2.iew.iewLSQFullEvents 2425 # Number of times the LSQ has become full, causing a stall
-system.cpu2.iew.memOrderViolationEvents 9138 # Number of memory order violations
-system.cpu2.iew.predictedTakenIncorrect 105201 # Number of branches that were predicted taken incorrectly
-system.cpu2.iew.predictedNotTakenIncorrect 88411 # Number of branches that were predicted not taken incorrectly
-system.cpu2.iew.branchMispredicts 193612 # Number of branch mispredicts detected at execute
-system.cpu2.iew.iewExecutedInsts 33245955 # Number of executed instructions
-system.cpu2.iew.iewExecLoadInsts 11093572 # Number of load instructions executed
-system.cpu2.iew.iewExecSquashedInsts 897565 # Number of squashed instructions skipped in execute
+system.cpu2.iew.iewSquashCycles 1155918 # Number of cycles IEW is squashing
+system.cpu2.iew.iewBlockCycles 5077664 # Number of cycles IEW is blocking
+system.cpu2.iew.iewUnblockCycles 88593 # Number of cycles IEW is unblocking
+system.cpu2.iew.iewDispatchedInsts 32732277 # Number of instructions dispatched to IQ
+system.cpu2.iew.iewDispSquashedInsts 60627 # Number of squashed instructions skipped by dispatch
+system.cpu2.iew.iewDispLoadInsts 6608021 # Number of dispatched load instructions
+system.cpu2.iew.iewDispStoreInsts 3899448 # Number of dispatched store instructions
+system.cpu2.iew.iewDispNonSpecInsts 368370 # Number of dispatched non-speculative instructions
+system.cpu2.iew.iewIQFullEvents 29616 # Number of times the IQ has become full, causing a stall
+system.cpu2.iew.iewLSQFullEvents 2740 # Number of times the LSQ has become full, causing a stall
+system.cpu2.iew.memOrderViolationEvents 9375 # Number of memory order violations
+system.cpu2.iew.predictedTakenIncorrect 107393 # Number of branches that were predicted taken incorrectly
+system.cpu2.iew.predictedNotTakenIncorrect 89251 # Number of branches that were predicted not taken incorrectly
+system.cpu2.iew.branchMispredicts 196644 # Number of branch mispredicts detected at execute
+system.cpu2.iew.iewExecutedInsts 33865771 # Number of executed instructions
+system.cpu2.iew.iewExecLoadInsts 11188559 # Number of load instructions executed
+system.cpu2.iew.iewExecSquashedInsts 916480 # Number of squashed instructions skipped in execute
system.cpu2.iew.exec_swp 0 # number of swp insts executed
-system.cpu2.iew.exec_nop 83174 # number of nop insts executed
-system.cpu2.iew.exec_refs 14459722 # number of memory reference insts executed
-system.cpu2.iew.exec_branches 3671566 # Number of branches executed
-system.cpu2.iew.exec_stores 3366150 # Number of stores executed
-system.cpu2.iew.exec_rate 0.376273 # Inst execution rate
-system.cpu2.iew.wb_sent 32817620 # cumulative count of insts sent to commit
-system.cpu2.iew.wb_count 27373382 # cumulative count of insts written-back
-system.cpu2.iew.wb_producers 15610718 # num instructions producing a value
-system.cpu2.iew.wb_consumers 28284338 # num instructions consuming a value
+system.cpu2.iew.exec_nop 82963 # number of nop insts executed
+system.cpu2.iew.exec_refs 14669578 # number of memory reference insts executed
+system.cpu2.iew.exec_branches 3700003 # Number of branches executed
+system.cpu2.iew.exec_stores 3481019 # Number of stores executed
+system.cpu2.iew.exec_rate 0.383342 # Inst execution rate
+system.cpu2.iew.wb_sent 33465265 # cumulative count of insts sent to commit
+system.cpu2.iew.wb_count 28023453 # cumulative count of insts written-back
+system.cpu2.iew.wb_producers 16087448 # num instructions producing a value
+system.cpu2.iew.wb_consumers 29114707 # num instructions consuming a value
system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu2.iew.wb_rate 0.309808 # insts written-back per cycle
-system.cpu2.iew.wb_fanout 0.551921 # average fanout of values written-back
+system.cpu2.iew.wb_rate 0.317210 # insts written-back per cycle
+system.cpu2.iew.wb_fanout 0.552554 # average fanout of values written-back
system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu2.commit.commitSquashedInsts 7382656 # The number of squashed insts skipped by commit
-system.cpu2.commit.commitNonSpecStalls 356404 # The number of times commit has been forced to stall to communicate backwards
-system.cpu2.commit.branchMispredicts 168463 # The number of times a branch was mispredicted
-system.cpu2.commit.committed_per_cycle::samples 35772498 # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::mean 0.686059 # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::stdev 1.714745 # Number of insts commited each cycle
+system.cpu2.commit.commitSquashedInsts 7129352 # The number of squashed insts skipped by commit
+system.cpu2.commit.commitNonSpecStalls 356651 # The number of times commit has been forced to stall to communicate backwards
+system.cpu2.commit.branchMispredicts 170839 # The number of times a branch was mispredicted
+system.cpu2.commit.committed_per_cycle::samples 35759991 # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::mean 0.708498 # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::stdev 1.752281 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::0 27202420 76.04% 76.04% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::1 4136400 11.56% 87.61% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::2 1256838 3.51% 91.12% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::3 645513 1.80% 92.92% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::4 564789 1.58% 94.50% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::5 319868 0.89% 95.40% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::6 386889 1.08% 96.48% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::7 302652 0.85% 97.32% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::8 957129 2.68% 100.00% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::0 27025739 75.58% 75.58% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::1 4219923 11.80% 87.38% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::2 1248297 3.49% 90.87% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::3 635334 1.78% 92.64% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::4 557295 1.56% 94.20% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::5 319233 0.89% 95.09% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::6 417712 1.17% 96.26% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::7 309905 0.87% 97.13% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::8 1026553 2.87% 100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::total 35772498 # Number of insts commited each cycle
-system.cpu2.commit.committedInsts 19845047 # Number of instructions committed
-system.cpu2.commit.committedOps 24542041 # Number of ops (including micro ops) committed
+system.cpu2.commit.committed_per_cycle::total 35759991 # Number of insts commited each cycle
+system.cpu2.commit.committedInsts 20506693 # Number of instructions committed
+system.cpu2.commit.committedOps 25335895 # Number of ops (including micro ops) committed
system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu2.commit.refs 8180202 # Number of memory references committed
-system.cpu2.commit.loads 4956013 # Number of loads committed
-system.cpu2.commit.membars 94398 # Number of memory barriers committed
-system.cpu2.commit.branches 3153060 # Number of branches committed
-system.cpu2.commit.fp_insts 3107 # Number of committed floating point instructions.
-system.cpu2.commit.int_insts 21774748 # Number of committed integer instructions.
-system.cpu2.commit.function_calls 294560 # Number of function calls committed.
-system.cpu2.commit.bw_lim_events 957129 # number cycles where commit BW limit reached
+system.cpu2.commit.refs 8417234 # Number of memory references committed
+system.cpu2.commit.loads 5080715 # Number of loads committed
+system.cpu2.commit.membars 94304 # Number of memory barriers committed
+system.cpu2.commit.branches 3173719 # Number of branches committed
+system.cpu2.commit.fp_insts 3091 # Number of committed floating point instructions.
+system.cpu2.commit.int_insts 22548127 # Number of committed integer instructions.
+system.cpu2.commit.function_calls 294799 # Number of function calls committed.
+system.cpu2.commit.bw_lim_events 1026553 # number cycles where commit BW limit reached
system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu2.rob.rob_reads 66215885 # The number of ROB reads
-system.cpu2.rob.rob_writes 65102408 # The number of ROB writes
-system.cpu2.timesIdled 362250 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu2.idleCycles 51375601 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu2.quiesceCycles 3556629546 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu2.committedInsts 19789566 # Number of Instructions Simulated
-system.cpu2.committedOps 24486560 # Number of Ops (including micro ops) Simulated
-system.cpu2.committedInsts_total 19789566 # Number of Instructions Simulated
-system.cpu2.cpi 4.464779 # CPI: Cycles Per Instruction
-system.cpu2.cpi_total 4.464779 # CPI: Total CPI of All Threads
-system.cpu2.ipc 0.223975 # IPC: Instructions Per Cycle
-system.cpu2.ipc_total 0.223975 # IPC: Total IPC of All Threads
-system.cpu2.int_regfile_reads 153595531 # number of integer regfile reads
-system.cpu2.int_regfile_writes 29235365 # number of integer regfile writes
-system.cpu2.fp_regfile_reads 22348 # number of floating regfile reads
-system.cpu2.fp_regfile_writes 20810 # number of floating regfile writes
-system.cpu2.misc_regfile_reads 8997423 # number of misc regfile reads
-system.cpu2.misc_regfile_writes 241258 # number of misc regfile writes
-system.iocache.tags.replacements 0 # number of replacements
-system.iocache.tags.tagsinuse 0 # Cycle average of tags in use
-system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks.
-system.iocache.tags.avg_refs nan # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu2.rob.rob_reads 66675347 # The number of ROB reads
+system.cpu2.rob.rob_writes 66130617 # The number of ROB writes
+system.cpu2.timesIdled 360964 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu2.idleCycles 51427456 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu2.quiesceCycles 3556668435 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu2.committedInsts 20451214 # Number of Instructions Simulated
+system.cpu2.committedOps 25280416 # Number of Ops (including micro ops) Simulated
+system.cpu2.committedInsts_total 20451214 # Number of Instructions Simulated
+system.cpu2.cpi 4.319722 # CPI: Cycles Per Instruction
+system.cpu2.cpi_total 4.319722 # CPI: Total CPI of All Threads
+system.cpu2.ipc 0.231496 # IPC: Instructions Per Cycle
+system.cpu2.ipc_total 0.231496 # IPC: Total IPC of All Threads
+system.cpu2.int_regfile_reads 156902302 # number of integer regfile reads
+system.cpu2.int_regfile_writes 29839836 # number of integer regfile writes
+system.cpu2.fp_regfile_reads 22382 # number of floating regfile reads
+system.cpu2.fp_regfile_writes 20836 # number of floating regfile writes
+system.cpu2.misc_regfile_reads 9252861 # number of misc regfile reads
+system.cpu2.misc_regfile_writes 241910 # number of misc regfile writes
+system.iocache.tags.replacements 0 # number of replacements
+system.iocache.tags.tagsinuse 0 # Cycle average of tags in use
+system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
+system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks.
+system.iocache.tags.avg_refs nan # Average number of references to valid blocks.
+system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1279969503000 # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 1279969503000 # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1279969503000 # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 1279969503000 # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1279629373750 # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 1279629373750 # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1279629373750 # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 1279629373750 # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
---------- Begin Simulation Statistics ----------
-sim_seconds 2.548515 # Number of seconds simulated
-sim_ticks 2548515380000 # Number of ticks simulated
-final_tick 2548515380000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 2.548576 # Number of seconds simulated
+sim_ticks 2548576209000 # Number of ticks simulated
+final_tick 2548576209000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 61977 # Simulator instruction rate (inst/s)
-host_op_rate 79748 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2618667230 # Simulator tick rate (ticks/s)
-host_mem_usage 403588 # Number of bytes of host memory used
-host_seconds 973.21 # Real time elapsed on the host
-sim_insts 60316341 # Number of instructions simulated
-sim_ops 77611368 # Number of ops (including micro ops) simulated
+host_inst_rate 60580 # Simulator instruction rate (inst/s)
+host_op_rate 77951 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2559708219 # Simulator tick rate (ticks/s)
+host_mem_usage 399668 # Number of bytes of host memory used
+host_seconds 995.65 # Real time elapsed on the host
+sim_insts 60316464 # Number of instructions simulated
+sim_ops 77611603 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.dtb.walker 1216 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.dtb.walker 1856 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst 440128 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 4850064 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker 1216 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 360448 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 4242200 # Number of bytes read from this memory
-system.physmem.bytes_read::total 131005928 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 440128 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 360448 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 800576 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 3785088 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0.data 1679112 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu1.data 1336988 # Number of bytes written to this memory
-system.physmem.bytes_written::total 6801188 # Number of bytes written to this memory
+system.physmem.bytes_read::cpu0.inst 483776 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 5166800 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker 704 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst 315264 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 3924504 # Number of bytes read from this memory
+system.physmem.bytes_read::total 131003560 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 483776 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 315264 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 799040 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 3783488 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu0.data 1522020 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu1.data 1494080 # Number of bytes written to this memory
+system.physmem.bytes_written::total 6799588 # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.dtb.walker 19 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.dtb.walker 29 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst 6877 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 75816 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker 19 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 5632 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 66290 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 15293471 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 59142 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0.data 419778 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu1.data 334247 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 813167 # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd 47521992 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.dtb.walker 477 # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_reads::cpu0.inst 7559 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 80765 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker 11 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst 4926 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 61326 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 15293434 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 59117 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu0.data 380505 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu1.data 373520 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 813142 # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd 47520858 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.dtb.walker 728 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 50 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst 172700 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 1903094 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker 477 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 141435 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 1664577 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 51404802 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 172700 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 141435 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 314134 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1485213 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data 658859 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1.data 524614 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 2668686 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1485213 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd 47521992 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker 477 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst 189822 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 2027328 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker 276 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 123702 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 1539881 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 51402646 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 189822 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 123702 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 313524 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 1484550 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data 597204 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1.data 586241 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 2667995 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 1484550 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd 47520858 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker 728 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 50 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 172700 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 2561953 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker 477 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 141435 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 2189191 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 54073488 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 15293471 # Total number of read requests seen
-system.physmem.writeReqs 813167 # Total number of write requests seen
-system.physmem.cpureqs 218464 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 978782144 # Total number of bytes read from memory
-system.physmem.bytesWritten 52042688 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 131005928 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 6801188 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 15 # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite 4709 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 955865 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 955532 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 955688 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 955892 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 955763 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 955998 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 955883 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 955786 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 956235 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 955940 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 955511 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 955116 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 956216 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 955973 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 956077 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 955981 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 49128 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 48906 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2 50979 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 51091 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 51008 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5 51270 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6 51265 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 51204 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 51310 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 51097 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 50763 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11 50416 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12 51359 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13 50976 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14 51272 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15 51123 # Track writes on a per bank basis
+system.physmem.bw_total::cpu0.inst 189822 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 2624532 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker 276 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 123702 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 2126122 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 54070641 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 15293434 # Total number of read requests accepted by DRAM controller
+system.physmem.writeReqs 813142 # Total number of write requests accepted by DRAM controller
+system.physmem.readBursts 15293434 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
+system.physmem.writeBursts 813142 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
+system.physmem.bytesRead 978779776 # Total number of bytes read from memory
+system.physmem.bytesWritten 52041088 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 131003560 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 6799588 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 13 # Number of DRAM read bursts serviced by write Q
+system.physmem.neitherReadNorWrite 4677 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 955864 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 955534 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 955684 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 955879 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 955769 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 955991 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 955868 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 955778 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 956236 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 955947 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 955508 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 955111 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 956226 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 955972 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 956075 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 955979 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 6690 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 6478 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 6630 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 6656 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 6589 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 6842 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 6835 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 6779 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 7114 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 6901 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 6563 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 6214 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 7157 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 6772 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 7070 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 6922 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
-system.physmem.numWrRetry 32396 # Number of times wr buffer was full causing retry
-system.physmem.totGap 2548513467000 # Total gap between requests
+system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
+system.physmem.totGap 2548575024500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 42 # Categorize read packet sizes
system.physmem.readPktSize::3 15138816 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 154613 # Categorize read packet sizes
+system.physmem.readPktSize::6 154576 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
system.physmem.writePktSize::2 754025 # Categorize write packet sizes
system.physmem.writePktSize::3 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
-system.physmem.writePktSize::6 59142 # Categorize write packet sizes
-system.physmem.rdQLenPdf::0 1060849 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 987246 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 977477 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 3738495 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 2806386 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 2806166 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 2776833 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 15211 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 14905 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 28917 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 42926 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11 28925 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12 2287 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13 2286 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14 2959 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15 1551 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16 20 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17 9 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18 4 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19 3 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 59117 # Categorize write packet sizes
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+system.physmem.rdQLenPdf::1 987876 # What read queue length does an incoming req see
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+system.physmem.rdQLenPdf::3 3738072 # What read queue length does an incoming req see
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+system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 2759 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 2878 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 2926 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 2969 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 2964 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 2963 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6 2962 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 2967 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8 2971 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9 35376 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10 35363 # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::12 35330 # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::14 35316 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 35302 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 35293 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 35281 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 35264 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 35252 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 35238 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 35229 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 35218 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 32746 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 32612 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 32550 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 32491 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 32482 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 32473 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 32457 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 32442 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 32421 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 40074 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 25722.964516 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 2062.503898 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 32877.713086 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::64-95 7020 17.52% 17.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-159 3450 8.61% 26.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::192-223 2302 5.74% 31.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-287 1762 4.40% 36.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::320-351 1221 3.05% 39.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-415 1083 2.70% 42.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::448-479 782 1.95% 43.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-543 826 2.06% 46.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::576-607 552 1.38% 47.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-671 527 1.32% 48.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::704-735 441 1.10% 49.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-799 399 1.00% 50.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::832-863 278 0.69% 51.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-927 274 0.68% 52.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::960-991 181 0.45% 52.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1055 260 0.65% 53.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1088-1119 121 0.30% 53.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1152-1183 146 0.36% 53.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1216-1247 103 0.26% 54.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1280-1311 108 0.27% 54.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1344-1375 77 0.19% 54.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1408-1439 372 0.93% 55.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1472-1503 611 1.52% 57.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1536-1567 461 1.15% 58.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1600-1631 86 0.21% 58.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1664-1695 174 0.43% 58.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1728-1759 54 0.13% 59.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1792-1823 96 0.24% 59.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1856-1887 48 0.12% 59.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1920-1951 68 0.17% 59.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1984-2015 31 0.08% 59.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2048-2079 67 0.17% 59.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2112-2143 19 0.05% 59.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2176-2207 52 0.13% 60.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2240-2271 17 0.04% 60.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2304-2335 39 0.10% 60.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2368-2399 17 0.04% 60.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2432-2463 35 0.09% 60.29% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2496-2527 6 0.01% 60.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2560-2591 20 0.05% 60.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2624-2655 5 0.01% 60.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2688-2719 15 0.04% 60.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2752-2783 12 0.03% 60.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2816-2847 19 0.05% 60.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2880-2911 10 0.02% 60.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2944-2975 19 0.05% 60.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3008-3039 6 0.01% 60.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3072-3103 14 0.03% 60.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3136-3167 5 0.01% 60.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3200-3231 6 0.01% 60.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3264-3295 5 0.01% 60.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3328-3359 9 0.02% 60.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3392-3423 3 0.01% 60.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3456-3487 12 0.03% 60.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3520-3551 4 0.01% 60.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3584-3615 10 0.02% 60.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3648-3679 3 0.01% 60.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3712-3743 8 0.02% 60.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3776-3807 7 0.02% 60.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3840-3871 6 0.01% 60.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3904-3935 1 0.00% 60.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3968-3999 7 0.02% 60.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4032-4063 5 0.01% 60.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4096-4127 35 0.09% 60.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4160-4191 5 0.01% 60.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4224-4255 2 0.00% 60.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4288-4319 3 0.01% 60.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4352-4383 7 0.02% 60.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4416-4447 4 0.01% 60.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4480-4511 5 0.01% 60.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4544-4575 1 0.00% 60.98% # Bytes accessed per row activation
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-system.physmem.bytesPerActivate::4928-4959 3 0.01% 61.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4992-5023 5 0.01% 61.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5120-5151 4 0.01% 61.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5184-5215 2 0.00% 61.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5248-5279 2 0.00% 61.07% # Bytes accessed per row activation
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-system.physmem.bytesPerActivate::7040-7071 4 0.01% 61.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7104-7135 2 0.00% 61.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7168-7199 3 0.01% 61.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7296-7327 5 0.01% 61.27% # Bytes accessed per row activation
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-system.physmem.bytesPerActivate::7552-7583 3 0.01% 61.28% # Bytes accessed per row activation
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-system.physmem.bytesPerActivate::65536-65567 14763 36.84% 99.10% # Bytes accessed per row activation
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-system.physmem.bytesPerActivate::131008-131039 1 0.00% 99.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::131072-131103 346 0.86% 99.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::131200-131231 1 0.00% 99.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::132096-132127 4 0.01% 99.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::136576-136607 1 0.00% 99.98% # Bytes accessed per row activation
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-system.physmem.bytesPerActivate::total 40074 # Bytes accessed per row activation
-system.physmem.totQLat 305431681500 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 397314004000 # Sum of mem lat for all requests
-system.physmem.totBusLat 76467280000 # Total cycles spent in databus access
-system.physmem.totBankLat 15415042500 # Total cycles spent in bank access
-system.physmem.avgQLat 19971.40 # Average queueing delay per request
-system.physmem.avgBankLat 1007.95 # Average bank access latency per request
+system.physmem.wrQLenPdf::0 4852 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::24 2 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples 39284 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 25091.701456 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 2070.748672 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 31471.829892 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::64-79 6644 16.91% 16.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-143 3436 8.75% 25.66% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::384-399 1105 2.81% 42.11% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::448-463 800 2.04% 44.15% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::576-591 554 1.41% 47.63% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::1344-1359 70 0.18% 54.96% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::1600-1615 85 0.22% 57.99% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::2304-2319 32 0.08% 59.64% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::2496-2511 8 0.02% 59.75% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2560-2575 26 0.07% 59.82% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2624-2639 6 0.02% 59.83% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2688-2703 18 0.05% 59.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2752-2767 15 0.04% 59.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2816-2831 16 0.04% 59.96% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2880-2895 7 0.02% 59.97% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::4160-4175 5 0.01% 60.39% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::8192-8207 311 0.79% 61.65% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::8448-8463 63 0.16% 61.81% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::8512-8527 194 0.49% 62.30% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::8576-8591 13 0.03% 62.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::8768-8783 3 0.01% 62.34% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::8832-8847 2 0.01% 62.35% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::20480-20495 1 0.00% 62.35% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::23680-23695 1 0.00% 62.35% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::25600-25615 2 0.01% 62.36% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::28352-28367 1 0.00% 62.36% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::28416-28431 1 0.00% 62.36% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::32192-32207 1 0.00% 62.36% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::33344-33359 1 0.00% 62.37% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::33664-33679 2 0.01% 62.37% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::33792-33807 2 0.01% 62.38% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::39488-39503 1 0.00% 62.38% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::45056-45071 1 0.00% 62.39% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::64768-64783 1 0.00% 62.39% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::65536-65551 14685 37.38% 99.77% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::68736-68751 1 0.00% 99.78% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::73984-73999 43 0.11% 99.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::74048-74063 33 0.08% 99.99% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::74112-74127 3 0.01% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 39284 # Bytes accessed per row activation
+system.physmem.totQLat 294283871250 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 386089225000 # Sum of mem lat for all requests
+system.physmem.totBusLat 76467105000 # Total cycles spent in databus access
+system.physmem.totBankLat 15338248750 # Total cycles spent in bank access
+system.physmem.avgQLat 19242.51 # Average queueing delay per request
+system.physmem.avgBankLat 1002.93 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 25979.35 # Average memory access latency
-system.physmem.avgRdBW 384.06 # Average achieved read bandwidth in MB/s
+system.physmem.avgMemAccLat 25245.45 # Average memory access latency
+system.physmem.avgRdBW 384.05 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 20.42 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 51.40 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 2.67 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 3.16 # Data bus utilization in percentage
-system.physmem.avgRdQLen 0.16 # Average read queue length over time
-system.physmem.avgWrQLen 1.11 # Average write queue length over time
-system.physmem.readRowHits 15267858 # Number of row buffer hits during reads
-system.physmem.writeRowHits 798688 # Number of row buffer hits during writes
+system.physmem.avgRdQLen 0.15 # Average read queue length over time
+system.physmem.avgWrQLen 1.08 # Average write queue length over time
+system.physmem.readRowHits 15268174 # Number of row buffer hits during reads
+system.physmem.writeRowHits 94166 # Number of row buffer hits during writes
system.physmem.readRowHitRate 99.83 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 98.22 # Row buffer hit rate for writes
-system.physmem.avgGap 158227.53 # Average gap between requests
+system.physmem.writeRowHitRate 11.58 # Row buffer hit rate for writes
+system.physmem.avgGap 158231.96 # Average gap between requests
system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory
system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput 55014417 # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq 16346104 # Transaction distribution
-system.membus.trans_dist::ReadResp 16346107 # Transaction distribution
+system.membus.throughput 55011549 # Throughput (bytes/s)
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+system.membus.trans_dist::ReadResp 16346069 # Transaction distribution
system.membus.trans_dist::WriteReq 763348 # Transaction distribution
system.membus.trans_dist::WriteResp 763348 # Transaction distribution
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-system.membus.trans_dist::UpgradeReq 4707 # Transaction distribution
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system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
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-system.membus.trans_dist::ReadExResp 131412 # Transaction distribution
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+system.membus.trans_dist::ReadExResp 131414 # Transaction distribution
system.membus.trans_dist::LoadLockedReq 3 # Transaction distribution
system.membus.trans_dist::StoreCondReq 3 # Transaction distribution
system.membus.trans_dist::StoreCondResp 3 # Transaction distribution
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system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes)
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system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 3790 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes)
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system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30277632 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 30277632 # Packet count per connected master and slave (bytes)
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system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes)
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system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 7580 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes)
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system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes)
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-system.membus.tot_pkt_size::total 140205089 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 140205089 # Total data (bytes)
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+system.membus.data_through_bus 140201125 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy 1476111500 # Layer occupancy (ticks)
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system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.membus.reqLayer1.occupancy 1000 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
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-system.membus.reqLayer3.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer5.occupancy 1500 # Layer occupancy (ticks)
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system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
-system.membus.respLayer2.occupancy 34172276993 # Layer occupancy (ticks)
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system.membus.respLayer2.utilization 1.3 # Layer utilization (%)
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-system.l2c.tags.total_refs 1905390 # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs 129776 # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs 14.682145 # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle 2511428822500 # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks 36972.715861 # Average occupied blocks per requestor
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-system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 6768250 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.data 96162290254 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data 94324110000 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total 190493168504 # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000574 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000287 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.013414 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.032089 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000626 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.011733 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.021902 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total 0.015818 # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.983964 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.985836 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total 0.984854 # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.285714 # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.153846 # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.548497 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.533185 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total 0.541204 # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000574 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000287 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst 0.013414 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data 0.241317 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000626 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst 0.011733 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data 0.205558 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total 0.091627 # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000574 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000287 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst 0.013414 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data 0.241317 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000626 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst 0.011733 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data 0.205558 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total 0.091627 # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 99434.210526 # average ReadReq mshr miss latency
+system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 6023999 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.data 93382533238 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data 90909138000 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total 184297695237 # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000933 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000294 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.014966 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.033619 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000341 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010138 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.020586 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total 0.015800 # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.986476 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.986420 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total 0.986445 # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.250000 # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.200000 # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.570099 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.507513 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total 0.541059 # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000933 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000294 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst 0.014966 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data 0.255522 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000341 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010138 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data 0.191498 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total 0.091636 # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000933 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000294 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst 0.014966 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data 0.255522 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000341 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010138 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data 0.191498 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total 0.091636 # mshr miss rate for overall accesses
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system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 52875 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 61263.087844 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 60817.646245 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 95960.526316 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 61535.422585 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 64195.633188 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 61853.395911 # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10002.303781 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10001.683527 # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average SCUpgradeReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 59233.207953 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 59880.367207 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 91750 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 63562.728380 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 62924.545204 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 61076.105220 # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10003.816020 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10002.545861 # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 56090.553308 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 56116.480736 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 56102.719595 # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 99434.210526 # average overall mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 57104.629002 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 54811.358977 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 56106.547358 # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 82870.689655 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 52875 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 61263.087844 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 56464.459493 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 95960.526316 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 61535.422585 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 56668.098479 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 56952.226652 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 99434.210526 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 59233.207953 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 57318.776060 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 91750 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 63562.728380 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 55377.377056 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 56839.678419 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 82870.689655 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 52875 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 61263.087844 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 56464.459493 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 95960.526316 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 61535.422585 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 56668.098479 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 56952.226652 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 59233.207953 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 57318.776060 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 91750 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 63562.728380 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 55377.377056 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 56839.678419 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
-system.toL2Bus.throughput 58503668 # Throughput (bytes/s)
-system.toL2Bus.trans_dist::ReadReq 2677420 # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp 2677422 # Transaction distribution
+system.toL2Bus.throughput 58475740 # Throughput (bytes/s)
+system.toL2Bus.trans_dist::ReadReq 2676749 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 2676751 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 763348 # Transaction distribution
system.toL2Bus.trans_dist::WriteResp 763348 # Transaction distribution
-system.toL2Bus.trans_dist::Writeback 608377 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq 2971 # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq 13 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp 2984 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 246105 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 246105 # Transaction distribution
+system.toL2Bus.trans_dist::Writeback 608201 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 2951 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq 10 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 2961 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 246143 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 246143 # Transaction distribution
system.toL2Bus.trans_dist::LoadLockedReq 3 # Transaction distribution
system.toL2Bus.trans_dist::StoreCondReq 3 # Transaction distribution
system.toL2Bus.trans_dist::StoreCondResp 3 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 1969614 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 5798105 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma 37248 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma 149421 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count 7954388 # Packet count per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 62990656 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 85594465 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma 54388 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma 253832 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size 148893341 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.data_through_bus 148893341 # Total data (bytes)
-system.toL2Bus.snoop_data_through_bus 204156 # Total snoop data (bytes)
-system.toL2Bus.reqLayer0.occupancy 4964785971 # Layer occupancy (ticks)
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1967991 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5797697 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 37845 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 149237 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 7952770 # Packet count per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 62938176 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 85577189 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 55304 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 253516 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size::total 148824185 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.data_through_bus 148824185 # Total data (bytes)
+system.toL2Bus.snoop_data_through_bus 205696 # Total snoop data (bytes)
+system.toL2Bus.reqLayer0.occupancy 4963674463 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy 4437766959 # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy 4434137240 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy 4499076262 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy 4494378467 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy 23705637 # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy 24064152 # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy 86451768 # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy 86310594 # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.throughput 48459921 # Throughput (bytes/s)
-system.iobus.trans_dist::ReadReq 16322133 # Transaction distribution
-system.iobus.trans_dist::ReadResp 16322133 # Transaction distribution
+system.iobus.throughput 48458766 # Throughput (bytes/s)
+system.iobus.trans_dist::ReadReq 16322134 # Transaction distribution
+system.iobus.trans_dist::ReadResp 16322134 # Transaction distribution
system.iobus.trans_dist::WriteReq 8160 # Transaction distribution
system.iobus.trans_dist::WriteResp 8160 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7936 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7938 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 522 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1030 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 2382954 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 2382956 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30277632 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.clcd.dma::total 30277632 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.realview_io.pio 7936 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.timer0.pio 522 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.timer1.pio 1030 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.iocache.cpu_side 30277632 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 32660586 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 32660588 # Packet count per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15872 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15876 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1044 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2060 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::total 2390325 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::total 2390329 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.realview.clcd.dma::total 121110528 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.realview_io.pio 15872 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.timer0.pio 1044 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.timer1.pio 2060 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::total 123500853 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.data_through_bus 123500853 # Total data (bytes)
+system.iobus.tot_pkt_size::total 123500857 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.data_through_bus 123500857 # Total data (bytes)
system.iobus.reqLayer0.occupancy 21043000 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer1.occupancy 3973000 # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy 3974000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.occupancy 522000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer25.occupancy 15138816000 # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%)
-system.iobus.respLayer0.occupancy 2374794000 # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy 2374796000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.1 # Layer utilization (%)
-system.iobus.respLayer1.occupancy 41501177007 # Layer occupancy (ticks)
+system.iobus.respLayer1.occupancy 41501700007 # Layer occupancy (ticks)
system.iobus.respLayer1.utilization 1.6 # Layer utilization (%)
-system.cpu0.branchPred.lookups 7460849 # Number of BP lookups
-system.cpu0.branchPred.condPredicted 5960235 # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect 378283 # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups 4914778 # Number of BTB lookups
-system.cpu0.branchPred.BTBHits 4045811 # Number of BTB hits
+system.cpu0.branchPred.lookups 7055231 # Number of BP lookups
+system.cpu0.branchPred.condPredicted 5603867 # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect 360036 # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups 4627391 # Number of BTB lookups
+system.cpu0.branchPred.BTBHits 3766189 # Number of BTB hits
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct 82.319303 # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS 696591 # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect 38344 # Number of incorrect RAS predictions.
+system.cpu0.branchPred.BTBHitPct 81.389038 # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS 696378 # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect 37374 # Number of incorrect RAS predictions.
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
-system.cpu0.dtb.read_hits 25704058 # DTB read hits
-system.cpu0.dtb.read_misses 39030 # DTB read misses
-system.cpu0.dtb.write_hits 5997479 # DTB write hits
-system.cpu0.dtb.write_misses 9591 # DTB write misses
-system.cpu0.dtb.flush_tlb 258 # Number of times complete TLB was flushed
+system.cpu0.dtb.read_hits 25604020 # DTB read hits
+system.cpu0.dtb.read_misses 37101 # DTB read misses
+system.cpu0.dtb.write_hits 6019786 # DTB write hits
+system.cpu0.dtb.write_misses 10089 # DTB write misses
+system.cpu0.dtb.flush_tlb 257 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid 775 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dtb.flush_tlb_asid 33 # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries 5605 # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults 1289 # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults 246 # Number of TLB faults due to prefetch
+system.cpu0.dtb.flush_tlb_mva_asid 658 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_asid 29 # Number of times TLB was flushed by ASID
+system.cpu0.dtb.flush_entries 5563 # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults 1360 # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults 245 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults 688 # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses 25743088 # DTB read accesses
-system.cpu0.dtb.write_accesses 6007070 # DTB write accesses
+system.cpu0.dtb.perms_faults 609 # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses 25641121 # DTB read accesses
+system.cpu0.dtb.write_accesses 6029875 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu0.dtb.hits 31701537 # DTB hits
-system.cpu0.dtb.misses 48621 # DTB misses
-system.cpu0.dtb.accesses 31750158 # DTB accesses
-system.cpu0.itb.inst_hits 6247488 # ITB inst hits
-system.cpu0.itb.inst_misses 7199 # ITB inst misses
+system.cpu0.dtb.hits 31623806 # DTB hits
+system.cpu0.dtb.misses 47190 # DTB misses
+system.cpu0.dtb.accesses 31670996 # DTB accesses
+system.cpu0.itb.inst_hits 5711817 # ITB inst hits
+system.cpu0.itb.inst_misses 6786 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
-system.cpu0.itb.flush_tlb 258 # Number of times complete TLB was flushed
+system.cpu0.itb.flush_tlb 257 # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid 775 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.itb.flush_tlb_asid 33 # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries 2628 # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_tlb_mva_asid 658 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_asid 29 # Number of times TLB was flushed by ASID
+system.cpu0.itb.flush_entries 2595 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults 1719 # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.perms_faults 1280 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
-system.cpu0.itb.inst_accesses 6254687 # ITB inst accesses
-system.cpu0.itb.hits 6247488 # DTB hits
-system.cpu0.itb.misses 7199 # DTB misses
-system.cpu0.itb.accesses 6254687 # DTB accesses
-system.cpu0.numCycles 237974378 # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses 5718603 # ITB inst accesses
+system.cpu0.itb.hits 5711817 # DTB hits
+system.cpu0.itb.misses 6786 # DTB misses
+system.cpu0.itb.accesses 5718603 # DTB accesses
+system.cpu0.numCycles 240384739 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.fetch.icacheStallCycles 15699723 # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts 49234228 # Number of instructions fetch has processed
-system.cpu0.fetch.Branches 7460849 # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches 4742402 # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles 10819268 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles 2791638 # Number of cycles fetch has spent squashing
-system.cpu0.fetch.TlbCycles 83518 # Number of cycles fetch has spent waiting for tlb
-system.cpu0.fetch.BlockedCycles 47679796 # Number of cycles fetch has spent blocked
-system.cpu0.fetch.MiscStallCycles 1230 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingDrainCycles 1910 # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu0.fetch.PendingTrapStallCycles 50382 # Number of stall cycles due to pending traps
-system.cpu0.fetch.PendingQuiesceStallCycles 1297285 # Number of stall cycles due to pending quiesce instructions
-system.cpu0.fetch.IcacheWaitRetryStallCycles 371 # Number of stall cycles due to full MSHR
-system.cpu0.fetch.CacheLines 6245426 # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes 421717 # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.ItlbSquashes 2971 # Number of outstanding ITLB misses that were squashed
-system.cpu0.fetch.rateDist::samples 77555768 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean 0.784584 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev 2.151481 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.icacheStallCycles 15036708 # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts 44324460 # Number of instructions fetch has processed
+system.cpu0.fetch.Branches 7055231 # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches 4462567 # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles 9979880 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles 2348952 # Number of cycles fetch has spent squashing
+system.cpu0.fetch.TlbCycles 79920 # Number of cycles fetch has spent waiting for tlb
+system.cpu0.fetch.BlockedCycles 48371030 # Number of cycles fetch has spent blocked
+system.cpu0.fetch.MiscStallCycles 1557 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu0.fetch.PendingDrainCycles 1896 # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu0.fetch.PendingTrapStallCycles 40136 # Number of stall cycles due to pending traps
+system.cpu0.fetch.PendingQuiesceStallCycles 1395788 # Number of stall cycles due to pending quiesce instructions
+system.cpu0.fetch.IcacheWaitRetryStallCycles 332 # Number of stall cycles due to full MSHR
+system.cpu0.fetch.CacheLines 5710035 # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes 358939 # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.ItlbSquashes 3057 # Number of outstanding ITLB misses that were squashed
+system.cpu0.fetch.rateDist::samples 76524952 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean 0.728839 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev 2.080650 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0 66744115 86.06% 86.06% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1 668305 0.86% 86.92% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2 854486 1.10% 88.02% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3 1301033 1.68% 89.70% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::4 1140084 1.47% 91.17% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::5 550475 0.71% 91.88% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::6 1373308 1.77% 93.65% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::7 375655 0.48% 94.14% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::8 4548307 5.86% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0 66552751 86.97% 86.97% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1 648002 0.85% 87.82% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2 843291 1.10% 88.92% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3 1146450 1.50% 90.42% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::4 1051496 1.37% 91.79% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::5 533927 0.70% 92.49% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::6 1248962 1.63% 94.12% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::7 369566 0.48% 94.60% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::8 4130507 5.40% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total 77555768 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate 0.031351 # Number of branch fetches per cycle
-system.cpu0.fetch.rate 0.206889 # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles 16771569 # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles 48649935 # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles 9795097 # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles 503008 # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles 1834030 # Number of cycles decode is squashing
-system.cpu0.decode.BranchResolved 1000504 # Number of times decode resolved a branch
-system.cpu0.decode.BranchMispred 90828 # Number of times decode detected a branch misprediction
-system.cpu0.decode.DecodedInsts 57451762 # Number of instructions handled by decode
-system.cpu0.decode.SquashedInsts 304997 # Number of squashed instructions handled by decode
-system.cpu0.rename.SquashCycles 1834030 # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles 17711945 # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles 19691518 # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles 25851696 # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles 9283653 # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles 3180864 # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts 54475085 # Number of instructions processed by rename
-system.cpu0.rename.ROBFullEvents 7298 # Number of times rename has blocked due to ROB full
-system.cpu0.rename.IQFullEvents 545691 # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LSQFullEvents 2120831 # Number of times rename has blocked due to LSQ full
-system.cpu0.rename.FullRegisterEvents 197 # Number of times there has been no free registers
-system.cpu0.rename.RenamedOperands 56755313 # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups 249403500 # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups 249355386 # Number of integer rename lookups
-system.cpu0.rename.fp_rename_lookups 48114 # Number of floating rename lookups
-system.cpu0.rename.CommittedMaps 39528436 # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps 17226877 # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts 410327 # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts 362870 # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts 6606046 # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads 10343576 # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores 6897280 # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads 1045135 # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores 1291149 # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded 49940914 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded 982735 # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued 62750040 # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued 92397 # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined 11407526 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined 29277622 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved 263780 # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples 77555768 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean 0.809096 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev 1.520917 # Number of insts issued each cycle
+system.cpu0.fetch.rateDist::total 76524952 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate 0.029350 # Number of branch fetches per cycle
+system.cpu0.fetch.rate 0.184390 # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles 15988793 # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles 49427885 # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles 9067900 # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles 506950 # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles 1531254 # Number of cycles decode is squashing
+system.cpu0.decode.BranchResolved 959604 # Number of times decode resolved a branch
+system.cpu0.decode.BranchMispred 89006 # Number of times decode detected a branch misprediction
+system.cpu0.decode.DecodedInsts 53104636 # Number of instructions handled by decode
+system.cpu0.decode.SquashedInsts 296594 # Number of squashed instructions handled by decode
+system.cpu0.rename.SquashCycles 1531254 # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles 16866391 # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles 20063365 # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles 26274348 # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles 8616750 # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles 3170765 # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts 50610961 # Number of instructions processed by rename
+system.cpu0.rename.ROBFullEvents 7411 # Number of times rename has blocked due to ROB full
+system.cpu0.rename.IQFullEvents 529520 # Number of times rename has blocked due to IQ full
+system.cpu0.rename.LSQFullEvents 2115247 # Number of times rename has blocked due to LSQ full
+system.cpu0.rename.FullRegisterEvents 208 # Number of times there has been no free registers
+system.cpu0.rename.RenamedOperands 52034450 # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups 231667374 # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups 231623806 # Number of integer rename lookups
+system.cpu0.rename.fp_rename_lookups 43568 # Number of floating rename lookups
+system.cpu0.rename.CommittedMaps 38251156 # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps 13783293 # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts 411980 # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts 362796 # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts 6588533 # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads 9723453 # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores 6830710 # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads 1010499 # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores 1245426 # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded 47056287 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded 968125 # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued 61041577 # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued 84130 # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined 9522170 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined 23883479 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedNonSpecRemoved 244384 # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.issued_per_cycle::samples 76524952 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean 0.797669 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev 1.517362 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0 55086998 71.03% 71.03% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1 6938242 8.95% 79.98% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2 3598420 4.64% 84.61% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3 3124608 4.03% 88.64% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4 6233139 8.04% 96.68% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5 1485765 1.92% 98.60% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::6 804564 1.04% 99.63% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::7 219887 0.28% 99.92% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::8 64145 0.08% 100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0 54759555 71.56% 71.56% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1 6733047 8.80% 80.36% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2 3420180 4.47% 84.83% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3 2920085 3.82% 88.64% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4 6164290 8.06% 96.70% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5 1467950 1.92% 98.62% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::6 772657 1.01% 99.62% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::7 222441 0.29% 99.92% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::8 64747 0.08% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total 77555768 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total 76524952 # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu 31748 0.72% 0.72% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult 3 0.00% 0.72% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv 0 0.00% 0.72% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd 0 0.00% 0.72% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp 0 0.00% 0.72% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt 0 0.00% 0.72% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult 0 0.00% 0.72% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv 0 0.00% 0.72% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 0.72% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd 0 0.00% 0.72% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 0.72% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu 0 0.00% 0.72% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp 0 0.00% 0.72% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt 0 0.00% 0.72% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc 0 0.00% 0.72% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult 0 0.00% 0.72% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 0.72% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift 0 0.00% 0.72% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 0.72% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 0.72% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 0.72% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 0.72% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 0.72% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 0.72% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 0.72% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 0.72% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 0.72% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.72% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 0.72% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead 4146155 94.50% 95.22% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite 209698 4.78% 100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu 27542 0.62% 0.62% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult 0 0.00% 0.62% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntDiv 0 0.00% 0.62% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatAdd 0 0.00% 0.62% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCmp 0 0.00% 0.62% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCvt 0 0.00% 0.62% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult 0 0.00% 0.62% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv 0 0.00% 0.62% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 0.62% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd 0 0.00% 0.62% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 0.62% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAlu 0 0.00% 0.62% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCmp 0 0.00% 0.62% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCvt 0 0.00% 0.62% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMisc 0 0.00% 0.62% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult 0 0.00% 0.62% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 0.62% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift 0 0.00% 0.62% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 0.62% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 0.62% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 0.62% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 0.62% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 0.62% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 0.62% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 0.62% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 0.62% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 0.62% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.62% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 0.62% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead 4220431 94.60% 95.22% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite 213140 4.78% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu0.iq.FU_type_0::No_OpClass 168420 0.27% 0.27% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu 29819854 47.52% 47.79% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult 48156 0.08% 47.87% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 47.87% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 47.87% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 47.87% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 47.87% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 47.87% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 47.87% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 47.87% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 47.87% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 47.87% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 47.87% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 47.87% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 47.87% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMisc 14 0.00% 47.87% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 47.87% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 47.87% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShift 3 0.00% 47.87% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShiftAcc 8 0.00% 47.87% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 47.87% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.87% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.87% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.87% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.87% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.87% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMisc 937 0.00% 47.87% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 47.87% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 47.87% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.87% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead 26415371 42.10% 89.96% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite 6297270 10.04% 100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::No_OpClass 171568 0.28% 0.28% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu 28242983 46.27% 46.55% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult 47431 0.08% 46.63% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 46.63% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 46.63% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 46.63% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 46.63% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 46.63% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 46.63% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 46.63% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 46.63% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 46.63% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 46.63% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 46.63% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 46.63% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMisc 9 0.00% 46.63% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 46.63% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 46.63% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 46.63% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShiftAcc 4 0.00% 46.63% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 46.63% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 46.63% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 46.63% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 46.63% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 46.63% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 46.63% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMisc 1218 0.00% 46.63% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 46.63% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 46.63% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 46.63% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead 26256845 43.01% 89.64% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite 6321515 10.36% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total 62750040 # Type of FU issued
-system.cpu0.iq.rate 0.263684 # Inst issue rate
-system.cpu0.iq.fu_busy_cnt 4387604 # FU busy when requested
-system.cpu0.iq.fu_busy_rate 0.069922 # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads 207571986 # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes 62340159 # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses 43794455 # Number of integer instruction queue wakeup accesses
-system.cpu0.iq.fp_inst_queue_reads 12289 # Number of floating instruction queue reads
-system.cpu0.iq.fp_inst_queue_writes 6579 # Number of floating instruction queue writes
-system.cpu0.iq.fp_inst_queue_wakeup_accesses 5482 # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses 66962707 # Number of integer alu accesses
-system.cpu0.iq.fp_alu_accesses 6517 # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads 317894 # Number of loads that had data forwarded from stores
+system.cpu0.iq.FU_type_0::total 61041577 # Type of FU issued
+system.cpu0.iq.rate 0.253933 # Inst issue rate
+system.cpu0.iq.fu_busy_cnt 4461113 # FU busy when requested
+system.cpu0.iq.fu_busy_rate 0.073083 # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads 203189112 # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes 57554843 # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses 42164489 # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.fp_inst_queue_reads 11244 # Number of floating instruction queue reads
+system.cpu0.iq.fp_inst_queue_writes 5997 # Number of floating instruction queue writes
+system.cpu0.iq.fp_inst_queue_wakeup_accesses 4944 # Number of floating instruction queue wakeup accesses
+system.cpu0.iq.int_alu_accesses 65325122 # Number of integer alu accesses
+system.cpu0.iq.fp_alu_accesses 6000 # Number of floating point alu accesses
+system.cpu0.iew.lsq.thread0.forwLoads 306679 # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads 2428904 # Number of loads squashed
-system.cpu0.iew.lsq.thread0.ignoredResponses 3600 # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread0.memOrderViolation 16156 # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores 921017 # Number of stores squashed
+system.cpu0.iew.lsq.thread0.squashedLoads 2052481 # Number of loads squashed
+system.cpu0.iew.lsq.thread0.ignoredResponses 3874 # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread0.memOrderViolation 14810 # Number of memory ordering violations
+system.cpu0.iew.lsq.thread0.squashedStores 826086 # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu0.iew.lsq.thread0.rescheduledLoads 16878789 # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked 486624 # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread0.rescheduledLoads 17207144 # Number of loads that were rescheduled
+system.cpu0.iew.lsq.thread0.cacheBlocked 348104 # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles 1834030 # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles 15021196 # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles 239984 # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts 51041656 # Number of instructions dispatched to IQ
-system.cpu0.iew.iewDispSquashedInsts 102587 # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts 10343576 # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts 6897280 # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts 695313 # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents 54984 # Number of times the IQ has become full, causing a stall
-system.cpu0.iew.iewLSQFullEvents 10683 # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.memOrderViolationEvents 16156 # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect 184294 # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect 146657 # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts 330951 # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts 61443864 # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts 26034265 # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts 1306176 # Number of squashed instructions skipped in execute
+system.cpu0.iew.iewSquashCycles 1531254 # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles 15306015 # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles 241273 # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts 48127004 # Number of instructions dispatched to IQ
+system.cpu0.iew.iewDispSquashedInsts 101529 # Number of squashed instructions skipped by dispatch
+system.cpu0.iew.iewDispLoadInsts 9723453 # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts 6830710 # Number of dispatched store instructions
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+system.cpu0.iew.iewIQFullEvents 53931 # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewLSQFullEvents 11240 # Number of times the LSQ has become full, causing a stall
+system.cpu0.iew.memOrderViolationEvents 14810 # Number of memory order violations
+system.cpu0.iew.predictedTakenIncorrect 174193 # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedNotTakenIncorrect 137584 # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts 311777 # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewExecutedInsts 60001377 # Number of executed instructions
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system.cpu0.iew.exec_swp 0 # number of swp insts executed
-system.cpu0.iew.exec_nop 118007 # number of nop insts executed
-system.cpu0.iew.exec_refs 32275135 # number of memory reference insts executed
-system.cpu0.iew.exec_branches 5809455 # Number of branches executed
-system.cpu0.iew.exec_stores 6240870 # Number of stores executed
-system.cpu0.iew.exec_rate 0.258195 # Inst execution rate
-system.cpu0.iew.wb_sent 60834498 # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count 43799937 # cumulative count of insts written-back
-system.cpu0.iew.wb_producers 23902926 # num instructions producing a value
-system.cpu0.iew.wb_consumers 43468500 # num instructions consuming a value
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+system.cpu0.iew.wb_sent 59520960 # cumulative count of insts sent to commit
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system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu0.iew.wb_rate 0.184053 # insts written-back per cycle
-system.cpu0.iew.wb_fanout 0.549891 # average fanout of values written-back
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+system.cpu0.iew.wb_fanout 0.542077 # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu0.commit.commitSquashedInsts 11258567 # The number of squashed insts skipped by commit
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system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0 61785849 81.60% 81.60% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1 6716034 8.87% 90.47% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2 2031673 2.68% 93.15% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3 1100696 1.45% 94.60% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4 996789 1.32% 95.92% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5 567209 0.75% 96.67% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6 697121 0.92% 97.59% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7 401495 0.53% 98.12% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8 1424872 1.88% 100.00% # Number of insts commited each cycle
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+system.cpu0.commit.committed_per_cycle::2 1921399 2.56% 93.23% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3 1064491 1.42% 94.65% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4 990154 1.32% 95.97% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5 565334 0.75% 96.73% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6 721378 0.96% 97.69% # Number of insts commited each cycle
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system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
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-system.cpu0.commit.committedInsts 30484303 # Number of instructions committed
-system.cpu0.commit.committedOps 39296836 # Number of ops (including micro ops) committed
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system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
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-system.cpu0.commit.membars 201566 # Number of memory barriers committed
-system.cpu0.commit.branches 4969836 # Number of branches committed
-system.cpu0.commit.fp_insts 5449 # Number of committed floating point instructions.
-system.cpu0.commit.int_insts 34871152 # Number of committed integer instructions.
-system.cpu0.commit.function_calls 489123 # Number of function calls committed.
-system.cpu0.commit.bw_lim_events 1424872 # number cycles where commit BW limit reached
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system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits
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-system.cpu0.rob.rob_writes 103001078 # The number of ROB writes
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-system.cpu0.quiesceCycles 2282332434 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.committedInsts 30404601 # Number of Instructions Simulated
-system.cpu0.committedOps 39217134 # Number of Ops (including micro ops) Simulated
-system.cpu0.committedInsts_total 30404601 # Number of Instructions Simulated
-system.cpu0.cpi 7.826920 # CPI: Cycles Per Instruction
-system.cpu0.cpi_total 7.826920 # CPI: Total CPI of All Threads
-system.cpu0.ipc 0.127764 # IPC: Instructions Per Cycle
-system.cpu0.ipc_total 0.127764 # IPC: Total IPC of All Threads
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+system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13498.487787 # average ReadReq miss latency
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+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6074560248 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 4703819078 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total 10778379326 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 82036251 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 64895003 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 146931254 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 22000 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 112998 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 134998 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 8603697716 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 7404762473 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total 16008460189 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 8603697716 # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 7404762473 # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total 16008460189 # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 92246094501 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 90072157750 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182318252251 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 13667158074 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 13097409574 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 26764567648 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::cpu1.data 155750 # number of LoadLockedReq MSHR uncacheable cycles
system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::total 155750 # number of LoadLockedReq MSHR uncacheable cycles
system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::cpu1.data 96000 # number of StoreCondReq MSHR uncacheable cycles
system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::total 96000 # number of StoreCondReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 109001574183 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 106248217570 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total 215249791753 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.024652 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.028587 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.026577 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025073 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.023607 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 105913252575 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 103169567324 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total 209082819899 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.025398 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.027718 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.026583 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025297 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.023351 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024353 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.051447 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.043646 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.047334 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000060 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000046 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000052 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.024826 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.026525 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total 0.025659 # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.024826 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.026525 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total 0.025659 # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13865.405311 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13318.627137 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13577.694977 # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 43750.757830 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 42789.411798 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 43292.904137 # average WriteReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12465.426541 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11476.628417 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11984.657122 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 14642.571429 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 11000 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 12961.384615 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 26299.954755 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 24177.701661 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25224.774470 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 26299.954755 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24177.701661 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 25224.774470 # average overall mshr miss latency
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.054662 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.040875 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.047357 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000017 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000061 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000040 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.025355 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025969 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total 0.025662 # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.025355 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025969 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total 0.025662 # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14012.307711 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13132.732332 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13543.853343 # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 45601.040815 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 40630.023477 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 43289.619476 # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12437.272741 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11673.862745 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12088.132785 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 11000 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 14124.750000 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 13499.800000 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 27426.077735 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 23036.434738 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25204.537236 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 27426.077735 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 23036.434738 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 25204.537236 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.branchPred.lookups 7195832 # Number of BP lookups
-system.cpu1.branchPred.condPredicted 5758794 # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect 347995 # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups 4705708 # Number of BTB lookups
-system.cpu1.branchPred.BTBHits 3816103 # Number of BTB hits
+system.cpu1.branchPred.lookups 7417918 # Number of BP lookups
+system.cpu1.branchPred.condPredicted 5931932 # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect 364646 # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups 4881678 # Number of BTB lookups
+system.cpu1.branchPred.BTBHits 3917644 # Number of BTB hits
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct 81.095193 # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS 703176 # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect 35899 # Number of incorrect RAS predictions.
+system.cpu1.branchPred.BTBHitPct 80.251995 # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS 703527 # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect 35801 # Number of incorrect RAS predictions.
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 25676963 # DTB read hits
-system.cpu1.dtb.read_misses 36626 # DTB read misses
-system.cpu1.dtb.write_hits 5717501 # DTB write hits
-system.cpu1.dtb.write_misses 9454 # DTB write misses
+system.cpu1.dtb.read_hits 25617777 # DTB read hits
+system.cpu1.dtb.read_misses 38543 # DTB read misses
+system.cpu1.dtb.write_hits 5691491 # DTB write hits
+system.cpu1.dtb.write_misses 8859 # DTB write misses
system.cpu1.dtb.flush_tlb 255 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid 664 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dtb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries 5514 # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults 1965 # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults 245 # Number of TLB faults due to prefetch
+system.cpu1.dtb.flush_tlb_mva_asid 781 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_asid 34 # Number of times TLB was flushed by ASID
+system.cpu1.dtb.flush_entries 5585 # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults 2011 # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults 285 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults 578 # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses 25713589 # DTB read accesses
-system.cpu1.dtb.write_accesses 5726955 # DTB write accesses
+system.cpu1.dtb.perms_faults 659 # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses 25656320 # DTB read accesses
+system.cpu1.dtb.write_accesses 5700350 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dtb.hits 31394464 # DTB hits
-system.cpu1.dtb.misses 46080 # DTB misses
-system.cpu1.dtb.accesses 31440544 # DTB accesses
-system.cpu1.itb.inst_hits 5739661 # ITB inst hits
-system.cpu1.itb.inst_misses 6710 # ITB inst misses
+system.cpu1.dtb.hits 31309268 # DTB hits
+system.cpu1.dtb.misses 47402 # DTB misses
+system.cpu1.dtb.accesses 31356670 # DTB accesses
+system.cpu1.itb.inst_hits 5866342 # ITB inst hits
+system.cpu1.itb.inst_misses 7403 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
system.cpu1.itb.flush_tlb 255 # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid 664 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.itb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries 2611 # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_tlb_mva_asid 781 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_asid 34 # Number of times TLB was flushed by ASID
+system.cpu1.itb.flush_entries 2681 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults 1312 # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.perms_faults 1687 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.inst_accesses 5746371 # ITB inst accesses
-system.cpu1.itb.hits 5739661 # DTB hits
-system.cpu1.itb.misses 6710 # DTB misses
-system.cpu1.itb.accesses 5746371 # DTB accesses
-system.cpu1.numCycles 238752144 # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses 5873745 # ITB inst accesses
+system.cpu1.itb.hits 5866342 # DTB hits
+system.cpu1.itb.misses 7403 # DTB misses
+system.cpu1.itb.accesses 5873745 # DTB accesses
+system.cpu1.numCycles 234836749 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.fetch.icacheStallCycles 14725732 # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts 45766952 # Number of instructions fetch has processed
-system.cpu1.fetch.Branches 7195832 # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches 4519279 # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles 10135681 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles 2420409 # Number of cycles fetch has spent squashing
-system.cpu1.fetch.TlbCycles 79807 # Number of cycles fetch has spent waiting for tlb
-system.cpu1.fetch.BlockedCycles 48403648 # Number of cycles fetch has spent blocked
-system.cpu1.fetch.MiscStallCycles 1533 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.PendingDrainCycles 1933 # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu1.fetch.PendingTrapStallCycles 42395 # Number of stall cycles due to pending traps
-system.cpu1.fetch.PendingQuiesceStallCycles 1408034 # Number of stall cycles due to pending quiesce instructions
-system.cpu1.fetch.IcacheWaitRetryStallCycles 243 # Number of stall cycles due to full MSHR
-system.cpu1.fetch.CacheLines 5737749 # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes 344300 # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.ItlbSquashes 2901 # Number of outstanding ITLB misses that were squashed
-system.cpu1.fetch.rateDist::samples 76459821 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean 0.743283 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev 2.100006 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.icacheStallCycles 14958684 # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts 46343438 # Number of instructions fetch has processed
+system.cpu1.fetch.Branches 7417918 # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches 4621171 # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles 10240931 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles 2382000 # Number of cycles fetch has spent squashing
+system.cpu1.fetch.TlbCycles 84846 # Number of cycles fetch has spent waiting for tlb
+system.cpu1.fetch.BlockedCycles 47705916 # Number of cycles fetch has spent blocked
+system.cpu1.fetch.MiscStallCycles 1143 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.PendingDrainCycles 1885 # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu1.fetch.PendingTrapStallCycles 51796 # Number of stall cycles due to pending traps
+system.cpu1.fetch.PendingQuiesceStallCycles 1300956 # Number of stall cycles due to pending quiesce instructions
+system.cpu1.fetch.IcacheWaitRetryStallCycles 156 # Number of stall cycles due to full MSHR
+system.cpu1.fetch.CacheLines 5864138 # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes 361139 # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.ItlbSquashes 3128 # Number of outstanding ITLB misses that were squashed
+system.cpu1.fetch.rateDist::samples 75991069 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean 0.753206 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev 2.110012 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0 66331645 86.75% 86.75% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1 641052 0.84% 87.59% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2 862069 1.13% 88.72% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3 1143637 1.50% 90.22% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::4 1042629 1.36% 91.58% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::5 566145 0.74% 92.32% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::6 1286339 1.68% 94.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::7 374523 0.49% 94.49% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::8 4211782 5.51% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0 65758157 86.53% 86.53% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1 661623 0.87% 87.40% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2 874095 1.15% 88.55% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3 1155735 1.52% 90.08% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::4 1058337 1.39% 91.47% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::5 579833 0.76% 92.23% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::6 1309635 1.72% 93.96% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::7 379645 0.50% 94.45% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::8 4214009 5.55% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total 76459821 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate 0.030139 # Number of branch fetches per cycle
-system.cpu1.fetch.rate 0.191692 # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles 15725454 # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles 49459208 # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles 9192415 # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles 503929 # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles 1576672 # Number of cycles decode is squashing
-system.cpu1.decode.BranchResolved 971007 # Number of times decode resolved a branch
-system.cpu1.decode.BranchMispred 86673 # Number of times decode detected a branch misprediction
-system.cpu1.decode.DecodedInsts 53874532 # Number of instructions handled by decode
-system.cpu1.decode.SquashedInsts 286668 # Number of squashed instructions handled by decode
-system.cpu1.rename.SquashCycles 1576672 # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles 16583861 # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles 19404823 # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles 27005764 # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles 8762969 # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles 3123666 # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts 51462507 # Number of instructions processed by rename
-system.cpu1.rename.ROBFullEvents 13354 # Number of times rename has blocked due to ROB full
-system.cpu1.rename.IQFullEvents 564319 # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LSQFullEvents 2029977 # Number of times rename has blocked due to LSQ full
-system.cpu1.rename.FullRegisterEvents 529 # Number of times there has been no free registers
-system.cpu1.rename.RenamedOperands 53559967 # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups 234998901 # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups 234956394 # Number of integer rename lookups
-system.cpu1.rename.fp_rename_lookups 42507 # Number of floating rename lookups
-system.cpu1.rename.CommittedMaps 38873752 # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps 14686214 # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts 422468 # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts 375757 # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts 6418869 # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads 9803560 # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores 6552959 # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads 903342 # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores 1157992 # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded 47368560 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded 1003626 # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued 61323847 # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued 88809 # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined 9695135 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined 24547753 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved 239591 # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples 76459821 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean 0.802040 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev 1.511450 # Number of insts issued each cycle
+system.cpu1.fetch.rateDist::total 75991069 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate 0.031588 # Number of branch fetches per cycle
+system.cpu1.fetch.rate 0.197343 # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles 15934805 # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles 48666188 # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles 9324612 # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles 504366 # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles 1558997 # Number of cycles decode is squashing
+system.cpu1.decode.BranchResolved 1010894 # Number of times decode resolved a branch
+system.cpu1.decode.BranchMispred 88249 # Number of times decode detected a branch misprediction
+system.cpu1.decode.DecodedInsts 54549781 # Number of instructions handled by decode
+system.cpu1.decode.SquashedInsts 295589 # Number of squashed instructions handled by decode
+system.cpu1.rename.SquashCycles 1558997 # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles 16808618 # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles 19027959 # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles 26571393 # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles 8885070 # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles 3136997 # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts 52018175 # Number of instructions processed by rename
+system.cpu1.rename.ROBFullEvents 13230 # Number of times rename has blocked due to ROB full
+system.cpu1.rename.IQFullEvents 586421 # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LSQFullEvents 2033878 # Number of times rename has blocked due to LSQ full
+system.cpu1.rename.FullRegisterEvents 525 # Number of times there has been no free registers
+system.cpu1.rename.RenamedOperands 54353089 # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups 236755846 # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups 236708688 # Number of integer rename lookups
+system.cpu1.rename.fp_rename_lookups 47158 # Number of floating rename lookups
+system.cpu1.rename.CommittedMaps 40151278 # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps 14201811 # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts 419760 # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts 374760 # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts 6443032 # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads 10070258 # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores 6501681 # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads 951169 # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores 1220754 # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded 48367033 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded 1016747 # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued 62006899 # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued 95474 # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined 9693963 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined 24244292 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved 257471 # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples 75991069 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean 0.815976 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev 1.521890 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0 54334795 71.06% 71.06% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1 6963817 9.11% 80.17% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2 3541064 4.63% 84.80% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3 3011943 3.94% 88.74% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4 6202034 8.11% 96.85% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5 1339759 1.75% 98.61% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::6 792493 1.04% 99.64% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::7 211144 0.28% 99.92% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::8 62772 0.08% 100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0 53638566 70.59% 70.59% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1 7003056 9.22% 79.80% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2 3617950 4.76% 84.56% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3 3068918 4.04% 88.60% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4 6184871 8.14% 96.74% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5 1401826 1.84% 98.58% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::6 782382 1.03% 99.61% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::7 229717 0.30% 99.92% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::8 63783 0.08% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total 76459821 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total 75991069 # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu 28001 0.63% 0.63% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult 3 0.00% 0.63% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.63% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.63% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.63% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.63% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.63% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.63% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.63% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.63% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.63% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.63% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.63% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.63% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.63% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.63% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.63% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.63% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.63% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.63% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.63% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.63% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.63% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.63% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.63% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.63% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.63% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.63% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.63% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead 4231917 94.82% 95.44% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite 203383 4.56% 100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu 31911 0.73% 0.73% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult 5 0.00% 0.73% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.73% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.73% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.73% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.73% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.73% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.73% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.73% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.73% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.73% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.73% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.73% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.73% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.73% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.73% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.73% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.73% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.73% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.73% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.73% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.73% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.73% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.73% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.73% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.73% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.73% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.73% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.73% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead 4158175 94.76% 95.48% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite 198234 4.52% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu1.iq.FU_type_0::No_OpClass 195246 0.32% 0.32% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu 28699765 46.80% 47.12% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult 45365 0.07% 47.19% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.19% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.19% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.19% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.19% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.19% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.19% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.19% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.19% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.19% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.19% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.19% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.19% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc 6 0.00% 47.19% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.19% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.19% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift 1 0.00% 47.19% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc 6 0.00% 47.19% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.19% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.19% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.19% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.19% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.19% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.19% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc 1174 0.00% 47.19% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.19% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 47.19% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.19% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead 26341683 42.96% 90.15% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite 6040595 9.85% 100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::No_OpClass 192098 0.31% 0.31% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu 29460264 47.51% 47.82% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult 45939 0.07% 47.90% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.90% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.90% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.90% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.90% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.90% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.90% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.90% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.90% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.90% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.90% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.90% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.90% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc 12 0.00% 47.90% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.90% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.90% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.90% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc 9 0.00% 47.90% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.90% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.90% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.90% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.90% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.90% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.90% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc 896 0.00% 47.90% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.90% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc 9 0.00% 47.90% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.90% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead 26296905 42.41% 90.31% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite 6010767 9.69% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total 61323847 # Type of FU issued
-system.cpu1.iq.rate 0.256852 # Inst issue rate
-system.cpu1.iq.fu_busy_cnt 4463304 # FU busy when requested
-system.cpu1.iq.fu_busy_rate 0.072783 # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads 203694277 # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes 58075857 # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses 42386346 # Number of integer instruction queue wakeup accesses
-system.cpu1.iq.fp_inst_queue_reads 11257 # Number of floating instruction queue reads
-system.cpu1.iq.fp_inst_queue_writes 5873 # Number of floating instruction queue writes
-system.cpu1.iq.fp_inst_queue_wakeup_accesses 4814 # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses 65585843 # Number of integer alu accesses
-system.cpu1.iq.fp_alu_accesses 6062 # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads 307143 # Number of loads that had data forwarded from stores
+system.cpu1.iq.FU_type_0::total 62006899 # Type of FU issued
+system.cpu1.iq.rate 0.264043 # Inst issue rate
+system.cpu1.iq.fu_busy_cnt 4388325 # FU busy when requested
+system.cpu1.iq.fu_busy_rate 0.070772 # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads 204523942 # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes 59086561 # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses 43409940 # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.fp_inst_queue_reads 11938 # Number of floating instruction queue reads
+system.cpu1.iq.fp_inst_queue_writes 6483 # Number of floating instruction queue writes
+system.cpu1.iq.fp_inst_queue_wakeup_accesses 5383 # Number of floating instruction queue wakeup accesses
+system.cpu1.iq.int_alu_accesses 66196788 # Number of integer alu accesses
+system.cpu1.iq.fp_alu_accesses 6338 # Number of floating point alu accesses
+system.cpu1.iew.lsq.thread0.forwLoads 319760 # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads 2060794 # Number of loads squashed
-system.cpu1.iew.lsq.thread0.ignoredResponses 3248 # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation 14926 # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores 795522 # Number of stores squashed
+system.cpu1.iew.lsq.thread0.squashedLoads 2083716 # Number of loads squashed
+system.cpu1.iew.lsq.thread0.ignoredResponses 3064 # Number of memory responses ignored because the instruction is squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation 15874 # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores 772589 # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu1.iew.lsq.thread0.rescheduledLoads 17225652 # Number of loads that were rescheduled
-system.cpu1.iew.lsq.thread0.cacheBlocked 391932 # Number of times an access to memory failed due to the cache being blocked
+system.cpu1.iew.lsq.thread0.rescheduledLoads 16902604 # Number of loads that were rescheduled
+system.cpu1.iew.lsq.thread0.cacheBlocked 332952 # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles 1576672 # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles 14666749 # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles 228879 # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts 48476685 # Number of instructions dispatched to IQ
-system.cpu1.iew.iewDispSquashedInsts 98660 # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts 9803560 # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts 6552959 # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts 716609 # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents 50437 # Number of times the IQ has become full, causing a stall
-system.cpu1.iew.iewLSQFullEvents 9701 # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents 14926 # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect 170356 # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect 133051 # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts 303407 # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts 60276255 # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts 26034557 # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts 1047592 # Number of squashed instructions skipped in execute
+system.cpu1.iew.iewSquashCycles 1558997 # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles 14375191 # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles 227377 # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts 49504406 # Number of instructions dispatched to IQ
+system.cpu1.iew.iewDispSquashedInsts 98291 # Number of squashed instructions skipped by dispatch
+system.cpu1.iew.iewDispLoadInsts 10070258 # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts 6501681 # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts 727587 # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents 51733 # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewLSQFullEvents 9370 # Number of times the LSQ has become full, causing a stall
+system.cpu1.iew.memOrderViolationEvents 15874 # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect 179251 # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect 141654 # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts 320905 # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts 60955471 # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts 25970384 # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts 1051428 # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp 0 # number of swp insts executed
-system.cpu1.iew.exec_nop 104499 # number of nop insts executed
-system.cpu1.iew.exec_refs 32021114 # number of memory reference insts executed
-system.cpu1.iew.exec_branches 5717498 # Number of branches executed
-system.cpu1.iew.exec_stores 5986557 # Number of stores executed
-system.cpu1.iew.exec_rate 0.252464 # Inst execution rate
-system.cpu1.iew.wb_sent 59765334 # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count 42391160 # cumulative count of insts written-back
-system.cpu1.iew.wb_producers 23307297 # num instructions producing a value
-system.cpu1.iew.wb_consumers 43055480 # num instructions consuming a value
+system.cpu1.iew.exec_nop 120626 # number of nop insts executed
+system.cpu1.iew.exec_refs 31928214 # number of memory reference insts executed
+system.cpu1.iew.exec_branches 5888736 # Number of branches executed
+system.cpu1.iew.exec_stores 5957830 # Number of stores executed
+system.cpu1.iew.exec_rate 0.259565 # Inst execution rate
+system.cpu1.iew.wb_sent 60476945 # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count 43415323 # cumulative count of insts written-back
+system.cpu1.iew.wb_producers 24094324 # num instructions producing a value
+system.cpu1.iew.wb_consumers 44023151 # num instructions consuming a value
system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu1.iew.wb_rate 0.177553 # insts written-back per cycle
-system.cpu1.iew.wb_fanout 0.541332 # average fanout of values written-back
+system.cpu1.iew.wb_rate 0.184874 # insts written-back per cycle
+system.cpu1.iew.wb_fanout 0.547310 # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu1.commit.commitSquashedInsts 9596314 # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls 764035 # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts 262671 # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples 74883149 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean 0.513666 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev 1.490214 # Number of insts commited each cycle
+system.cpu1.commit.commitSquashedInsts 9567264 # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls 759276 # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts 277731 # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples 74432072 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean 0.530472 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev 1.515537 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0 61098286 81.59% 81.59% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1 6805438 9.09% 90.68% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2 1903916 2.54% 93.22% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3 1064936 1.42% 94.64% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4 1018174 1.36% 96.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5 531111 0.71% 96.71% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6 691593 0.92% 97.64% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7 378534 0.51% 98.14% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8 1391161 1.86% 100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0 60336914 81.06% 81.06% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1 6930423 9.31% 90.37% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2 1972494 2.65% 93.02% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3 1094851 1.47% 94.50% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4 1021489 1.37% 95.87% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5 524731 0.70% 96.57% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6 707921 0.95% 97.52% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7 378966 0.51% 98.03% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8 1464283 1.97% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total 74883149 # Number of insts commited each cycle
-system.cpu1.commit.committedInsts 29982419 # Number of instructions committed
-system.cpu1.commit.committedOps 38464913 # Number of ops (including micro ops) committed
+system.cpu1.commit.committed_per_cycle::total 74432072 # Number of insts commited each cycle
+system.cpu1.commit.committedInsts 31082580 # Number of instructions committed
+system.cpu1.commit.committedOps 39484127 # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu1.commit.refs 13500203 # Number of memory references committed
-system.cpu1.commit.loads 7742766 # Number of loads committed
-system.cpu1.commit.membars 202217 # Number of memory barriers committed
-system.cpu1.commit.branches 4992962 # Number of branches committed
-system.cpu1.commit.fp_insts 4763 # Number of committed floating point instructions.
-system.cpu1.commit.int_insts 33994528 # Number of committed integer instructions.
-system.cpu1.commit.function_calls 502375 # Number of function calls committed.
-system.cpu1.commit.bw_lim_events 1391161 # number cycles where commit BW limit reached
+system.cpu1.commit.refs 13715634 # Number of memory references committed
+system.cpu1.commit.loads 7986542 # Number of loads committed
+system.cpu1.commit.membars 202747 # Number of memory barriers committed
+system.cpu1.commit.branches 5103464 # Number of branches committed
+system.cpu1.commit.fp_insts 5321 # Number of committed floating point instructions.
+system.cpu1.commit.int_insts 34903456 # Number of committed integer instructions.
+system.cpu1.commit.function_calls 500366 # Number of function calls committed.
+system.cpu1.commit.bw_lim_events 1464283 # number cycles where commit BW limit reached
system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu1.rob.rob_reads 120638730 # The number of ROB reads
-system.cpu1.rob.rob_writes 97745041 # The number of ROB writes
-system.cpu1.timesIdled 886317 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles 162292323 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.quiesceCycles 2286407630 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts 29911740 # Number of Instructions Simulated
-system.cpu1.committedOps 38394234 # Number of Ops (including micro ops) Simulated
-system.cpu1.committedInsts_total 29911740 # Number of Instructions Simulated
-system.cpu1.cpi 7.981888 # CPI: Cycles Per Instruction
-system.cpu1.cpi_total 7.981888 # CPI: Total CPI of All Threads
-system.cpu1.ipc 0.125284 # IPC: Instructions Per Cycle
-system.cpu1.ipc_total 0.125284 # IPC: Total IPC of All Threads
-system.cpu1.int_regfile_reads 272364887 # number of integer regfile reads
-system.cpu1.int_regfile_writes 43577017 # number of integer regfile writes
-system.cpu1.fp_regfile_reads 22187 # number of floating regfile reads
-system.cpu1.fp_regfile_writes 19914 # number of floating regfile writes
-system.cpu1.misc_regfile_reads 14848508 # number of misc regfile reads
-system.cpu1.misc_regfile_writes 429527 # number of misc regfile writes
-system.iocache.tags.replacements 0 # number of replacements
-system.iocache.tags.tagsinuse 0 # Cycle average of tags in use
-system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks.
-system.iocache.tags.avg_refs nan # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu1.rob.rob_reads 121076761 # The number of ROB reads
+system.cpu1.rob.rob_writes 99705340 # The number of ROB writes
+system.cpu1.timesIdled 873554 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu1.idleCycles 158845680 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu1.quiesceCycles 2319747272 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.committedInsts 31000692 # Number of Instructions Simulated
+system.cpu1.committedOps 39402239 # Number of Ops (including micro ops) Simulated
+system.cpu1.committedInsts_total 31000692 # Number of Instructions Simulated
+system.cpu1.cpi 7.575210 # CPI: Cycles Per Instruction
+system.cpu1.cpi_total 7.575210 # CPI: Total CPI of All Threads
+system.cpu1.ipc 0.132010 # IPC: Instructions Per Cycle
+system.cpu1.ipc_total 0.132010 # IPC: Total IPC of All Threads
+system.cpu1.int_regfile_reads 276194442 # number of integer regfile reads
+system.cpu1.int_regfile_writes 44861664 # number of integer regfile writes
+system.cpu1.fp_regfile_reads 22699 # number of floating regfile reads
+system.cpu1.fp_regfile_writes 19852 # number of floating regfile writes
+system.cpu1.misc_regfile_reads 15196533 # number of misc regfile reads
+system.cpu1.misc_regfile_writes 431717 # number of misc regfile writes
+system.iocache.tags.replacements 0 # number of replacements
+system.iocache.tags.tagsinuse 0 # Cycle average of tags in use
+system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
+system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks.
+system.iocache.tags.avg_refs nan # Average number of references to valid blocks.
+system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1453044953007 # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 1453044953007 # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1453044953007 # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 1453044953007 # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1441896554007 # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 1441896554007 # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1441896554007 # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 1441896554007 # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
---------- Begin Simulation Statistics ----------
-sim_seconds 2.630645 # Number of seconds simulated
-sim_ticks 2630645085500 # Number of ticks simulated
-final_tick 2630645085500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 2.630640 # Number of seconds simulated
+sim_ticks 2630640106500 # Number of ticks simulated
+final_tick 2630640106500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 281405 # Simulator instruction rate (inst/s)
-host_op_rate 358084 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 12294669184 # Simulator tick rate (ticks/s)
-host_mem_usage 398476 # Number of bytes of host memory used
-host_seconds 213.97 # Real time elapsed on the host
-sim_insts 60211229 # Number of instructions simulated
-sim_ops 76617937 # Number of ops (including micro ops) simulated
+host_inst_rate 544255 # Simulator instruction rate (inst/s)
+host_op_rate 692557 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 23778611565 # Simulator tick rate (ticks/s)
+host_mem_usage 394548 # Number of bytes of host memory used
+host_seconds 110.63 # Real time elapsed on the host
+sim_insts 60211209 # Number of instructions simulated
+sim_ops 76617916 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::realview.clcd 124256256 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst 305952 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 4748752 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst 310496 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 4767440 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 398080 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 4312560 # Number of bytes read from this memory
-system.physmem.bytes_read::total 134021792 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 305952 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 398080 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 704032 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 3690176 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0.data 1535008 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu1.data 1481144 # Number of bytes written to this memory
-system.physmem.bytes_written::total 6706328 # Number of bytes written to this memory
+system.physmem.bytes_read::cpu1.inst 393856 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 4293936 # Number of bytes read from this memory
+system.physmem.bytes_read::total 134022176 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 310496 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 393856 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 704352 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 3690624 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu0.data 1534960 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu1.data 1481192 # Number of bytes written to this memory
+system.physmem.bytes_written::total 6706776 # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd 15532032 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst 10983 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 74233 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst 11054 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 74525 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 6220 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 67410 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 15690881 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 57659 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0.data 383752 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu1.data 370286 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 811697 # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd 47234139 # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_reads::cpu1.inst 6154 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 67119 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 15690887 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 57666 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu0.data 383740 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu1.data 370298 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 811704 # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd 47234229 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 49 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst 116303 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 1805166 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst 118031 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 1812274 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker 24 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 151324 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 1639355 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 50946360 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 116303 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 151324 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 267627 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1402765 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data 583510 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1.data 563035 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 2549309 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1402765 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd 47234139 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 149719 # Total read bandwidth from this memory (bytes/s)
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+system.physmem.bw_inst_read::cpu0.inst 118031 # Instruction read bandwidth from this memory (bytes/s)
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+system.physmem.bw_inst_read::total 267749 # Instruction read bandwidth from this memory (bytes/s)
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+system.physmem.bw_write::cpu0.data 583493 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::cpu0.itb.walker 49 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 116303 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 2388676 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.dtb.walker 24 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 151324 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 2202389 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 53495669 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 15690881 # Total number of read requests seen
-system.physmem.writeReqs 811697 # Total number of write requests seen
-system.physmem.cpureqs 214350 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 1004216384 # Total number of bytes read from memory
-system.physmem.bytesWritten 51948608 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 134021792 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 6706328 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 26 # Number of read reqs serviced by write Q
+system.physmem.bw_total::cpu1.inst 149719 # Total bandwidth to/from this memory (bytes/s)
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+system.physmem.bw_total::total 53496087 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 15690887 # Total number of read requests accepted by DRAM controller
+system.physmem.writeReqs 811704 # Total number of write requests accepted by DRAM controller
+system.physmem.readBursts 15690887 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
+system.physmem.writeBursts 811704 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
+system.physmem.bytesRead 1004216768 # Total number of bytes read from memory
+system.physmem.bytesWritten 51949056 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 134022176 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 6706776 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 29 # Number of DRAM read bursts serviced by write Q
system.physmem.neitherReadNorWrite 4522 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 980391 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 980205 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 980221 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::3 980428 # Track reads on a per bank basis
system.physmem.perBankRdReqs::4 986950 # Track reads on a per bank basis
system.physmem.perBankRdReqs::5 980709 # Track reads on a per bank basis
system.physmem.perBankRdReqs::6 980611 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 980417 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 980420 # Track reads on a per bank basis
system.physmem.perBankRdReqs::8 980615 # Track reads on a per bank basis
system.physmem.perBankRdReqs::9 980431 # Track reads on a per bank basis
system.physmem.perBankRdReqs::10 979815 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 979554 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::12 980154 # Track reads on a per bank basis
system.physmem.perBankRdReqs::13 980076 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::15 980109 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 49158 # Track writes on a per bank basis
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-system.physmem.perBankWrReqs::14 50830 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15 50810 # Track writes on a per bank basis
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+system.physmem.perBankWrReqs::15 6624 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 2630640666000 # Total gap between requests
+system.physmem.totGap 2630635687000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 6680 # Categorize read packet sizes
system.physmem.readPktSize::3 15532032 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 152169 # Categorize read packet sizes
+system.physmem.readPktSize::6 152175 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
system.physmem.writePktSize::2 754038 # Categorize write packet sizes
system.physmem.writePktSize::3 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
-system.physmem.writePktSize::6 57659 # Categorize write packet sizes
-system.physmem.rdQLenPdf::0 1131442 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 37996 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 27796.675861 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 2568.021256 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 33333.179984 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::64-127 5396 14.20% 14.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-191 3321 8.74% 22.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::192-255 2191 5.77% 28.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-319 1656 4.36% 33.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::320-383 1158 3.05% 36.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-447 1048 2.76% 38.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::448-511 789 2.08% 40.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-575 726 1.91% 42.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::576-639 577 1.52% 44.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-703 474 1.25% 45.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::704-767 440 1.16% 46.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-831 388 1.02% 47.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::832-895 251 0.66% 48.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-959 273 0.72% 49.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::960-1023 221 0.58% 49.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1087 258 0.68% 50.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1088-1151 159 0.42% 50.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1152-1215 126 0.33% 51.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1216-1279 108 0.28% 51.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1280-1343 95 0.25% 51.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1344-1407 80 0.21% 51.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1408-1471 156 0.41% 52.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1472-1535 779 2.05% 54.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1536-1599 205 0.54% 54.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1600-1663 146 0.38% 55.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1664-1727 108 0.28% 55.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1728-1791 84 0.22% 55.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1792-1855 80 0.21% 56.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1856-1919 53 0.14% 56.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1920-1983 48 0.13% 56.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1984-2047 45 0.12% 56.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2048-2111 58 0.15% 56.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2112-2175 47 0.12% 56.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2176-2239 19 0.05% 56.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2240-2303 26 0.07% 56.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2304-2367 22 0.06% 56.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2368-2431 18 0.05% 56.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2432-2495 19 0.05% 56.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2496-2559 19 0.05% 57.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2560-2623 11 0.03% 57.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2624-2687 11 0.03% 57.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2688-2751 13 0.03% 57.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2752-2815 9 0.02% 57.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2816-2879 7 0.02% 57.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2880-2943 8 0.02% 57.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2944-3007 10 0.03% 57.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3008-3071 7 0.02% 57.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3072-3135 16 0.04% 57.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3136-3199 3 0.01% 57.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3200-3263 9 0.02% 57.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3264-3327 9 0.02% 57.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3328-3391 4 0.01% 57.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3392-3455 6 0.02% 57.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3456-3519 5 0.01% 57.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3520-3583 5 0.01% 57.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3584-3647 15 0.04% 57.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3648-3711 11 0.03% 57.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3712-3775 13 0.03% 57.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3776-3839 8 0.02% 57.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3840-3903 9 0.02% 57.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3904-3967 6 0.02% 57.54% # Bytes accessed per row activation
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-system.physmem.bytesPerActivate::4032-4095 8 0.02% 57.57% # Bytes accessed per row activation
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-system.physmem.bytesPerActivate::4352-4415 7 0.02% 57.70% # Bytes accessed per row activation
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-system.physmem.bytesPerActivate::4608-4671 6 0.02% 57.75% # Bytes accessed per row activation
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-system.physmem.bytesPerActivate::5120-5183 7 0.02% 57.80% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::mean 26627.977877 # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::12800-12863 1 0.00% 59.98% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::14080-14143 1 0.00% 59.98% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::14336-14399 1 0.00% 59.99% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::15360-15423 2 0.01% 59.99% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::16128-16191 1 0.00% 59.99% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::16384-16447 2 0.01% 60.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::17152-17215 1 0.00% 60.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::18176-18239 1 0.00% 60.01% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::19456-19519 1 0.00% 60.01% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::20992-21055 1 0.00% 60.01% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::23296-23359 1 0.00% 60.01% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::23552-23615 1 0.00% 60.02% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::27136-27199 1 0.00% 60.02% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::27648-27711 1 0.00% 60.02% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::27904-27967 1 0.00% 60.02% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::29696-29759 3 0.01% 60.03% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::29952-30015 1 0.00% 60.03% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::30464-30527 1 0.00% 60.04% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::30720-30783 1 0.00% 60.04% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::30976-31039 1 0.00% 60.04% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::31744-31807 1 0.00% 60.05% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::32512-32575 1 0.00% 60.05% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::33024-33087 7 0.02% 60.07% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::33280-33343 12 0.03% 60.10% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::33792-33855 1 0.00% 60.10% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::65536-65599 15142 39.88% 99.99% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::67392-67455 1 0.00% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::420352-420415 1 0.00% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 37996 # Bytes accessed per row activation
-system.physmem.totQLat 300645538000 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 395312713000 # Sum of mem lat for all requests
-system.physmem.totBusLat 78454275000 # Total cycles spent in databus access
-system.physmem.totBankLat 16212900000 # Total cycles spent in bank access
-system.physmem.avgQLat 19160.56 # Average queueing delay per request
-system.physmem.avgBankLat 1033.27 # Average bank access latency per request
+system.physmem.bytesPerActivate::total 37970 # Bytes accessed per row activation
+system.physmem.totQLat 300039544000 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 394721941500 # Sum of mem lat for all requests
+system.physmem.totBusLat 78454290000 # Total cycles spent in databus access
+system.physmem.totBankLat 16228107500 # Total cycles spent in bank access
+system.physmem.avgQLat 19121.93 # Average queueing delay per request
+system.physmem.avgBankLat 1034.24 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 25193.83 # Average memory access latency
+system.physmem.avgMemAccLat 25156.17 # Average memory access latency
system.physmem.avgRdBW 381.74 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 19.75 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 50.95 # Average consumed read bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 3.14 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.15 # Average read queue length over time
-system.physmem.avgWrQLen 1.26 # Average write queue length over time
-system.physmem.readRowHits 15666172 # Number of row buffer hits during reads
-system.physmem.writeRowHits 798379 # Number of row buffer hits during writes
+system.physmem.avgWrQLen 1.25 # Average write queue length over time
+system.physmem.readRowHits 15666199 # Number of row buffer hits during reads
+system.physmem.writeRowHits 93719 # Number of row buffer hits during writes
system.physmem.readRowHitRate 99.84 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 98.36 # Row buffer hit rate for writes
-system.physmem.avgGap 159407.86 # Average gap between requests
+system.physmem.writeRowHitRate 11.55 # Row buffer hit rate for writes
+system.physmem.avgGap 159407.43 # Average gap between requests
system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput 54407285 # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq 16743607 # Transaction distribution
-system.membus.trans_dist::ReadResp 16743607 # Transaction distribution
+system.membus.throughput 54407704 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 16743613 # Transaction distribution
+system.membus.trans_dist::ReadResp 16743613 # Transaction distribution
system.membus.trans_dist::WriteReq 763392 # Transaction distribution
system.membus.trans_dist::WriteResp 763392 # Transaction distribution
-system.membus.trans_dist::Writeback 57659 # Transaction distribution
+system.membus.trans_dist::Writeback 57666 # Transaction distribution
system.membus.trans_dist::UpgradeReq 4522 # Transaction distribution
system.membus.trans_dist::UpgradeResp 4522 # Transaction distribution
system.membus.trans_dist::ReadExReq 131350 # Transaction distribution
system.membus.trans_dist::ReadExResp 131350 # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382988 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1892477 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 3860 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total 4279337 # Packet count per connected master and slave (bytes)
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system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 31064064 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 31064064 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::system.bridge.slave 2382988 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::system.physmem.port 32956541 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::system.realview.gic.pio 3860 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 35343401 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 35343420 # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2390393 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes)
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system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 7720 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::total 18870001 # Cumulative packet size per connected master and slave (bytes)
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system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 124256256 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::total 124256256 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::system.bridge.slave 2390393 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::system.physmem.port 140728120 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::system.realview.gic.pio 7720 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 143126257 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 143126257 # Total data (bytes)
+system.membus.tot_pkt_size::total 143127089 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 143127089 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy 1209137000 # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy 1209125000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer1.occupancy 5000 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 18109692000 # Layer occupancy (ticks)
-system.membus.reqLayer2.utilization 0.7 # Layer utilization (%)
-system.membus.reqLayer3.occupancy 3744500 # Layer occupancy (ticks)
-system.membus.reqLayer3.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer5.occupancy 1000 # Layer occupancy (ticks)
-system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer1.occupancy 4946454076 # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy 3743000 # Layer occupancy (ticks)
+system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
+system.membus.reqLayer4.occupancy 1000 # Layer occupancy (ticks)
+system.membus.reqLayer4.utilization 0.0 # Layer utilization (%)
+system.membus.reqLayer6.occupancy 18109707000 # Layer occupancy (ticks)
+system.membus.reqLayer6.utilization 0.7 # Layer utilization (%)
+system.membus.respLayer1.occupancy 4946568726 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
-system.membus.respLayer2.occupancy 35060518750 # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy 35058992750 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 1.3 # Layer utilization (%)
-system.l2c.tags.replacements 62055 # number of replacements
-system.l2c.tags.tagsinuse 51615.482729 # Cycle average of tags in use
-system.l2c.tags.total_refs 1699189 # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs 127440 # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs 13.333247 # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle 2575816655500 # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks 38219.751550 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000690 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst 2839.791296 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data 3005.850612 # Average occupied blocks per requestor
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-system.l2c.tags.occ_blocks::cpu1.data 3368.106163 # Average occupied blocks per requestor
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-system.l2c.Writeback_hits::writebacks 596408 # number of Writeback hits
-system.l2c.Writeback_hits::total 596408 # number of Writeback hits
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-system.l2c.UpgradeReq_hits::cpu1.data 9 # number of UpgradeReq hits
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system.l2c.UpgradeReq_hits::total 26 # number of UpgradeReq hits
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system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses
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system.l2c.UpgradeReq_misses::total 2881 # number of UpgradeReq misses
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-system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma 20327 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma 50707 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count 7549494 # Packet count per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 54749620 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 83783741 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma 28900 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma 79720 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size 138641981 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.data_through_bus 138641981 # Total data (bytes)
-system.toL2Bus.snoop_data_through_bus 170704 # Total snoop data (bytes)
-system.toL2Bus.reqLayer0.occupancy 4808390000 # Layer occupancy (ticks)
+system.toL2Bus.trans_dist::ReadExReq 247504 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 247504 # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1724904 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5753314 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 20307 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 50676 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 7549201 # Packet count per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 54747764 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 83776253 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 28860 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 79676 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size::total 138632553 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.data_through_bus 138632553 # Total data (bytes)
+system.toL2Bus.snoop_data_through_bus 170668 # Total snoop data (bytes)
+system.toL2Bus.reqLayer0.occupancy 4808102000 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy 3865864500 # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy 3865742750 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy 4428402674 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy 4428115774 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy 13102500 # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy 13092500 # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy 30777250 # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy 30757250 # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.throughput 48142811 # Throughput (bytes/s)
+system.iobus.throughput 48142902 # Throughput (bytes/s)
system.iobus.trans_dist::ReadReq 16715359 # Transaction distribution
system.iobus.trans_dist::ReadResp 16715359 # Transaction distribution
system.iobus.trans_dist::WriteReq 8167 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::total 2382988 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 31064064 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.clcd.dma::total 31064064 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.realview_io.pio 7944 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.timer0.pio 536 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.timer1.pio 1042 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.iocache.cpu_side 31064064 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total 33447052 # Packet count per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15888 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::total 2390393 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 124256256 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.realview.clcd.dma::total 124256256 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.realview_io.pio 15888 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.timer0.pio 1072 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.timer1.pio 2084 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.iocache.cpu_side 124256256 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::total 126646649 # Cumulative packet size per connected master and slave (bytes)
system.iobus.data_through_bus 126646649 # Total data (bytes)
system.iobus.reqLayer0.occupancy 21043000 # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%)
system.iobus.respLayer0.occupancy 2374821000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.1 # Layer utilization (%)
-system.iobus.respLayer1.occupancy 42579543250 # Layer occupancy (ticks)
+system.iobus.respLayer1.occupancy 42581193250 # Layer occupancy (ticks)
system.iobus.respLayer1.utilization 1.6 # Layer utilization (%)
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
-system.cpu0.dtb.read_hits 7541054 # DTB read hits
-system.cpu0.dtb.read_misses 7077 # DTB read misses
-system.cpu0.dtb.write_hits 5712165 # DTB write hits
-system.cpu0.dtb.write_misses 1789 # DTB write misses
+system.cpu0.dtb.read_hits 7542817 # DTB read hits
+system.cpu0.dtb.read_misses 7082 # DTB read misses
+system.cpu0.dtb.write_hits 5717425 # DTB write hits
+system.cpu0.dtb.write_misses 1778 # DTB write misses
system.cpu0.dtb.flush_tlb 1248 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid 735 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_mva_asid 734 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries 6540 # Number of entries that have been flushed from TLB
+system.cpu0.dtb.flush_entries 6542 # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults 146 # Number of TLB faults due to prefetch
+system.cpu0.dtb.prefetch_faults 149 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults 226 # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses 7548131 # DTB read accesses
-system.cpu0.dtb.write_accesses 5713954 # DTB write accesses
+system.cpu0.dtb.read_accesses 7549899 # DTB read accesses
+system.cpu0.dtb.write_accesses 5719203 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu0.dtb.hits 13253219 # DTB hits
-system.cpu0.dtb.misses 8866 # DTB misses
-system.cpu0.dtb.accesses 13262085 # DTB accesses
-system.cpu0.itb.inst_hits 30586267 # ITB inst hits
-system.cpu0.itb.inst_misses 3713 # ITB inst misses
+system.cpu0.dtb.hits 13260242 # DTB hits
+system.cpu0.dtb.misses 8860 # DTB misses
+system.cpu0.dtb.accesses 13269102 # DTB accesses
+system.cpu0.itb.inst_hits 30610477 # ITB inst hits
+system.cpu0.itb.inst_misses 3712 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
system.cpu0.itb.flush_tlb 1248 # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid 735 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_mva_asid 734 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries 2774 # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_entries 2775 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
-system.cpu0.itb.inst_accesses 30589980 # ITB inst accesses
-system.cpu0.itb.hits 30586267 # DTB hits
-system.cpu0.itb.misses 3713 # DTB misses
-system.cpu0.itb.accesses 30589980 # DTB accesses
-system.cpu0.numCycles 2629433969 # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses 30614189 # ITB inst accesses
+system.cpu0.itb.hits 30610477 # DTB hits
+system.cpu0.itb.misses 3712 # DTB misses
+system.cpu0.itb.accesses 30614189 # DTB accesses
+system.cpu0.numCycles 2629428479 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.committedInsts 29984771 # Number of instructions committed
-system.cpu0.committedOps 38337194 # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses 34488518 # Number of integer alu accesses
+system.cpu0.committedInsts 30009354 # Number of instructions committed
+system.cpu0.committedOps 38372334 # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses 34511671 # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses 5157 # Number of float alu accesses
-system.cpu0.num_func_calls 1080132 # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts 3980914 # number of instructions that are conditional controls
-system.cpu0.num_int_insts 34488518 # number of integer instructions
+system.cpu0.num_func_calls 1080838 # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts 3989390 # number of instructions that are conditional controls
+system.cpu0.num_int_insts 34511671 # number of integer instructions
system.cpu0.num_fp_insts 5157 # number of float instructions
-system.cpu0.num_int_register_reads 197896297 # number of times the integer registers were read
-system.cpu0.num_int_register_writes 36953400 # number of times the integer registers were written
+system.cpu0.num_int_register_reads 198034256 # number of times the integer registers were read
+system.cpu0.num_int_register_writes 36980567 # number of times the integer registers were written
system.cpu0.num_fp_register_reads 3554 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 1606 # number of times the floating registers were written
-system.cpu0.num_mem_refs 13834370 # number of memory refs
-system.cpu0.num_load_insts 7870253 # Number of load instructions
-system.cpu0.num_store_insts 5964117 # Number of store instructions
-system.cpu0.num_idle_cycles -1415422.936618 # Number of idle cycles
-system.cpu0.num_busy_cycles 2630849391.936618 # Number of busy cycles
-system.cpu0.not_idle_fraction 1.000538 # Percentage of non-idle cycles
-system.cpu0.idle_fraction -0.000538 # Percentage of idle cycles
+system.cpu0.num_mem_refs 13842126 # number of memory refs
+system.cpu0.num_load_insts 7871888 # Number of load instructions
+system.cpu0.num_store_insts 5970238 # Number of store instructions
+system.cpu0.num_idle_cycles 2283161569.446249 # Number of idle cycles
+system.cpu0.num_busy_cycles 346266909.553751 # Number of busy cycles
+system.cpu0.not_idle_fraction 0.131689 # Percentage of non-idle cycles
+system.cpu0.idle_fraction 0.868311 # Percentage of idle cycles
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
system.cpu0.kern.inst.quiesce 83028 # number of quiesce instructions executed
-system.cpu0.icache.tags.replacements 856159 # number of replacements
-system.cpu0.icache.tags.tagsinuse 510.881074 # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs 60648644 # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs 856671 # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs 70.795724 # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle 19966906250 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst 210.109344 # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu1.inst 300.771730 # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst 0.410370 # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu1.inst 0.587445 # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total 0.997815 # Average percentage of cache occupancy
-system.cpu0.icache.ReadReq_hits::cpu0.inst 30145271 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu1.inst 30503373 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total 60648644 # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst 30145271 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu1.inst 30503373 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total 60648644 # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst 30145271 # number of overall hits
-system.cpu0.icache.overall_hits::cpu1.inst 30503373 # number of overall hits
-system.cpu0.icache.overall_hits::total 60648644 # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst 440996 # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu1.inst 415675 # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total 856671 # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst 440996 # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu1.inst 415675 # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total 856671 # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst 440996 # number of overall misses
-system.cpu0.icache.overall_misses::cpu1.inst 415675 # number of overall misses
-system.cpu0.icache.overall_misses::total 856671 # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 6006488500 # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 5787528750 # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total 11794017250 # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst 6006488500 # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::cpu1.inst 5787528750 # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total 11794017250 # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst 6006488500 # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::cpu1.inst 5787528750 # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total 11794017250 # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst 30586267 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu1.inst 30919048 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total 61505315 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst 30586267 # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu1.inst 30919048 # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total 61505315 # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst 30586267 # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu1.inst 30919048 # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total 61505315 # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014418 # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.013444 # miss rate for ReadReq accesses
+system.cpu0.icache.tags.replacements 856130 # number of replacements
+system.cpu0.icache.tags.tagsinuse 510.884273 # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs 60648659 # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs 856642 # Sample count of references to valid blocks.
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+system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.027195 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025190 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.023763 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024490 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.048585 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.044617 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.046658 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.026297 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025768 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total 0.026035 # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026297 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025768 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total 0.026035 # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12777.255202 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12673.845682 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12725.664628 # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 39889.324801 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 39839.238743 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 39865.454334 # average WriteReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11348.215727 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12384.292901 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11829.238754 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24022.879633 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 23357.598677 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23696.972963 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24022.879633 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 23357.598677 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23696.972963 # average overall mshr miss latency
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.048594 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.044613 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.046650 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.026241 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025820 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total 0.026033 # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026241 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025820 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total 0.026033 # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12766.546092 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12643.971981 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12705.226813 # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 39962.468278 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 39739.847519 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 39856.448910 # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11332.900503 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12381.369279 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11822.482263 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24070.378329 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 23278.747757 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23682.045532 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24070.378329 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 23278.747757 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23682.045532 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 7458653 # DTB read hits
-system.cpu1.dtb.read_misses 7094 # DTB read misses
-system.cpu1.dtb.write_hits 5520448 # DTB write hits
-system.cpu1.dtb.write_misses 1859 # DTB write misses
+system.cpu1.dtb.read_hits 7456887 # DTB read hits
+system.cpu1.dtb.read_misses 7096 # DTB read misses
+system.cpu1.dtb.write_hits 5515190 # DTB write hits
+system.cpu1.dtb.write_misses 1853 # DTB write misses
system.cpu1.dtb.flush_tlb 1247 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid 704 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_mva_asid 705 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries 6666 # Number of entries that have been flushed from TLB
+system.cpu1.dtb.flush_entries 6662 # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults 134 # Number of TLB faults due to prefetch
+system.cpu1.dtb.prefetch_faults 137 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults 226 # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses 7465747 # DTB read accesses
-system.cpu1.dtb.write_accesses 5522307 # DTB write accesses
+system.cpu1.dtb.read_accesses 7463983 # DTB read accesses
+system.cpu1.dtb.write_accesses 5517043 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dtb.hits 12979101 # DTB hits
-system.cpu1.dtb.misses 8953 # DTB misses
-system.cpu1.dtb.accesses 12988054 # DTB accesses
-system.cpu1.itb.inst_hits 30919048 # ITB inst hits
-system.cpu1.itb.inst_misses 3673 # ITB inst misses
+system.cpu1.dtb.hits 12972077 # DTB hits
+system.cpu1.dtb.misses 8949 # DTB misses
+system.cpu1.dtb.accesses 12981026 # DTB accesses
+system.cpu1.itb.inst_hits 30894824 # ITB inst hits
+system.cpu1.itb.inst_misses 3669 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
system.cpu1.itb.flush_tlb 1247 # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid 704 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_mva_asid 705 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries 2817 # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_entries 2813 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.inst_accesses 30922721 # ITB inst accesses
-system.cpu1.itb.hits 30919048 # DTB hits
-system.cpu1.itb.misses 3673 # DTB misses
-system.cpu1.itb.accesses 30922721 # DTB accesses
-system.cpu1.numCycles 2631856202 # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses 30898493 # ITB inst accesses
+system.cpu1.itb.hits 30894824 # DTB hits
+system.cpu1.itb.misses 3669 # DTB misses
+system.cpu1.itb.accesses 30898493 # DTB accesses
+system.cpu1.numCycles 2631851734 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.committedInsts 30226458 # Number of instructions committed
-system.cpu1.committedOps 38280743 # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses 34395206 # Number of integer alu accesses
+system.cpu1.committedInsts 30201855 # Number of instructions committed
+system.cpu1.committedOps 38245582 # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses 34372038 # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses 5112 # Number of float alu accesses
-system.cpu1.num_func_calls 1060216 # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts 3968456 # number of instructions that are conditional controls
-system.cpu1.num_int_insts 34395206 # number of integer instructions
+system.cpu1.num_func_calls 1059508 # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts 3959978 # number of instructions that are conditional controls
+system.cpu1.num_int_insts 34372038 # number of integer instructions
system.cpu1.num_fp_insts 5112 # number of float instructions
-system.cpu1.num_int_register_reads 196952140 # number of times the integer registers were read
-system.cpu1.num_int_register_writes 37242776 # number of times the integer registers were written
+system.cpu1.num_int_register_reads 196814123 # number of times the integer registers were read
+system.cpu1.num_int_register_writes 37215593 # number of times the integer registers were written
system.cpu1.num_fp_register_reads 3939 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 1174 # number of times the floating registers were written
-system.cpu1.num_mem_refs 13565505 # number of memory refs
-system.cpu1.num_load_insts 7793640 # Number of load instructions
-system.cpu1.num_store_insts 5771865 # Number of store instructions
-system.cpu1.num_idle_cycles 4920851591.451757 # Number of idle cycles
-system.cpu1.num_busy_cycles -2288995389.451757 # Number of busy cycles
-system.cpu1.not_idle_fraction -0.869727 # Percentage of non-idle cycles
-system.cpu1.idle_fraction 1.869727 # Percentage of idle cycles
+system.cpu1.num_mem_refs 13557754 # number of memory refs
+system.cpu1.num_load_insts 7792008 # Number of load instructions
+system.cpu1.num_store_insts 5765746 # Number of store instructions
+system.cpu1.num_idle_cycles 2293589601.195636 # Number of idle cycles
+system.cpu1.num_busy_cycles 338262132.804364 # Number of busy cycles
+system.cpu1.not_idle_fraction 0.128526 # Percentage of non-idle cycles
+system.cpu1.idle_fraction 0.871474 # Percentage of idle cycles
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
-system.iocache.tags.replacements 0 # number of replacements
-system.iocache.tags.tagsinuse 0 # Cycle average of tags in use
-system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks.
-system.iocache.tags.avg_refs nan # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.iocache.tags.replacements 0 # number of replacements
+system.iocache.tags.tagsinuse 0 # Cycle average of tags in use
+system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
+system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks.
+system.iocache.tags.avg_refs nan # Average number of references to valid blocks.
+system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1478947388250 # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 1478947388250 # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1478947388250 # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 1478947388250 # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1478384126250 # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 1478384126250 # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1478384126250 # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 1478384126250 # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
sim_ticks 5133762710000 # Number of ticks simulated
final_tick 5133762710000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 199223 # Simulator instruction rate (inst/s)
-host_op_rate 393808 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2508257843 # Simulator tick rate (ticks/s)
-host_mem_usage 730904 # Number of bytes of host memory used
-host_seconds 2046.74 # Real time elapsed on the host
+host_inst_rate 156198 # Simulator instruction rate (inst/s)
+host_op_rate 308758 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1966557914 # Simulator tick rate (ticks/s)
+host_mem_usage 728732 # Number of bytes of host memory used
+host_seconds 2610.53 # Real time elapsed on the host
sim_insts 407759186 # Number of instructions simulated
sim_ops 806023868 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::pc.south_bridge.ide 2444032 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 199738 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2097474 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 4626202 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 222526 # Total number of read requests seen
-system.physmem.writeReqs 148565 # Total number of write requests seen
-system.physmem.cpureqs 372829 # Reqs generatd by CPU via cache - shady
+system.physmem.readReqs 222526 # Total number of read requests accepted by DRAM controller
+system.physmem.writeReqs 148565 # Total number of write requests accepted by DRAM controller
+system.physmem.readBursts 222526 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
+system.physmem.writeBursts 148565 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
system.physmem.bytesRead 14241664 # Total number of bytes read from memory
system.physmem.bytesWritten 9508160 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 14241664 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 9508160 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 75 # Number of read reqs serviced by write Q
+system.physmem.servicedByWrQ 75 # Number of DRAM read bursts serviced by write Q
system.physmem.neitherReadNorWrite 1733 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 14338 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 13735 # Track reads on a per bank basis
system.membus.trans_dist::MessageResp 1642 # Transaction distribution
system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3284 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.apicbridge.master::total 3284 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 475204 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 470782 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 775072 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 475204 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1721058 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 132484 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 132484 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::system.physmem.port 607688 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::system.bridge.slave 470782 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::system.cpu.interrupts.pio 775072 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::system.cpu.interrupts.int_slave 3284 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 1856826 # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6568 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.apicbridge.master::total 6568 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18319104 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 241674 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1550141 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18319104 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 20110919 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5430720 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::total 5430720 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::system.physmem.port 23749824 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::system.bridge.slave 241674 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::system.cpu.interrupts.pio 1550141 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::system.cpu.interrupts.int_slave 6568 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total 25548207 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 25548207 # Total data (bytes)
system.membus.snoop_data_through_bus 646848 # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy 1608355497 # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy 250293000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer1.occupancy 250293000 # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy 583289000 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 583289000 # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy 3284000 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer3.occupancy 3284000 # Layer occupancy (ticks)
+system.membus.reqLayer3.occupancy 1608355497 # Layer occupancy (ticks)
system.membus.reqLayer3.utilization 0.0 # Layer utilization (%)
system.membus.respLayer0.occupancy 1642000 # Layer occupancy (ticks)
system.membus.respLayer0.utilization 0.0 # Layer utilization (%)
system.membus.respLayer2.utilization 0.1 # Layer utilization (%)
system.membus.respLayer4.occupancy 429399995 # Layer occupancy (ticks)
system.membus.respLayer4.utilization 0.0 # Layer utilization (%)
-system.iocache.tags.replacements 47574 # number of replacements
-system.iocache.tags.tagsinuse 0.103958 # Cycle average of tags in use
-system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs 47590 # Sample count of references to valid blocks.
-system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle 4992794933000 # Cycle when the warmup percentage was hit.
+system.iocache.tags.replacements 47574 # number of replacements
+system.iocache.tags.tagsinuse 0.103958 # Cycle average of tags in use
+system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
+system.iocache.tags.sampled_refs 47590 # Sample count of references to valid blocks.
+system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
+system.iocache.tags.warmup_cycle 4992794933000 # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.103958 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::pc.south_bridge.ide 0.006497 # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total 0.006497 # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total 0.006497 # Average percentage of cache occupancy
system.iocache.ReadReq_misses::pc.south_bridge.ide 909 # number of ReadReq misses
system.iocache.ReadReq_misses::total 909 # number of ReadReq misses
system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95258 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3284 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3284 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.apicbridge.slave 3284 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.pc.south_bridge.ide.pio 11134 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.pc.south_bridge.pic1.pio 78 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.pc.south_bridge.speaker.pio 427356 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.pc.i_dont_exist.pio 170 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.pc.com_1.pio 26980 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.iocache.cpu_side 95258 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total 569324 # Packet count per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 3027816 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6568 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 6568 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.apicbridge.slave 6568 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.pc.south_bridge.ide.pio 6712 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.pc.south_bridge.pic1.pio 39 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.pc.south_bridge.speaker.pio 213678 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.pc.i_dont_exist.pio 85 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.pc.com_1.pio 13490 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.iocache.cpu_side 3027816 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::total 3276058 # Cumulative packet size per connected master and slave (bytes)
system.iobus.data_through_bus 3276058 # Total data (bytes)
system.iobus.reqLayer0.occupancy 3920600 # Layer occupancy (ticks)
system.cpu.toL2Bus.trans_dist::UpgradeResp 2243 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 334736 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 288025 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1906694 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 6122854 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side 16266 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side 154977 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count 8200791 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 61010496 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 207591623 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb_walker_cache.mem_side 510912 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb_walker_cache.mem_side 5512832 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size 274625863 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1906694 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6122854 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 16266 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 154977 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 8200791 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61010496 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 207591623 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 510912 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5512832 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total 274625863 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus 274602311 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 551744 # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy 4037956918 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer3.occupancy 103328135 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.cpu.icache.tags.replacements 952820 # number of replacements
-system.cpu.icache.tags.tagsinuse 509.973198 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 7477461 # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs 953332 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 7.843502 # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle 147437101250 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 509.973198 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.996041 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.996041 # Average percentage of cache occupancy
+system.cpu.icache.tags.replacements 952820 # number of replacements
+system.cpu.icache.tags.tagsinuse 509.973198 # Cycle average of tags in use
+system.cpu.icache.tags.total_refs 7477461 # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs 953332 # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs 7.843502 # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle 147437101250 # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst 509.973198 # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst 0.996041 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total 0.996041 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 7477461 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 7477461 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 7477461 # number of demand (read+write) hits
system.cpu.icache.overall_avg_mshr_miss_latency::total 12310.982228 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.itb_walker_cache.tags.replacements 7402 # number of replacements
-system.cpu.itb_walker_cache.tags.tagsinuse 6.006857 # Cycle average of tags in use
-system.cpu.itb_walker_cache.tags.total_refs 21909 # Total number of references to valid blocks.
+system.cpu.itb_walker_cache.tags.tagsinuse 6.006857 # Cycle average of tags in use
+system.cpu.itb_walker_cache.tags.total_refs 21909 # Total number of references to valid blocks.
system.cpu.itb_walker_cache.tags.sampled_refs 7416 # Sample count of references to valid blocks.
-system.cpu.itb_walker_cache.tags.avg_refs 2.954288 # Average number of references to valid blocks.
+system.cpu.itb_walker_cache.tags.avg_refs 2.954288 # Average number of references to valid blocks.
system.cpu.itb_walker_cache.tags.warmup_cycle 5104253177000 # Cycle when the warmup percentage was hit.
system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 6.006857 # Average occupied blocks per requestor
system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.375429 # Average percentage of cache occupancy
system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9176.084873 # average overall mshr miss latency
system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dtb_walker_cache.tags.replacements 67804 # number of replacements
-system.cpu.dtb_walker_cache.tags.tagsinuse 13.886481 # Cycle average of tags in use
-system.cpu.dtb_walker_cache.tags.total_refs 92487 # Total number of references to valid blocks.
+system.cpu.dtb_walker_cache.tags.tagsinuse 13.886481 # Cycle average of tags in use
+system.cpu.dtb_walker_cache.tags.total_refs 92487 # Total number of references to valid blocks.
system.cpu.dtb_walker_cache.tags.sampled_refs 67819 # Sample count of references to valid blocks.
-system.cpu.dtb_walker_cache.tags.avg_refs 1.363733 # Average number of references to valid blocks.
+system.cpu.dtb_walker_cache.tags.avg_refs 1.363733 # Average number of references to valid blocks.
system.cpu.dtb_walker_cache.tags.warmup_cycle 5101460528500 # Cycle when the warmup percentage was hit.
system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 13.886481 # Average occupied blocks per requestor
system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.867905 # Average percentage of cache occupancy
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10369.244789 # average overall mshr miss latency
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10369.244789 # average overall mshr miss latency
system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements 1656828 # number of replacements
-system.cpu.dcache.tags.tagsinuse 511.997492 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 18985847 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 1657340 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 11.455614 # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle 38296250 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 511.997492 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.999995 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.999995 # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements 1656828 # number of replacements
+system.cpu.dcache.tags.tagsinuse 511.997492 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 18985847 # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs 1657340 # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 11.455614 # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle 38296250 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data 511.997492 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data 0.999995 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total 0.999995 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 10890330 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 10890330 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 8092849 # number of WriteReq hits
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements 111287 # number of replacements
-system.cpu.l2cache.tags.tagsinuse 64824.187334 # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs 3785036 # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs 175649 # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs 21.548862 # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.replacements 111287 # number of replacements
+system.cpu.l2cache.tags.tagsinuse 64824.187334 # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs 3785036 # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs 175649 # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs 21.548862 # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 50594.922506 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 9.467907 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.125935 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 3127.998862 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 11091.672124 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 3127.998862 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 11091.672124 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.772017 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000144 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.047729 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.169245 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total 0.989139 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total 0.989139 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 63059 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 6479 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.inst 937263 # number of ReadReq hits
sim_ticks 5304405061000 # Number of ticks simulated
final_tick 5304405061000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 226332 # Simulator instruction rate (inst/s)
-host_op_rate 434274 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 11093442301 # Simulator tick rate (ticks/s)
-host_mem_usage 870272 # Number of bytes of host memory used
-host_seconds 478.16 # Real time elapsed on the host
+host_inst_rate 96456 # Simulator instruction rate (inst/s)
+host_op_rate 185076 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 4727720712 # Simulator tick rate (ticks/s)
+host_mem_usage 825708 # Number of bytes of host memory used
+host_seconds 1121.98 # Real time elapsed on the host
sim_insts 108221987 # Number of instructions simulated
sim_ops 207651289 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::pc.south_bridge.ide 35104 # Number of bytes read from this memory
system.physmem.bw_total::cpu1.inst 32140877 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 9555659 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 225885267 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 804 # Total number of read requests seen
-system.physmem.writeReqs 46736 # Total number of write requests seen
-system.physmem.cpureqs 47256 # Reqs generatd by CPU via cache - shady
+system.physmem.readReqs 804 # Total number of read requests accepted by DRAM controller
+system.physmem.writeReqs 46736 # Total number of write requests accepted by DRAM controller
+system.physmem.readBursts 804 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
+system.physmem.writeBursts 46736 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
system.physmem.bytesRead 51456 # Total number of bytes read from memory
system.physmem.bytesWritten 2991104 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 35104 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 2991104 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
+system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis
system.piobus.pkt_count_system.cpu0.interrupts.int_master::total 1022 # Packet count per connected master and slave (bytes)
system.piobus.pkt_count_system.cpu1.interrupts.int_master::system.cpu0.interrupts.int_slave 1024 # Packet count per connected master and slave (bytes)
system.piobus.pkt_count_system.cpu1.interrupts.int_master::total 1024 # Packet count per connected master and slave (bytes)
-system.piobus.pkt_count::system.physmem.port 95080 # Packet count per connected master and slave (bytes)
-system.piobus.pkt_count::system.pc.south_bridge.cmos.pio 52 # Packet count per connected master and slave (bytes)
-system.piobus.pkt_count::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes)
-system.piobus.pkt_count::system.pc.south_bridge.ide.pio 11042 # Packet count per connected master and slave (bytes)
-system.piobus.pkt_count::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes)
-system.piobus.pkt_count::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes)
-system.piobus.pkt_count::system.pc.south_bridge.pic1.pio 94 # Packet count per connected master and slave (bytes)
-system.piobus.pkt_count::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes)
-system.piobus.pkt_count::system.pc.south_bridge.pit.pio 33204 # Packet count per connected master and slave (bytes)
-system.piobus.pkt_count::system.pc.south_bridge.speaker.pio 938970 # Packet count per connected master and slave (bytes)
-system.piobus.pkt_count::system.pc.south_bridge.io_apic.pio 1372 # Packet count per connected master and slave (bytes)
-system.piobus.pkt_count::system.pc.i_dont_exist.pio 33352 # Packet count per connected master and slave (bytes)
-system.piobus.pkt_count::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes)
-system.piobus.pkt_count::system.pc.com_1.pio 26412 # Packet count per connected master and slave (bytes)
-system.piobus.pkt_count::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes)
-system.piobus.pkt_count::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes)
-system.piobus.pkt_count::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes)
-system.piobus.pkt_count::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes)
-system.piobus.pkt_count::system.cpu0.interrupts.pio 751802 # Packet count per connected master and slave (bytes)
-system.piobus.pkt_count::system.cpu0.interrupts.int_slave 2728 # Packet count per connected master and slave (bytes)
-system.piobus.pkt_count::system.cpu1.interrupts.pio 8324 # Packet count per connected master and slave (bytes)
-system.piobus.pkt_count::system.cpu1.interrupts.int_slave 2670 # Packet count per connected master and slave (bytes)
-system.piobus.pkt_count::system.pc.pciconfig.pio 2126 # Packet count per connected master and slave (bytes)
system.piobus.pkt_count::total 1908880 # Packet count per connected master and slave (bytes)
system.piobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.physmem.port 3026208 # Cumulative packet size per connected master and slave (bytes)
system.piobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 3026208 # Cumulative packet size per connected master and slave (bytes)
system.piobus.tot_pkt_size_system.cpu0.interrupts.int_master::total 2044 # Cumulative packet size per connected master and slave (bytes)
system.piobus.tot_pkt_size_system.cpu1.interrupts.int_master::system.cpu0.interrupts.int_slave 2048 # Cumulative packet size per connected master and slave (bytes)
system.piobus.tot_pkt_size_system.cpu1.interrupts.int_master::total 2048 # Cumulative packet size per connected master and slave (bytes)
-system.piobus.tot_pkt_size::system.physmem.port 3026208 # Cumulative packet size per connected master and slave (bytes)
-system.piobus.tot_pkt_size::system.pc.south_bridge.cmos.pio 26 # Cumulative packet size per connected master and slave (bytes)
-system.piobus.tot_pkt_size::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes)
-system.piobus.tot_pkt_size::system.pc.south_bridge.ide.pio 6660 # Cumulative packet size per connected master and slave (bytes)
-system.piobus.tot_pkt_size::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes)
-system.piobus.tot_pkt_size::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes)
-system.piobus.tot_pkt_size::system.pc.south_bridge.pic1.pio 47 # Cumulative packet size per connected master and slave (bytes)
-system.piobus.tot_pkt_size::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes)
-system.piobus.tot_pkt_size::system.pc.south_bridge.pit.pio 16602 # Cumulative packet size per connected master and slave (bytes)
-system.piobus.tot_pkt_size::system.pc.south_bridge.speaker.pio 469485 # Cumulative packet size per connected master and slave (bytes)
-system.piobus.tot_pkt_size::system.pc.south_bridge.io_apic.pio 2744 # Cumulative packet size per connected master and slave (bytes)
-system.piobus.tot_pkt_size::system.pc.i_dont_exist.pio 16676 # Cumulative packet size per connected master and slave (bytes)
-system.piobus.tot_pkt_size::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes)
-system.piobus.tot_pkt_size::system.pc.com_1.pio 13206 # Cumulative packet size per connected master and slave (bytes)
-system.piobus.tot_pkt_size::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes)
-system.piobus.tot_pkt_size::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes)
-system.piobus.tot_pkt_size::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes)
-system.piobus.tot_pkt_size::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes)
-system.piobus.tot_pkt_size::system.cpu0.interrupts.pio 1503598 # Cumulative packet size per connected master and slave (bytes)
-system.piobus.tot_pkt_size::system.cpu0.interrupts.int_slave 5456 # Cumulative packet size per connected master and slave (bytes)
-system.piobus.tot_pkt_size::system.cpu1.interrupts.pio 16645 # Cumulative packet size per connected master and slave (bytes)
-system.piobus.tot_pkt_size::system.cpu1.interrupts.int_slave 5340 # Cumulative packet size per connected master and slave (bytes)
-system.piobus.tot_pkt_size::system.pc.pciconfig.pio 4252 # Cumulative packet size per connected master and slave (bytes)
system.piobus.tot_pkt_size::total 5087902 # Cumulative packet size per connected master and slave (bytes)
system.piobus.data_through_bus 5087902 # Total data (bytes)
-system.piobus.reqLayer0.occupancy 421716677 # Layer occupancy (ticks)
+system.piobus.reqLayer0.occupancy 49000 # Layer occupancy (ticks)
system.piobus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.piobus.reqLayer1.occupancy 49000 # Layer occupancy (ticks)
+system.piobus.reqLayer1.occupancy 7500 # Layer occupancy (ticks)
system.piobus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.piobus.reqLayer2.occupancy 7500 # Layer occupancy (ticks)
+system.piobus.reqLayer2.occupancy 10159500 # Layer occupancy (ticks)
system.piobus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.piobus.reqLayer3.occupancy 10159500 # Layer occupancy (ticks)
+system.piobus.reqLayer3.occupancy 140500 # Layer occupancy (ticks)
system.piobus.reqLayer3.utilization 0.0 # Layer utilization (%)
-system.piobus.reqLayer4.occupancy 140500 # Layer occupancy (ticks)
+system.piobus.reqLayer4.occupancy 1061000 # Layer occupancy (ticks)
system.piobus.reqLayer4.utilization 0.0 # Layer utilization (%)
-system.piobus.reqLayer5.occupancy 1061000 # Layer occupancy (ticks)
+system.piobus.reqLayer5.occupancy 97000 # Layer occupancy (ticks)
system.piobus.reqLayer5.utilization 0.0 # Layer utilization (%)
-system.piobus.reqLayer6.occupancy 97000 # Layer occupancy (ticks)
+system.piobus.reqLayer6.occupancy 57000 # Layer occupancy (ticks)
system.piobus.reqLayer6.utilization 0.0 # Layer utilization (%)
-system.piobus.reqLayer7.occupancy 57000 # Layer occupancy (ticks)
+system.piobus.reqLayer7.occupancy 30437500 # Layer occupancy (ticks)
system.piobus.reqLayer7.utilization 0.0 # Layer utilization (%)
-system.piobus.reqLayer8.occupancy 30437500 # Layer occupancy (ticks)
+system.piobus.reqLayer8.occupancy 586857000 # Layer occupancy (ticks)
system.piobus.reqLayer8.utilization 0.0 # Layer utilization (%)
-system.piobus.reqLayer9.occupancy 586857000 # Layer occupancy (ticks)
+system.piobus.reqLayer9.occupancy 1329000 # Layer occupancy (ticks)
system.piobus.reqLayer9.utilization 0.0 # Layer utilization (%)
-system.piobus.reqLayer10.occupancy 1329000 # Layer occupancy (ticks)
+system.piobus.reqLayer10.occupancy 33375500 # Layer occupancy (ticks)
system.piobus.reqLayer10.utilization 0.0 # Layer utilization (%)
-system.piobus.reqLayer11.occupancy 33375500 # Layer occupancy (ticks)
+system.piobus.reqLayer11.occupancy 2000 # Layer occupancy (ticks)
system.piobus.reqLayer11.utilization 0.0 # Layer utilization (%)
-system.piobus.reqLayer12.occupancy 2000 # Layer occupancy (ticks)
+system.piobus.reqLayer12.occupancy 23058500 # Layer occupancy (ticks)
system.piobus.reqLayer12.utilization 0.0 # Layer utilization (%)
-system.piobus.reqLayer13.occupancy 23058500 # Layer occupancy (ticks)
+system.piobus.reqLayer13.occupancy 10500 # Layer occupancy (ticks)
system.piobus.reqLayer13.utilization 0.0 # Layer utilization (%)
system.piobus.reqLayer14.occupancy 10500 # Layer occupancy (ticks)
system.piobus.reqLayer14.utilization 0.0 # Layer utilization (%)
system.piobus.reqLayer15.utilization 0.0 # Layer utilization (%)
system.piobus.reqLayer16.occupancy 10500 # Layer occupancy (ticks)
system.piobus.reqLayer16.utilization 0.0 # Layer utilization (%)
-system.piobus.reqLayer17.occupancy 10500 # Layer occupancy (ticks)
+system.piobus.reqLayer17.occupancy 473807500 # Layer occupancy (ticks)
system.piobus.reqLayer17.utilization 0.0 # Layer utilization (%)
-system.piobus.reqLayer18.occupancy 473807500 # Layer occupancy (ticks)
+system.piobus.reqLayer18.occupancy 3197816 # Layer occupancy (ticks)
system.piobus.reqLayer18.utilization 0.0 # Layer utilization (%)
-system.piobus.reqLayer19.occupancy 3197816 # Layer occupancy (ticks)
+system.piobus.reqLayer19.occupancy 8805500 # Layer occupancy (ticks)
system.piobus.reqLayer19.utilization 0.0 # Layer utilization (%)
-system.piobus.reqLayer20.occupancy 8805500 # Layer occupancy (ticks)
+system.piobus.reqLayer20.occupancy 3140084 # Layer occupancy (ticks)
system.piobus.reqLayer20.utilization 0.0 # Layer utilization (%)
-system.piobus.reqLayer21.occupancy 3140084 # Layer occupancy (ticks)
+system.piobus.reqLayer21.occupancy 421716677 # Layer occupancy (ticks)
system.piobus.reqLayer21.utilization 0.0 # Layer utilization (%)
system.piobus.reqLayer22.occupancy 1081500 # Layer occupancy (ticks)
system.piobus.reqLayer22.utilization 0.0 # Layer utilization (%)
sim_ticks 5139589353000 # Number of ticks simulated
final_tick 5139589353000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 286755 # Simulator instruction rate (inst/s)
-host_op_rate 569759 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 6048900638 # Simulator tick rate (ticks/s)
-host_mem_usage 936564 # Number of bytes of host memory used
-host_seconds 849.67 # Real time elapsed on the host
+host_inst_rate 190335 # Simulator instruction rate (inst/s)
+host_op_rate 378180 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 4014985901 # Simulator tick rate (ticks/s)
+host_mem_usage 934028 # Number of bytes of host memory used
+host_seconds 1280.10 # Real time elapsed on the host
sim_insts 243647713 # Number of instructions simulated
sim_ops 484108731 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::pc.south_bridge.ide 2450688 # Number of bytes read from this memory
system.physmem.bw_total::cpu2.inst 72386 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.data 552150 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 4451182 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 96603 # Total number of read requests seen
-system.physmem.writeReqs 74912 # Total number of write requests seen
-system.physmem.cpureqs 172248 # Reqs generatd by CPU via cache - shady
+system.physmem.readReqs 96603 # Total number of read requests accepted by DRAM controller
+system.physmem.writeReqs 74912 # Total number of write requests accepted by DRAM controller
+system.physmem.readBursts 96603 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
+system.physmem.writeBursts 74912 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
system.physmem.bytesRead 6182592 # Total number of bytes read from memory
system.physmem.bytesWritten 4794368 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 6182592 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 4794368 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 12 # Number of read reqs serviced by write Q
+system.physmem.servicedByWrQ 12 # Number of DRAM read bursts serviced by write Q
system.physmem.neitherReadNorWrite 732 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 5743 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 5750 # Track reads on a per bank basis
system.membus.trans_dist::MessageResp 216 # Transaction distribution
system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave 432 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.apicbridge.master::total 432 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 219090 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 312952 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio 498180 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 219090 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total 1030222 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 54502 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 54502 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::system.physmem.port 273592 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::system.bridge.slave 312952 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::system.cpu0.interrupts.pio 498180 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::system.cpu0.interrupts.int_slave 432 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 1085156 # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave 864 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.apicbridge.master::total 864 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 8733312 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 159887 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio 996357 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 8733312 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::total 9889556 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 2243648 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::total 2243648 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::system.physmem.port 10976960 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::system.bridge.slave 159887 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::system.cpu0.interrupts.pio 996357 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::system.cpu0.interrupts.int_slave 864 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total 12134068 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 32713165 # Total data (bytes)
system.membus.snoop_data_through_bus 256448 # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy 793885999 # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy 164366000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer1.occupancy 164366000 # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy 314753000 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 314753000 # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy 432000 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer3.occupancy 432000 # Layer occupancy (ticks)
+system.membus.reqLayer3.occupancy 793885999 # Layer occupancy (ticks)
system.membus.reqLayer3.utilization 0.0 # Layer utilization (%)
system.membus.respLayer0.occupancy 216000 # Layer occupancy (ticks)
system.membus.respLayer0.utilization 0.0 # Layer utilization (%)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
system.membus.respLayer4.occupancy 175306750 # Layer occupancy (ticks)
system.membus.respLayer4.utilization 0.0 # Layer utilization (%)
-system.l2c.tags.replacements 104154 # number of replacements
-system.l2c.tags.tagsinuse 64818.882502 # Cycle average of tags in use
-system.l2c.tags.total_refs 3632248 # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs 168346 # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs 21.576087 # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks 51171.986670 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker 0.125486 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst 1262.785068 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data 4574.642727 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst 231.301246 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data 1356.639626 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.dtb.walker 11.163681 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.itb.walker 0.039070 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.inst 1464.364249 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.data 4745.834679 # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks 0.780823 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.itb.walker 0.000002 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst 0.019269 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data 0.069804 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst 0.003529 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data 0.020701 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000170 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.itb.walker 0.000001 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.inst 0.022344 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.data 0.072416 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total 0.989058 # Average percentage of cache occupancy
+system.l2c.tags.replacements 104154 # number of replacements
+system.l2c.tags.tagsinuse 64818.882502 # Cycle average of tags in use
+system.l2c.tags.total_refs 3632248 # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs 168346 # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs 21.576087 # Average number of references to valid blocks.
+system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.l2c.tags.occ_blocks::writebacks 51171.986670 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.itb.walker 0.125486 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst 1262.785068 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data 4574.642727 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst 231.301246 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data 1356.639626 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.dtb.walker 11.163681 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.itb.walker 0.039070 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.inst 1464.364249 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.data 4745.834679 # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks 0.780823 # Average percentage of cache occupancy
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+system.l2c.tags.occ_percent::cpu0.inst 0.019269 # Average percentage of cache occupancy
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+system.l2c.tags.occ_percent::cpu1.data 0.020701 # Average percentage of cache occupancy
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+system.l2c.tags.occ_percent::cpu2.data 0.072416 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total 0.989058 # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu0.dtb.walker 20178 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker 11162 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.inst 357762 # number of ReadReq hits
system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.iocache.tags.replacements 47579 # number of replacements
-system.iocache.tags.tagsinuse 0.100447 # Cycle average of tags in use
-system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs 47595 # Sample count of references to valid blocks.
-system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle 4999807573509 # Cycle when the warmup percentage was hit.
+system.iocache.tags.replacements 47579 # number of replacements
+system.iocache.tags.tagsinuse 0.100447 # Cycle average of tags in use
+system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
+system.iocache.tags.sampled_refs 47595 # Sample count of references to valid blocks.
+system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
+system.iocache.tags.warmup_cycle 4999807573509 # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.100447 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::pc.south_bridge.ide 0.006278 # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total 0.006278 # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total 0.006278 # Average percentage of cache occupancy
system.iocache.ReadReq_misses::pc.south_bridge.ide 914 # number of ReadReq misses
system.iocache.ReadReq_misses::total 914 # number of ReadReq misses
system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses
system.toL2Bus.trans_dist::UpgradeResp 745 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 173207 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 153920 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 966317 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 3599461 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.itb.walker.port 26176 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port 114965 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count 4706919 # Packet count per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 30921472 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 118979348 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.port 89784 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.port 413728 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size 150404332 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 966317 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3599461 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side 26176 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side 114965 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 4706919 # Packet count per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 30921472 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 118979348 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side 89784 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side 413728 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size::total 150404332 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.data_through_bus 267998065 # Total data (bytes)
system.toL2Bus.snoop_data_through_bus 148408 # Total snoop data (bytes)
system.toL2Bus.reqLayer0.occupancy 4987080585 # Layer occupancy (ticks)
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 38890 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 432 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 432 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.apicbridge.slave 432 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.pc.south_bridge.cmos.pio 36 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.pc.south_bridge.dma1.pio 2 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.pc.south_bridge.ide.pio 4266 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.pc.south_bridge.ide-pciconf 2 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.pc.south_bridge.keyboard.pio 12 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.pc.south_bridge.pic1.pio 30 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.pc.south_bridge.pic2.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.pc.south_bridge.pit.pio 18 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.pc.south_bridge.speaker.pio 290624 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.pc.south_bridge.io_apic.pio 38 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.pc.i_dont_exist.pio 86 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.pc.com_1.pio 15770 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.pc.fake_floppy.pio 4 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.iocache.cpu_side 38890 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.pc.pciconfig.pio 2048 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total 352274 # Packet count per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 18 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 1 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 1236136 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 864 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 864 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.apicbridge.slave 864 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.pc.south_bridge.cmos.pio 18 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.pc.south_bridge.dma1.pio 1 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.pc.south_bridge.ide.pio 2412 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.pc.south_bridge.ide-pciconf 4 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.pc.south_bridge.keyboard.pio 6 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.pc.south_bridge.pic1.pio 15 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.pc.south_bridge.pic2.pio 8 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.pc.south_bridge.pit.pio 9 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.pc.south_bridge.speaker.pio 145312 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.pc.south_bridge.io_apic.pio 76 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.pc.i_dont_exist.pio 43 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.pc.com_1.pio 7885 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.pc.fake_floppy.pio 2 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.iocache.cpu_side 1236136 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.pc.pciconfig.pio 4096 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::total 1396887 # Cumulative packet size per connected master and slave (bytes)
system.iobus.data_through_bus 6479664 # Total data (bytes)
system.iobus.reqLayer0.occupancy 492564 # Layer occupancy (ticks)
system.cpu0.num_mem_refs 14736464 # number of memory refs
system.cpu0.num_load_insts 10677140 # Number of load instructions
system.cpu0.num_store_insts 4059324 # Number of store instructions
-system.cpu0.num_idle_cycles 1078995887905.232788 # Number of idle cycles
-system.cpu0.num_busy_cycles -1077174534900.232788 # Number of busy cycles
-system.cpu0.not_idle_fraction -591.414477 # Percentage of non-idle cycles
-system.cpu0.idle_fraction 592.414477 # Percentage of idle cycles
+system.cpu0.num_idle_cycles 1727957342.597034 # Number of idle cycles
+system.cpu0.num_busy_cycles 93395662.402966 # Number of busy cycles
+system.cpu0.not_idle_fraction 0.051278 # Percentage of non-idle cycles
+system.cpu0.idle_fraction 0.948722 # Percentage of idle cycles
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed
-system.cpu0.icache.tags.replacements 847048 # number of replacements
-system.cpu0.icache.tags.tagsinuse 510.817647 # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs 129995405 # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs 847560 # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs 153.376050 # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle 147328649500 # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.replacements 847048 # number of replacements
+system.cpu0.icache.tags.tagsinuse 510.817647 # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs 129995405 # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs 847560 # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs 153.376050 # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle 147328649500 # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst 320.566465 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu1.inst 97.238420 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu2.inst 93.012763 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.626106 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu1.inst 0.189919 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu2.inst 0.181666 # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total 0.997691 # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total 0.997691 # Average percentage of cache occupancy
system.cpu0.icache.ReadReq_hits::cpu0.inst 89325030 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst 38126450 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu2.inst 2543925 # number of ReadReq hits
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12652.003554 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 12469.721021 # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.dcache.tags.replacements 1634474 # number of replacements
-system.cpu0.dcache.tags.tagsinuse 511.999389 # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs 19647501 # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs 1634986 # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs 12.016923 # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle 7549500 # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.tags.replacements 1634474 # number of replacements
+system.cpu0.dcache.tags.tagsinuse 511.999389 # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs 19647501 # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs 1634986 # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs 12.016923 # Average number of references to valid blocks.
+system.cpu0.dcache.tags.warmup_cycle 7549500 # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data 379.364018 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu1.data 126.391213 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu2.data 6.244158 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.740945 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu1.data 0.246858 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu2.data 0.012196 # Average percentage of cache occupancy
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system.cpu0.dcache.ReadReq_hits::cpu0.data 5614384 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data 2225977 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu2.data 3715968 # number of ReadReq hits
system.cpu1.num_mem_refs 4252332 # number of memory refs
system.cpu1.num_load_insts 2649427 # Number of load instructions
system.cpu1.num_store_insts 1602905 # Number of store instructions
-system.cpu1.num_idle_cycles 9584663693.774578 # Number of idle cycles
-system.cpu1.num_busy_cycles -6978657908.774579 # Number of busy cycles
-system.cpu1.not_idle_fraction -2.677913 # Percentage of non-idle cycles
-system.cpu1.idle_fraction 3.677913 # Percentage of idle cycles
+system.cpu1.num_idle_cycles 2479239642.942777 # Number of idle cycles
+system.cpu1.num_busy_cycles 126766142.057223 # Number of busy cycles
+system.cpu1.not_idle_fraction 0.048644 # Percentage of non-idle cycles
+system.cpu1.idle_fraction 0.951356 # Percentage of idle cycles
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
system.cpu2.branchPred.lookups 28549199 # Number of BP lookups
sim_ticks 26877484000 # Number of ticks simulated
final_tick 26877484000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 175198 # Simulator instruction rate (inst/s)
-host_op_rate 176456 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 51980195 # Simulator tick rate (ticks/s)
-host_mem_usage 379404 # Number of bytes of host memory used
-host_seconds 517.07 # Real time elapsed on the host
+host_inst_rate 190344 # Simulator instruction rate (inst/s)
+host_op_rate 191711 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 56473959 # Simulator tick rate (ticks/s)
+host_mem_usage 375760 # Number of bytes of host memory used
+host_seconds 475.93 # Real time elapsed on the host
sim_insts 90589798 # Number of instructions simulated
sim_ops 91240351 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 44928 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 1671585 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 35250919 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 36922504 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 15506 # Total number of read requests seen
-system.physmem.writeReqs 0 # Total number of write requests seen
-system.physmem.cpureqs 15508 # Reqs generatd by CPU via cache - shady
+system.physmem.readReqs 15506 # Total number of read requests accepted by DRAM controller
+system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller
+system.physmem.readBursts 15506 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
+system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
system.physmem.bytesRead 992384 # Total number of bytes read from memory
system.physmem.bytesWritten 0 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 992384 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
+system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q
system.physmem.neitherReadNorWrite 2 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 987 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 886 # Track reads on a per bank basis
system.membus.trans_dist::UpgradeResp 2 # Transaction distribution
system.membus.trans_dist::ReadExReq 14538 # Transaction distribution
system.membus.trans_dist::ReadExResp 14538 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side 31016 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count 31016 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 992384 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size 992384 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31016 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 31016 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 992384 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total 992384 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 992384 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.membus.reqLayer0.occupancy 19239000 # Layer occupancy (ticks)
system.cpu.toL2Bus.trans_dist::UpgradeResp 3 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 43736 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 43736 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1454 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 2838179 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count 2839633 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 46400 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 120994944 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size 121041344 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1454 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2838179 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 2839633 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 46400 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 120994944 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total 121041344 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus 121041344 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 192 # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy 1888558000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 1424224742 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 5.3 # Layer utilization (%)
-system.cpu.icache.tags.replacements 3 # number of replacements
-system.cpu.icache.tags.tagsinuse 627.810421 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 13838909 # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs 725 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 19088.150345 # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 627.810421 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.306548 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.306548 # Average percentage of cache occupancy
+system.cpu.icache.tags.replacements 3 # number of replacements
+system.cpu.icache.tags.tagsinuse 627.810421 # Cycle average of tags in use
+system.cpu.icache.tags.total_refs 13838909 # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs 725 # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs 19088.150345 # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst 627.810421 # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst 0.306548 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total 0.306548 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 13838909 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 13838909 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 13838909 # number of demand (read+write) hits
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67477.023320 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 67477.023320 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements 0 # number of replacements
-system.cpu.l2cache.tags.tagsinuse 10729.444424 # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs 1831414 # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs 15489 # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs 118.239654 # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.replacements 0 # number of replacements
+system.cpu.l2cache.tags.tagsinuse 10729.444424 # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs 1831414 # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs 15489 # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs 118.239654 # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 9885.972786 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 614.181359 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 229.290279 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 614.181359 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 229.290279 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.301696 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.018743 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.006997 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total 0.327437 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total 0.327437 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 23 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 903615 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 903638 # number of ReadReq hits
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49322.598622 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49627.305559 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements 943531 # number of replacements
-system.cpu.dcache.tags.tagsinuse 3671.859513 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 28137843 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 947627 # Sample count of references to valid blocks.
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system.membus.trans_dist::ReadExResp 14567 # Transaction distribution
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system.cpu.toL2Bus.trans_dist::ReadExResp 46714 # Transaction distribution
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system.cpu.toL2Bus.data_through_bus 120046016 # Total data (bytes)
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system.physmem.bw_total::cpu.data 28739572 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 29870043 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bytesRead 1946112 # Total number of bytes read from memory
system.physmem.bytesWritten 10432 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 1946112 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 10432 # bytesWritten derated as per pkt->getSize()
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system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 1921 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 2071 # Track reads on a per bank basis
system.membus.trans_dist::ReadExResp 29004 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 60980 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 60980 # Packet count per connected master and slave (bytes)
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system.membus.pkt_count::total 60980 # Packet count per connected master and slave (bytes)
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system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 1956480 # Cumulative packet size per connected master and slave (bytes)
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system.membus.tot_pkt_size::total 1956480 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 1956480 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.toL2Bus.trans_dist::Writeback 2066630 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 82305 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 82305 # Transaction distribution
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system.cpu.toL2Bus.data_through_bus 265229120 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy 4138734000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 3122065000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 4.8 # Layer utilization (%)
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system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67807.425743 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 67807.425743 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.l2cache.tags.occ_blocks::writebacks 19907.577759 # Average occupied blocks per requestor
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system.cpu.l2cache.ReadReq_hits::total 1993867 # number of ReadReq hits
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49000.373946 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49201.118053 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.ReadReq_hits::cpu.data 40036076 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 40036076 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 31341699 # number of WriteReq hits
sim_ticks 365989065000 # Number of ticks simulated
final_tick 365989065000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 157988548 # Number of instructions simulated
sim_ops 278192465 # Number of ops (including micro ops) simulated
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system.membus.trans_dist::ReadExResp 29024 # Transaction distribution
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system.membus.pkt_count::total 60198 # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1929536 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 1929536 # Cumulative packet size per connected master and slave (bytes)
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system.membus.tot_pkt_size::total 1929536 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 1929536 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.num_busy_cycles 731978130 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
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system.cpu.icache.demand_hits::cpu.inst 217695357 # number of demand (read+write) hits
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52740.099010 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 52740.099010 # average overall mshr miss latency
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system.cpu.toL2Bus.trans_dist::ReadExResp 106109 # Transaction distribution
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system.cpu.toL2Bus.data_through_bus 264327744 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy 4127544500 # Layer occupancy (ticks)
sim_ticks 202349747500 # Number of ticks simulated
final_tick 202349747500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 505237723 # Number of instructions simulated
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system.physmem.bytes_read::cpu.inst 216896 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 1071887 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 45802993 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 77765395 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bytesRead 9485120 # Total number of bytes read from memory
system.physmem.bytesWritten 6250688 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 9485120 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 6250688 # bytesWritten derated as per pkt->getSize()
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system.physmem.neitherReadNorWrite 7 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 9580 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 9220 # Track reads on a per bank basis
system.membus.trans_dist::UpgradeResp 7 # Transaction distribution
system.membus.trans_dist::ReadExReq 101306 # Transaction distribution
system.membus.trans_dist::ReadExResp 101306 # Transaction distribution
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-system.membus.tot_pkt_size 15735808 # Cumulative packet size per connected master and slave (bytes)
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+system.membus.pkt_count::total 394092 # Packet count per connected master and slave (bytes)
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+system.membus.tot_pkt_size::total 15735808 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 15735808 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.membus.reqLayer0.occupancy 1084180500 # Layer occupancy (ticks)
system.cpu.toL2Bus.trans_dist::UpgradeResp 69 # Transaction distribution
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system.cpu.toL2Bus.data_through_bus 148783104 # Total data (bytes)
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system.cpu.toL2Bus.reqLayer0.occupancy 2273504243 # Layer occupancy (ticks)
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system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%)
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system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 25103.227023 # average overall mshr miss latency
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.WriteReq_hits::cpu.data 50989456 # number of WriteReq hits
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final_tick 717366012000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
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system.membus.trans_dist::ReadExResp 100794 # Transaction distribution
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system.membus.data_through_bus 15270528 # Total data (bytes)
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system.cpu.toL2Bus.trans_dist::ReadExResp 356260 # Transaction distribution
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system.cpu.toL2Bus.data_through_bus 141782016 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy 2172577000 # Layer occupancy (ticks)
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final_tick 458201684000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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system.physmem.bw_total::cpu.data 53417735 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 94862960 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bytesRead 24677504 # Total number of bytes read from memory
system.physmem.bytesWritten 18788864 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 24677504 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 18788864 # bytesWritten derated as per pkt->getSize()
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system.physmem.neitherReadNorWrite 131239 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 24063 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 26436 # Track reads on a per bank basis
system.membus.trans_dist::ReadExResp 206848 # Transaction distribution
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system.membus.pkt_count::total 1327226 # Packet count per connected master and slave (bytes)
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system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 43466368 # Cumulative packet size per connected master and slave (bytes)
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system.membus.tot_pkt_size::total 43466368 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 43466368 # Total data (bytes)
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system.cpu.toL2Bus.data_through_bus 311784960 # Total data (bytes)
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system.cpu.toL2Bus.reqLayer0.occupancy 4903151186 # Layer occupancy (ticks)
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system.cpu.toL2Bus.respLayer1.occupancy 3959772656 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%)
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.ReadReq_hits::cpu.data 247340077 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 247340077 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 148239061 # number of WriteReq hits
sim_ticks 1647872849000 # Number of ticks simulated
final_tick 1647872849000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 826877110 # Number of instructions simulated
sim_ops 1528988702 # Number of ops (including micro ops) simulated
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system.membus.trans_dist::ReadExResp 206691 # Transaction distribution
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system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1054572 # Packet count per connected master and slave (bytes)
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system.membus.pkt_count::total 1054572 # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43099456 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 43099456 # Cumulative packet size per connected master and slave (bytes)
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system.membus.tot_pkt_size::total 43099456 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 43099456 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
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system.cpu.idle_fraction 0 # Percentage of idle cycles
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system.cpu.icache.overall_avg_mshr_miss_latency::total 39153.518124 # average overall mshr miss latency
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system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.324318 # average overall mshr miss latency
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system.cpu.dcache.ReadReq_hits::total 382374772 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 148369158 # number of WriteReq hits
system.cpu.toL2Bus.trans_dist::Writeback 2323523 # Transaction distribution
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system.cpu.toL2Bus.trans_dist::ReadExResp 791044 # Transaction distribution
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system.cpu.toL2Bus.data_through_bus 310066880 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy 4745920500 # Layer occupancy (ticks)
sim_ticks 139916242500 # Number of ticks simulated
final_tick 139916242500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
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+host_op_rate 80792 # Simulator op (including micro ops) rate (op/s)
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sim_insts 398664595 # Number of instructions simulated
sim_ops 398664595 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 214976 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 1536462 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 1815486 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 3351948 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bytesRead 468992 # Total number of bytes read from memory
system.physmem.bytesWritten 0 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 468992 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
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system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 507 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 643 # Track reads on a per bank basis
system.membus.trans_dist::ReadResp 4183 # Transaction distribution
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system.membus.trans_dist::ReadExResp 3145 # Transaction distribution
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system.membus.data_through_bus 468992 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.membus.reqLayer0.occupancy 8796500 # Layer occupancy (ticks)
system.cpu.stage4.idleCycles 90364523 # Number of cycles 0 instructions are processed.
system.cpu.stage4.runCycles 189467963 # Number of cycles 1+ instructions are processed.
system.cpu.stage4.utilization 67.707637 # Percentage of cycles stage was utilized (processing insts).
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system.cpu.icache.ReadReq_hits::cpu.inst 48606795 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 48606795 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 48606795 # number of demand (read+write) hits
system.cpu.toL2Bus.trans_dist::Writeback 649 # Transaction distribution
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system.cpu.toL2Bus.trans_dist::ReadExResp 3205 # Transaction distribution
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system.cpu.toL2Bus.data_through_bus 557056 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy 5001000 # Layer occupancy (ticks)
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system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
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system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 56623.015873 # average overall mshr miss latency
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final_tick 77521581000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_insts 375574808 # Number of instructions simulated
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system.physmem.bw_total::cpu.data 3293225 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 6143941 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bytesRead 476288 # Total number of bytes read from memory
system.physmem.bytesWritten 0 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 476288 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
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system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 527 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 653 # Track reads on a per bank basis
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system.membus.trans_dist::ReadExResp 3132 # Transaction distribution
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system.membus.data_through_bus 476288 # Total data (bytes)
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system.membus.reqLayer0.occupancy 9304000 # Layer occupancy (ticks)
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system.cpu.toL2Bus.trans_dist::ReadExResp 3200 # Transaction distribution
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final_tick 567335093000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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+host_op_rate 1598767 # Simulator op (including micro ops) rate (op/s)
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sim_insts 398664609 # Number of instructions simulated
sim_ops 398664609 # Number of ops (including micro ops) simulated
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system.membus.trans_dist::ReadResp 4032 # Transaction distribution
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system.membus.trans_dist::ReadExResp 3142 # Transaction distribution
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-system.membus.tot_pkt_size 459136 # Cumulative packet size per connected master and slave (bytes)
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system.membus.data_through_bus 459136 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.membus.reqLayer0.occupancy 7174000 # Layer occupancy (ticks)
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system.cpu.idle_fraction 0 # Percentage of idle cycles
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+system.cpu.l2cache.tags.occ_blocks::cpu.inst 2770.469924 # Average occupied blocks per requestor
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system.cpu.l2cache.ReadReq_hits::cpu.inst 468 # number of ReadReq hits
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system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.ReadReq_hits::cpu.data 94753540 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 94753540 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 73517528 # number of WriteReq hits
system.cpu.toL2Bus.trans_dist::Writeback 649 # Transaction distribution
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system.cpu.toL2Bus.trans_dist::ReadExResp 3202 # Transaction distribution
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system.cpu.toL2Bus.data_through_bus 542336 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy 4886000 # Layer occupancy (ticks)
sim_ticks 68375005500 # Number of ticks simulated
final_tick 68375005500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 273036725 # Number of instructions simulated
sim_ops 349064449 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 194176 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 2839868 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 3981806 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 6821674 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bytesRead 466432 # Total number of bytes read from memory
system.physmem.bytesWritten 0 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 466432 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
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system.physmem.neitherReadNorWrite 5 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 605 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 802 # Track reads on a per bank basis
system.membus.trans_dist::UpgradeResp 5 # Transaction distribution
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system.membus.trans_dist::ReadExResp 2821 # Transaction distribution
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system.membus.data_through_bus 466432 # Total data (bytes)
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system.membus.reqLayer0.occupancy 8910500 # Layer occupancy (ticks)
system.cpu.toL2Bus.trans_dist::UpgradeResp 5 # Transaction distribution
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system.cpu.toL2Bus.trans_dist::ReadExResp 2838 # Transaction distribution
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system.cpu.toL2Bus.data_through_bus 1374656 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 384 # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy 11782000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 7509966 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
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system.cpu.l2cache.tags.occ_blocks::writebacks 375.051576 # Average occupied blocks per requestor
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system.cpu.l2cache.ReadReq_hits::cpu.data 298 # number of ReadReq hits
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system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 55178.479079 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55080.920692 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.ReadReq_hits::total 88809743 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 82031242 # number of WriteReq hits
sim_ticks 525834342000 # Number of ticks simulated
final_tick 525834342000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 272739283 # Number of instructions simulated
sim_ops 348687122 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 166976 # Number of bytes read from this memory
system.membus.trans_dist::ReadResp 3976 # Transaction distribution
system.membus.trans_dist::ReadExReq 2856 # Transaction distribution
system.membus.trans_dist::ReadExResp 2856 # Transaction distribution
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-system.membus.tot_pkt_size 437248 # Cumulative packet size per connected master and slave (bytes)
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system.membus.data_through_bus 437248 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.membus.reqLayer0.occupancy 6832000 # Layer occupancy (ticks)
system.cpu.num_busy_cycles 1051668684 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
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system.cpu.icache.demand_hits::cpu.inst 348644747 # number of demand (read+write) hits
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18022.880215 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 18022.880215 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
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+system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.ReadReq_hits::cpu.data 94570004 # number of ReadReq hits
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system.cpu.dcache.WriteReq_hits::cpu.data 82049805 # number of WriteReq hits
system.cpu.toL2Bus.trans_dist::Writeback 998 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 2872 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 2872 # Transaction distribution
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system.cpu.toL2Bus.data_through_bus 1349056 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy 11537500 # Layer occupancy (ticks)
sim_ticks 631883288500 # Number of ticks simulated
final_tick 631883288500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
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-host_op_rate 129491 # Simulator op (including micro ops) rate (op/s)
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+host_op_rate 177291 # Simulator op (including micro ops) rate (op/s)
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sim_insts 1823043370 # Number of instructions simulated
sim_ops 1823043370 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 176064 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 278634 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 47944246 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 54999625 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 476114 # Total number of read requests seen
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-system.physmem.cpureqs 543022 # Reqs generatd by CPU via cache - shady
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system.physmem.bytesRead 30471232 # Total number of bytes read from memory
system.physmem.bytesWritten 4282112 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 30471232 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 4282112 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 90 # Number of read reqs serviced by write Q
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system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 29447 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 29799 # Track reads on a per bank basis
system.membus.trans_dist::Writeback 66908 # Transaction distribution
system.membus.trans_dist::ReadExReq 66856 # Transaction distribution
system.membus.trans_dist::ReadExResp 66856 # Transaction distribution
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system.membus.data_through_bus 34753344 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.membus.reqLayer0.occupancy 1232718500 # Layer occupancy (ticks)
system.cpu.toL2Bus.trans_dist::Writeback 95986 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 71645 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 71645 # Transaction distribution
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system.cpu.toL2Bus.data_through_bus 104827200 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy 914949000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 2398320750 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%)
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system.cpu.icache.ReadReq_hits::cpu.inst 394735107 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 394735107 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 394735107 # number of demand (read+write) hits
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 27883.100946 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 27883.100946 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.l2cache.tags.occ_blocks::writebacks 1328.456107 # Average occupied blocks per requestor
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system.cpu.l2cache.ReadReq_hits::total 1061037 # number of ReadReq hits
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60811.242242 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60800.628631 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.ReadReq_hits::cpu.data 458073360 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 458073360 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 209733012 # number of WriteReq hits
sim_ticks 2769739533000 # Number of ticks simulated
final_tick 2769739533000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 2008987605 # Number of instructions simulated
sim_ops 2008987605 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 137792 # Number of bytes read from this memory
system.membus.trans_dist::Writeback 66908 # Transaction distribution
system.membus.trans_dist::ReadExReq 66873 # Transaction distribution
system.membus.trans_dist::ReadExResp 66873 # Transaction distribution
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system.membus.data_through_bus 34704448 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.membus.reqLayer0.occupancy 1077521000 # Layer occupancy (ticks)
system.cpu.num_busy_cycles 5539479066 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
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system.cpu.icache.demand_hits::cpu.inst 2009410475 # number of demand (read+write) hits
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19533.975085 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 19533.975085 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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+system.cpu.l2cache.tags.occ_blocks::cpu.inst 26.518402 # Average occupied blocks per requestor
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+system.cpu.toL2Bus.pkt_count::total 3177609 # Packet count per connected master and slave (bytes)
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system.cpu.toL2Bus.data_through_bus 104759616 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy 914563500 # Layer occupancy (ticks)
sim_ticks 640648369500 # Number of ticks simulated
final_tick 640648369500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 1384370590 # Number of instructions simulated
sim_ops 1885325342 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 155648 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 242954 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 47208174 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 54054239 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bytesRead 30399488 # Total number of bytes read from memory
system.physmem.bytesWritten 4230272 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 30399488 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 4230272 # bytesWritten derated as per pkt->getSize()
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system.physmem.neitherReadNorWrite 4361 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 29873 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 29675 # Track reads on a per bank basis
system.membus.trans_dist::UpgradeResp 4361 # Transaction distribution
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system.membus.trans_dist::ReadExResp 66075 # Transaction distribution
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system.membus.data_through_bus 34629696 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.membus.reqLayer0.occupancy 1215067500 # Layer occupancy (ticks)
system.cpu.toL2Bus.trans_dist::UpgradeResp 4364 # Transaction distribution
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system.cpu.toL2Bus.trans_dist::ReadExResp 72519 # Transaction distribution
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system.cpu.toL2Bus.data_through_bus 106061888 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 279232 # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy 929276999 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 2407943085 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%)
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system.cpu.icache.demand_hits::cpu.inst 345973619 # number of demand (read+write) hits
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14882.555031 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 14882.555031 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.l2cache.tags.occ_blocks::writebacks 1291.826262 # Average occupied blocks per requestor
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system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62076.363848 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62059.509423 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.ReadReq_hits::cpu.data 696790485 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 696790485 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 276093216 # number of WriteReq hits
sim_ticks 2326118592000 # Number of ticks simulated
final_tick 2326118592000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 1381604339 # Number of instructions simulated
sim_ops 1874244941 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 113472 # Number of bytes read from this memory
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system.membus.trans_dist::ReadExReq 66093 # Transaction distribution
system.membus.trans_dist::ReadExResp 66093 # Transaction distribution
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-system.membus.tot_pkt_size 34576320 # Cumulative packet size per connected master and slave (bytes)
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system.membus.data_through_bus 34576320 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.membus.reqLayer0.occupancy 1069047000 # Layer occupancy (ticks)
system.cpu.num_busy_cycles 4652237184 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
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system.cpu.icache.demand_hits::cpu.inst 1390251699 # number of demand (read+write) hits
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system.cpu.icache.overall_avg_mshr_miss_latency::total 14760.642327 # average overall mshr miss latency
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+system.cpu.toL2Bus.pkt_count::total 3203169 # Packet count per connected master and slave (bytes)
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+system.cpu.toL2Bus.tot_pkt_size::total 105581632 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus 105581632 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy 921113500 # Layer occupancy (ticks)
sim_ticks 43769191000 # Number of ticks simulated
final_tick 43769191000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
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-host_op_rate 112888 # Simulator op (including micro ops) rate (op/s)
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+host_inst_rate 69144 # Simulator instruction rate (inst/s)
+host_op_rate 69144 # Simulator op (including micro ops) rate (op/s)
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+host_seconds 1277.63 # Real time elapsed on the host
sim_insts 88340673 # Number of instructions simulated
sim_ops 88340673 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 454592 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 10386118 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 231632520 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 408706846 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 165515 # Total number of read requests seen
-system.physmem.writeReqs 113997 # Total number of write requests seen
-system.physmem.cpureqs 279512 # Reqs generatd by CPU via cache - shady
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system.physmem.bytesRead 10592960 # Total number of bytes read from memory
system.physmem.bytesWritten 7295808 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 10592960 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 7295808 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
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system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 10379 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 10437 # Track reads on a per bank basis
system.membus.trans_dist::Writeback 113997 # Transaction distribution
system.membus.trans_dist::ReadExReq 130890 # Transaction distribution
system.membus.trans_dist::ReadExResp 130890 # Transaction distribution
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system.membus.data_through_bus 17888768 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.membus.reqLayer0.occupancy 1218896000 # Layer occupancy (ticks)
system.cpu.stage4.idleCycles 41496378 # Number of cycles 0 instructions are processed.
system.cpu.stage4.runCycles 46042005 # Number of cycles 1+ instructions are processed.
system.cpu.stage4.utilization 52.596362 # Percentage of cycles stage was utilized (processing insts).
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system.cpu.icache.ReadReq_hits::cpu.inst 12250515 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 12250515 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 12250515 # number of demand (read+write) hits
system.cpu.toL2Bus.trans_dist::Writeback 168352 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 143769 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 143769 # Transaction distribution
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system.cpu.toL2Bus.data_through_bus 29383424 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy 397910000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.3 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 326782984 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%)
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system.cpu.l2cache.tags.occ_blocks::writebacks 27124.475533 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 2007.439767 # Average occupied blocks per requestor
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system.cpu.l2cache.tags.occ_percent::writebacks 0.827773 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.061262 # Average percentage of cache occupancy
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system.cpu.l2cache.ReadReq_hits::cpu.inst 79314 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 33056 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 112370 # number of ReadReq hits
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 87183.204240 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 86404.621938 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements 200251 # number of replacements
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-system.cpu.dcache.tags.warmup_cycle 293009000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 4076.642006 # Average occupied blocks per requestor
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system.cpu.dcache.ReadReq_hits::cpu.data 20180271 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 20180271 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 13574569 # number of WriteReq hits
sim_ticks 24977022500 # Number of ticks simulated
final_tick 24977022500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
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-host_op_rate 130696 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 41014411 # Simulator tick rate (ticks/s)
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-host_seconds 608.98 # Real time elapsed on the host
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sim_insts 79591756 # Number of instructions simulated
sim_ops 79591756 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 489984 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 19617390 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 406515068 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 718281933 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 166305 # Total number of read requests seen
-system.physmem.writeReqs 114016 # Total number of write requests seen
-system.physmem.cpureqs 280321 # Reqs generatd by CPU via cache - shady
+system.physmem.readReqs 166305 # Total number of read requests accepted by DRAM controller
+system.physmem.writeReqs 114016 # Total number of write requests accepted by DRAM controller
+system.physmem.readBursts 166305 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
+system.physmem.writeBursts 114016 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
system.physmem.bytesRead 10643520 # Total number of bytes read from memory
system.physmem.bytesWritten 7297024 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 10643520 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 7297024 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 3 # Number of read reqs serviced by write Q
+system.physmem.servicedByWrQ 3 # Number of DRAM read bursts serviced by write Q
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 10424 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 10464 # Track reads on a per bank basis
system.membus.trans_dist::Writeback 114016 # Transaction distribution
system.membus.trans_dist::ReadExReq 130797 # Transaction distribution
system.membus.trans_dist::ReadExResp 130797 # Transaction distribution
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-system.membus.pkt_count 446626 # Packet count per connected master and slave (bytes)
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-system.membus.tot_pkt_size 17940544 # Cumulative packet size per connected master and slave (bytes)
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+system.membus.pkt_count::total 446626 # Packet count per connected master and slave (bytes)
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system.membus.data_through_bus 17940544 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.membus.reqLayer0.occupancy 1244155000 # Layer occupancy (ticks)
system.cpu.toL2Bus.trans_dist::Writeback 168929 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 143410 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 143410 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 186551 # Packet count per connected master and slave (bytes)
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-system.cpu.toL2Bus.pkt_count 766612 # Packet count per connected master and slave (bytes)
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-system.cpu.toL2Bus.tot_pkt_size 29937280 # Cumulative packet size per connected master and slave (bytes)
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+system.cpu.toL2Bus.tot_pkt_size::total 29937280 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus 29937280 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy 402814500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.6 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 327076000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%)
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+system.cpu.icache.tags.warmup_cycle 20172265250 # Cycle when the warmup percentage was hit.
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system.cpu.icache.ReadReq_hits::cpu.inst 13799737 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 13799737 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 13799737 # number of demand (read+write) hits
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17000.812278 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 17000.812278 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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-system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.replacements 132400 # number of replacements
+system.cpu.l2cache.tags.tagsinuse 30717.176709 # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs 159637 # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs 164461 # Sample count of references to valid blocks.
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+system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 26388.752281 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 2106.212865 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 2222.211563 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 2106.212865 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 2222.211563 # Average occupied blocks per requestor
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system.cpu.l2cache.tags.occ_percent::cpu.inst 0.064277 # Average percentage of cache occupancy
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system.cpu.l2cache.ReadReq_hits::total 119923 # number of ReadReq hits
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 89605.561649 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 88716.653338 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements 201470 # number of replacements
-system.cpu.dcache.tags.tagsinuse 4074.474898 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 34190075 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 205566 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 166.321644 # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle 215349000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 4074.474898 # Average occupied blocks per requestor
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-system.cpu.dcache.tags.occ_percent::total 0.994745 # Average percentage of cache occupancy
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+system.cpu.dcache.tags.tagsinuse 4074.474898 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 34190075 # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs 205566 # Sample count of references to valid blocks.
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+system.cpu.dcache.tags.warmup_cycle 215349000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data 4074.474898 # Average occupied blocks per requestor
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system.cpu.dcache.ReadReq_hits::cpu.data 20615905 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 20615905 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 13574108 # number of WriteReq hits
sim_ticks 133634727000 # Number of ticks simulated
final_tick 133634727000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 671194 # Simulator instruction rate (inst/s)
-host_op_rate 671194 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1015328507 # Simulator tick rate (ticks/s)
-host_mem_usage 233108 # Number of bytes of host memory used
-host_seconds 131.62 # Real time elapsed on the host
+host_inst_rate 775893 # Simulator instruction rate (inst/s)
+host_op_rate 775893 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1173708198 # Simulator tick rate (ticks/s)
+host_mem_usage 233104 # Number of bytes of host memory used
+host_seconds 113.86 # Real time elapsed on the host
sim_insts 88340673 # Number of instructions simulated
sim_ops 88340673 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 432896 # Number of bytes read from this memory
system.membus.trans_dist::Writeback 113982 # Transaction distribution
system.membus.trans_dist::ReadExReq 130881 # Transaction distribution
system.membus.trans_dist::ReadExResp 130881 # Transaction distribution
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system.membus.data_through_bus 17864640 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.membus.reqLayer0.occupancy 1190991000 # Layer occupancy (ticks)
system.cpu.num_busy_cycles 267269454 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
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system.cpu.icache.ReadReq_hits::cpu.inst 88361638 # number of ReadReq hits
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system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14721.335496 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 14721.335496 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.l2cache.tags.occ_blocks::writebacks 27298.448351 # Average occupied blocks per requestor
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system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.WriteReq_hits::cpu.data 14469799 # number of WriteReq hits
system.cpu.toL2Bus.trans_dist::Writeback 168375 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 143578 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 143578 # Transaction distribution
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system.cpu.toL2Bus.data_through_bus 28745920 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy 392952500 # Layer occupancy (ticks)
sim_ticks 26765004500 # Number of ticks simulated
final_tick 26765004500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 70907629 # Number of instructions simulated
sim_ops 100626876 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 297792 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 11126170 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 296831783 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 508673780 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 128790 # Total number of read requests seen
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-system.physmem.cpureqs 213051 # Reqs generatd by CPU via cache - shady
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+system.physmem.readBursts 128790 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
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system.physmem.bytesRead 8242496 # Total number of bytes read from memory
system.physmem.bytesWritten 5372160 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 8242496 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 5372160 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 3 # Number of read reqs serviced by write Q
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system.physmem.neitherReadNorWrite 321 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 8146 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 8397 # Track reads on a per bank basis
system.membus.trans_dist::UpgradeResp 321 # Transaction distribution
system.membus.trans_dist::ReadExReq 102252 # Transaction distribution
system.membus.trans_dist::ReadExResp 102252 # Transaction distribution
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system.membus.data_through_bus 13614656 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.membus.reqLayer0.occupancy 935941500 # Layer occupancy (ticks)
system.cpu.toL2Bus.trans_dist::UpgradeResp 336 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 107033 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 107033 # Transaction distribution
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system.cpu.toL2Bus.data_through_bus 20627776 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 32000 # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy 290686995 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 262412261 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%)
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system.cpu.icache.ReadReq_hits::cpu.inst 11651673 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 11651673 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 11651673 # number of demand (read+write) hits
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21904.401543 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 21904.401543 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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+system.cpu.l2cache.tags.tagsinuse 29916.504006 # Cycle average of tags in use
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system.cpu.l2cache.tags.occ_blocks::writebacks 26705.369214 # Average occupied blocks per requestor
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+system.cpu.l2cache.tags.occ_blocks::cpu.inst 1366.053749 # Average occupied blocks per requestor
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system.cpu.l2cache.tags.occ_percent::writebacks 0.814983 # Average percentage of cache occupancy
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system.cpu.l2cache.ReadReq_hits::total 59554 # number of ReadReq hits
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69986.508974 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70033.975596 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
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-system.cpu.dcache.tags.warmup_cycle 354003250 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 4069.400137 # Average occupied blocks per requestor
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+system.cpu.dcache.tags.tagsinuse 4069.400137 # Cycle average of tags in use
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+system.cpu.dcache.tags.warmup_cycle 354003250 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data 4069.400137 # Average occupied blocks per requestor
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system.cpu.dcache.ReadReq_hits::cpu.data 26075013 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 26075013 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 18266800 # number of WriteReq hits
sim_ticks 132689045000 # Number of ticks simulated
final_tick 132689045000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
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-host_tick_rate 825892843 # Simulator tick rate (ticks/s)
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-host_seconds 160.66 # Real time elapsed on the host
+host_inst_rate 525201 # Simulator instruction rate (inst/s)
+host_op_rate 744748 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 990262559 # Simulator tick rate (ticks/s)
+host_mem_usage 247408 # Number of bytes of host memory used
+host_seconds 133.99 # Real time elapsed on the host
sim_insts 70373628 # Number of instructions simulated
sim_ops 99791654 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 255488 # Number of bytes read from this memory
system.membus.trans_dist::Writeback 83909 # Transaction distribution
system.membus.trans_dist::ReadExReq 102280 # Transaction distribution
system.membus.trans_dist::ReadExResp 102280 # Transaction distribution
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-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 13550144 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size 13550144 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 339533 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 339533 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13550144 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total 13550144 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 13550144 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.membus.reqLayer0.occupancy 882993000 # Layer occupancy (ticks)
system.cpu.num_busy_cycles 265378090 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.icache.tags.replacements 16890 # number of replacements
-system.cpu.icache.tags.tagsinuse 1736.497265 # Cycle average of tags in use
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system.cpu.l2cache.tags.occ_blocks::writebacks 27745.868937 # Average occupied blocks per requestor
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system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40053.908900 # average overall mshr miss latency
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system.cpu.dcache.ReadReq_hits::total 27087367 # number of ReadReq hits
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system.cpu.toL2Bus.data_through_bus 19657280 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy 281811500 # Layer occupancy (ticks)
sim_ticks 202242260000 # Number of ticks simulated
final_tick 202242260000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
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-system.membus.tot_pkt_size 13721664 # Cumulative packet size per connected master and slave (bytes)
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system.membus.data_through_bus 13721664 # Total data (bytes)
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system.cpu.idle_fraction 0 # Percentage of idle cycles
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system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.toL2Bus.trans_dist::Writeback 123970 # Transaction distribution
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system.cpu.toL2Bus.trans_dist::ReadExResp 105179 # Transaction distribution
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-system.cpu.toL2Bus.tot_pkt_size 29547008 # Cumulative packet size per connected master and slave (bytes)
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+system.cpu.toL2Bus.tot_pkt_size::total 29547008 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus 29547008 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy 354806000 # Layer occupancy (ticks)
sim_ticks 1017016979500 # Number of ticks simulated
final_tick 1017016979500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
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+host_op_rate 89946 # Simulator op (including micro ops) rate (op/s)
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sim_insts 1819780127 # Number of instructions simulated
sim_ops 1819780127 # Number of ops (including micro ops) simulated
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system.physmem.bw_total::cpu.data 123267606 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 187387172 # Total bandwidth to/from this memory (bytes/s)
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-system.physmem.cpureqs 2977749 # Reqs generatd by CPU via cache - shady
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system.physmem.bytesRead 125420224 # Total number of bytes read from memory
system.physmem.bytesWritten 65155712 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 125420224 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 65155712 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 576 # Number of read reqs serviced by write Q
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system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 118716 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 114074 # Track reads on a per bank basis
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system.membus.trans_dist::ReadExResp 781298 # Transaction distribution
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-system.membus.tot_pkt_size 190575936 # Cumulative packet size per connected master and slave (bytes)
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+system.membus.pkt_count::total 4937440 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190575936 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total 190575936 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 190575936 # Total data (bytes)
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system.membus.reqLayer0.occupancy 11803876500 # Layer occupancy (ticks)
system.cpu.stage4.idleCycles 1012697898 # Number of cycles 0 instructions are processed.
system.cpu.stage4.runCycles 1021336062 # Number of cycles 1+ instructions are processed.
system.cpu.stage4.utilization 50.212341 # Percentage of cycles stage was utilized (processing insts).
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system.cpu.icache.ReadReq_hits::cpu.inst 231946364 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 231946364 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 231946364 # number of demand (read+write) hits
system.cpu.toL2Bus.trans_dist::Writeback 3693279 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 1889621 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 1889621 # Transaction distribution
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system.cpu.toL2Bus.data_through_bus 819557696 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy 10096073500 # Layer occupancy (ticks)
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system.cpu.toL2Bus.respLayer1.occupancy 14100129000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%)
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system.cpu.l2cache.ReadReq_hits::total 6044296 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 3693279 # number of Writeback hits
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system.physmem.bw_total::cpu.data 181209495 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 275311755 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bytesRead 125852032 # Total number of bytes read from memory
system.physmem.bytesWritten 65261440 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 125852032 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 65261440 # bytesWritten derated as per pkt->getSize()
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system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 119011 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 114417 # Track reads on a per bank basis
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system.membus.data_through_bus 191113472 # Total data (bytes)
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system.membus.reqLayer0.occupancy 11881655250 # Layer occupancy (ticks)
system.cpu.toL2Bus.trans_dist::Writeback 3725037 # Transaction distribution
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system.cpu.toL2Bus.reqLayer0.occupancy 10178230165 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
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system.cpu.toL2Bus.respLayer1.utilization 2.0 # Layer utilization (%)
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final_tick 2623386226000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_insts 1819780127 # Number of instructions simulated
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system.membus.trans_dist::ReadExReq 781301 # Transaction distribution
system.membus.trans_dist::ReadExResp 781301 # Transaction distribution
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system.membus.data_through_bus 190575360 # Total data (bytes)
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system.cpu.idle_fraction 0 # Percentage of idle cycles
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system.physmem.bytesRead 143773696 # Total number of bytes read from memory
system.physmem.bytesWritten 70430528 # Total number of bytes written to memory
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system.physmem.bytesConsumedWr 70430528 # bytesWritten derated as per pkt->getSize()
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system.cpu.l2cache.overall_avg_mshr_miss_latency::total 86536.159716 # average overall mshr miss latency
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sim_insts 1538759601 # Number of instructions simulated
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system.membus.trans_dist::ReadExResp 780876 # Transaction distribution
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system.membus.data_through_bus 190462208 # Total data (bytes)
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system.cpu.idle_fraction 0 # Percentage of idle cycles
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system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.ReadReq_hits::total 475158039 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 170696898 # number of WriteReq hits
system.cpu.toL2Bus.trans_dist::Writeback 3697418 # Transaction distribution
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system.cpu.toL2Bus.trans_dist::ReadExResp 1889149 # Transaction distribution
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system.cpu.toL2Bus.data_through_bus 820050688 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy 10104064000 # Layer occupancy (ticks)
sim_ticks 5882580526000 # Number of ticks simulated
final_tick 5882580526000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 3008081022 # Number of instructions simulated
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system.physmem.bytes_read::cpu.inst 43200 # Number of bytes read from this memory
system.membus.trans_dist::ReadExResp 781295 # Transaction distribution
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system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4936239 # Packet count per connected master and slave (bytes)
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system.membus.pkt_count::total 4936239 # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190549120 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 190549120 # Cumulative packet size per connected master and slave (bytes)
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system.membus.tot_pkt_size::total 190549120 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 190549120 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.num_busy_cycles 11765161052 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
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system.cpu.icache.ReadReq_hits::cpu.inst 4013232208 # number of ReadReq hits
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system.cpu.icache.demand_hits::cpu.inst 4013232208 # number of demand (read+write) hits
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53045.925926 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 53045.925926 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.l2cache.tags.occ_blocks::writebacks 15396.795533 # Average occupied blocks per requestor
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system.cpu.l2cache.ReadReq_hits::total 6045911 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 3697956 # number of Writeback hits
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.064854 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.080657 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.ReadReq_hits::total 1231961896 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 436638511 # number of WriteReq hits
system.cpu.toL2Bus.trans_dist::Writeback 3697956 # Transaction distribution
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system.cpu.toL2Bus.trans_dist::ReadExResp 1889827 # Transaction distribution
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system.cpu.toL2Bus.data_through_bus 819923712 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy 10103610000 # Layer occupancy (ticks)
sim_ticks 41671895000 # Number of ticks simulated
final_tick 41671895000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 91903056 # Number of instructions simulated
sim_ops 91903056 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 178816 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 4291046 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 3292771 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 7583816 # Total bandwidth to/from this memory (bytes/s)
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-system.physmem.cpureqs 4938 # Reqs generatd by CPU via cache - shady
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system.physmem.bytesRead 316032 # Total number of bytes read from memory
system.physmem.bytesWritten 0 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 316032 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
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system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 443 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 270 # Track reads on a per bank basis
system.membus.trans_dist::ReadResp 3216 # Transaction distribution
system.membus.trans_dist::ReadExReq 1722 # Transaction distribution
system.membus.trans_dist::ReadExResp 1722 # Transaction distribution
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system.membus.data_through_bus 316032 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.membus.reqLayer0.occupancy 5784500 # Layer occupancy (ticks)
system.cpu.stage4.idleCycles 29484037 # Number of cycles 0 instructions are processed.
system.cpu.stage4.runCycles 53859754 # Number of cycles 1+ instructions are processed.
system.cpu.stage4.utilization 64.623595 # Percentage of cycles stage was utilized (processing insts).
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system.cpu.icache.ReadReq_hits::cpu.inst 9945551 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 9945551 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 9945551 # number of demand (read+write) hits
system.cpu.toL2Bus.trans_dist::Writeback 107 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 1748 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 1748 # Transaction distribution
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system.cpu.toL2Bus.data_through_bus 758400 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy 6032000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 3600000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
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system.cpu.l2cache.tags.occ_blocks::writebacks 17.843770 # Average occupied blocks per requestor
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+system.cpu.l2cache.tags.occ_blocks::cpu.inst 1820.865070 # Average occupied blocks per requestor
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system.cpu.l2cache.tags.occ_percent::writebacks 0.000545 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.055568 # Average percentage of cache occupancy
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system.cpu.l2cache.ReadReq_hits::cpu.inst 6726 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 53 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 6779 # number of ReadReq hits
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 55345.382463 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53827.663021 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.ReadReq_hits::total 19995622 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 6492886 # number of WriteReq hits
sim_ticks 23492267500 # Number of ticks simulated
final_tick 23492267500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 84179709 # Number of instructions simulated
sim_ops 84179709 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 195904 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 8339084 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 5898111 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 14237195 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bytesRead 334464 # Total number of bytes read from memory
system.physmem.bytesWritten 0 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 334464 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
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system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 469 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 291 # Track reads on a per bank basis
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system.membus.trans_dist::ReadExResp 1706 # Transaction distribution
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system.membus.data_through_bus 334464 # Total data (bytes)
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system.membus.reqLayer0.occupancy 6824500 # Layer occupancy (ticks)
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system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
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system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
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system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 25714.605813 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 25714.605813 # average overall mshr miss latency
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system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54013.681592 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.ReadReq_hits::total 21603146 # number of ReadReq hits
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final_tick 118729316000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
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+host_op_rate 2022504 # Simulator op (including micro ops) rate (op/s)
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host_mem_usage 228676 # Number of bytes of host memory used
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sim_insts 91903056 # Number of instructions simulated
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system.membus.trans_dist::ReadExReq 1722 # Transaction distribution
system.membus.trans_dist::ReadExResp 1722 # Transaction distribution
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system.membus.data_through_bus 304960 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
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system.cpu.idle_fraction 0 # Percentage of idle cycles
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system.cpu.icache.overall_avg_mshr_miss_latency::total 23935.605170 # average overall mshr miss latency
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system.cpu.toL2Bus.trans_dist::ReadExResp 1748 # Transaction distribution
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+system.cpu.toL2Bus.tot_pkt_size::total 693760 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus 693760 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy 5527000 # Layer occupancy (ticks)
sim_ticks 74201024500 # Number of ticks simulated
final_tick 74201024500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
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-host_op_rate 89268 # Simulator op (including micro ops) rate (op/s)
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sim_insts 172303021 # Number of instructions simulated
sim_ops 188656503 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 131328 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 1769895 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 1507688 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 3277583 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 3801 # Total number of read requests seen
-system.physmem.writeReqs 0 # Total number of write requests seen
-system.physmem.cpureqs 3803 # Reqs generatd by CPU via cache - shady
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+system.physmem.readBursts 3801 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
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system.physmem.bytesRead 243200 # Total number of bytes read from memory
system.physmem.bytesWritten 0 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 243200 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
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system.physmem.neitherReadNorWrite 2 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 308 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 215 # Track reads on a per bank basis
system.membus.trans_dist::UpgradeResp 2 # Transaction distribution
system.membus.trans_dist::ReadExReq 1075 # Transaction distribution
system.membus.trans_dist::ReadExResp 1075 # Transaction distribution
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system.membus.data_through_bus 243200 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.membus.reqLayer0.occupancy 4684500 # Layer occupancy (ticks)
system.cpu.toL2Bus.trans_dist::UpgradeResp 2 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 1083 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 1083 # Transaction distribution
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system.cpu.toL2Bus.data_through_bus 383680 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 128 # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy 3018000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 3106490 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
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system.cpu.icache.ReadReq_hits::cpu.inst 36834377 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 36834377 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 36834377 # number of demand (read+write) hits
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39366.607030 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 39366.607030 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.l2cache.tags.occ_blocks::writebacks 4.994051 # Average occupied blocks per requestor
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system.cpu.l2cache.tags.occ_percent::writebacks 0.000152 # Average percentage of cache occupancy
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system.cpu.l2cache.ReadReq_hits::cpu.inst 2065 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 87 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 2152 # number of ReadReq hits
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53045.480549 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53705.077611 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.ReadReq_hits::cpu.data 34397014 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 34397014 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 12356557 # number of WriteReq hits
sim_ticks 232072304000 # Number of ticks simulated
final_tick 232072304000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 171842483 # Number of instructions simulated
sim_ops 188185920 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 110656 # Number of bytes read from this memory
system.membus.trans_dist::ReadResp 2361 # Transaction distribution
system.membus.trans_dist::ReadExReq 1092 # Transaction distribution
system.membus.trans_dist::ReadExResp 1092 # Transaction distribution
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-system.membus.tot_pkt_size 220992 # Cumulative packet size per connected master and slave (bytes)
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system.membus.data_through_bus 220992 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.membus.reqLayer0.occupancy 3453000 # Layer occupancy (ticks)
system.cpu.num_busy_cycles 464144608 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
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system.cpu.icache.ReadReq_hits::cpu.inst 189857001 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 189857001 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 189857001 # number of demand (read+write) hits
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34801.376598 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 34801.376598 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.l2cache.ReadReq_hits::total 1379 # number of ReadReq hits
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
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system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.ReadReq_hits::total 29599357 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 12363187 # number of WriteReq hits
system.cpu.toL2Bus.trans_dist::Writeback 16 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 1100 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 1100 # Transaction distribution
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+system.cpu.toL2Bus.tot_pkt_size::total 310784 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus 310784 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy 2444000 # Layer occupancy (ticks)
sim_ticks 270563082000 # Number of ticks simulated
final_tick 270563082000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 942019 # Simulator instruction rate (inst/s)
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-host_seconds 205.35 # Real time elapsed on the host
+host_inst_rate 872463 # Simulator instruction rate (inst/s)
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sim_insts 193444518 # Number of instructions simulated
sim_ops 193444756 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 230208 # Number of bytes read from this memory
system.membus.trans_dist::ReadResp 4095 # Transaction distribution
system.membus.trans_dist::ReadExReq 1078 # Transaction distribution
system.membus.trans_dist::ReadExResp 1078 # Transaction distribution
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-system.membus.pkt_count 10346 # Packet count per connected master and slave (bytes)
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-system.membus.tot_pkt_size 331072 # Cumulative packet size per connected master and slave (bytes)
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system.membus.data_through_bus 331072 # Total data (bytes)
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system.membus.reqLayer0.occupancy 5173000 # Layer occupancy (ticks)
system.cpu.num_busy_cycles 541126164 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
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system.cpu.icache.ReadReq_hits::cpu.inst 193433248 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 193433248 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 193433248 # number of demand (read+write) hits
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23294.433594 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 23294.433594 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.l2cache.tags.occ_blocks::writebacks 0.000453 # Average occupied blocks per requestor
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system.cpu.l2cache.ReadReq_hits::total 8691 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 2 # number of Writeback hits
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system.cpu.dcache.ReadReq_hits::total 57734570 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 18975362 # number of WriteReq hits
system.cpu.toL2Bus.trans_dist::Writeback 2 # Transaction distribution
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system.cpu.toL2Bus.trans_dist::ReadExResp 1078 # Transaction distribution
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system.cpu.toL2Bus.data_through_bus 887424 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy 6935000 # Layer occupancy (ticks)
sim_ticks 144470654000 # Number of ticks simulated
final_tick 144470654000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 132071192 # Number of instructions simulated
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system.physmem.bw_total::cpu.inst 1500429 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 865172 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 2365602 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bytesRead 341760 # Total number of bytes read from memory
system.physmem.bytesWritten 0 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 341760 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
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system.physmem.neitherReadNorWrite 152 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 286 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 358 # Track reads on a per bank basis
system.membus.trans_dist::ReadExResp 1530 # Transaction distribution
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system.membus.pkt_count::total 10983 # Packet count per connected master and slave (bytes)
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system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 341696 # Cumulative packet size per connected master and slave (bytes)
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system.membus.tot_pkt_size::total 341696 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 341696 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.toL2Bus.trans_dist::UpgradeResp 153 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 1537 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 1537 # Transaction distribution
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system.cpu.toL2Bus.data_through_bus 552320 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 9856 # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy 4483500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 3515652 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
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system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 38650.612637 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 38650.612637 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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+system.cpu.l2cache.tags.tagsinuse 2537.222896 # Cycle average of tags in use
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system.cpu.l2cache.tags.occ_blocks::writebacks 1.748933 # Average occupied blocks per requestor
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+system.cpu.l2cache.tags.occ_blocks::cpu.inst 2223.089774 # Average occupied blocks per requestor
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system.cpu.l2cache.ReadReq_hits::cpu.data 38 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 3270 # number of ReadReq hits
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 52681.515617 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 52954.736941 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
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+system.cpu.dcache.tags.tagsinuse 1433.333580 # Cycle average of tags in use
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system.cpu.dcache.ReadReq_hits::cpu.data 45609763 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 45609763 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 20514039 # number of WriteReq hits
sim_ticks 250953957000 # Number of ticks simulated
final_tick 250953957000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
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-host_seconds 194.28 # Real time elapsed on the host
+host_inst_rate 352771 # Simulator instruction rate (inst/s)
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sim_insts 132071193 # Number of instructions simulated
sim_ops 221362963 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 181760 # Number of bytes read from this memory
system.membus.trans_dist::ReadExResp 1575 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 9470 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 9470 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::system.physmem.port 9470 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 9470 # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 303040 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 303040 # Cumulative packet size per connected master and slave (bytes)
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system.membus.tot_pkt_size::total 303040 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 303040 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.num_busy_cycles 501907914 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
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+system.cpu.icache.tags.tagsinuse 1455.296642 # Cycle average of tags in use
+system.cpu.icache.tags.total_refs 173489674 # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs 4694 # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs 36959.879421 # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.icache.demand_hits::cpu.inst 173489674 # number of demand (read+write) hits
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36414.784832 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 36414.784832 # average overall mshr miss latency
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system.cpu.l2cache.tags.occ_blocks::writebacks 0.021744 # Average occupied blocks per requestor
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system.cpu.dcache.ReadReq_hits::total 56681678 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 20514153 # number of WriteReq hits
system.cpu.toL2Bus.trans_dist::Writeback 7 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 1578 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 1578 # Transaction distribution
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system.cpu.toL2Bus.data_through_bus 422784 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy 3310000 # Layer occupancy (ticks)
system.physmem.bw_total::cpu1.inst 59335 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 357514 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 42102082 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bytesRead 0 # Total number of bytes read from memory
system.physmem.bytesWritten 0 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 0 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
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system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis
system.physmem.bw_total::cpu.data 36537607 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::tsunami.ide 1449867 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 42507908 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bytesRead 0 # Total number of bytes read from memory
system.physmem.bytesWritten 0 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 0 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
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system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis
sim_ticks 1961841175000 # Number of ticks simulated
final_tick 1961841175000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 59351715 # Number of instructions simulated
sim_ops 59351715 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu0.inst 831360 # Number of bytes read from this memory
system.physmem.bw_total::cpu1.inst 16409 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 146703 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 18586263 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bytesRead 28716928 # Total number of bytes read from memory
system.physmem.bytesWritten 7746368 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 28716928 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 7746368 # bytesWritten derated as per pkt->getSize()
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system.physmem.neitherReadNorWrite 3165 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 27842 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 28115 # Track reads on a per bank basis
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system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124669 # Packet count per connected master and slave (bytes)
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system.membus.pkt_count::total 1066505 # Packet count per connected master and slave (bytes)
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system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 31155200 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::total 31223794 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5308096 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::total 5308096 # Cumulative packet size per connected master and slave (bytes)
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system.membus.tot_pkt_size::total 36531890 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 36531890 # Total data (bytes)
system.membus.snoop_data_through_bus 36736 # Total snoop data (bytes)
system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
system.membus.respLayer2.occupancy 376257250 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
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system.l2c.ReadReq_hits::cpu0.inst 908184 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data 776732 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst 79667 # number of ReadReq hits
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
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+system.iocache.tags.warmup_cycle 1754539957000 # Cycle when the warmup percentage was hit.
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system.iocache.ReadReq_misses::tsunami.ide 178 # number of ReadReq misses
system.iocache.ReadReq_misses::total 178 # number of ReadReq misses
system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses
system.toL2Bus.trans_dist::UpgradeResp 5142 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 348581 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 307031 # Transaction distribution
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-system.toL2Bus.pkt_count_system.cpu1.icache.mem_side 160357 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side 115223 # Packet count per connected master and slave (bytes)
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-system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side 5131392 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side 4050090 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size 205243314 # Cumulative packet size per connected master and slave (bytes)
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+system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 115223 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 5652298 # Packet count per connected master and slave (bytes)
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+system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 137106504 # Cumulative packet size per connected master and slave (bytes)
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+system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 4050090 # Cumulative packet size per connected master and slave (bytes)
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system.toL2Bus.data_through_bus 205232754 # Total data (bytes)
system.toL2Bus.snoop_data_through_bus 908800 # Total snoop data (bytes)
system.toL2Bus.reqLayer0.occupancy 4911962990 # Layer occupancy (ticks)
system.iobus.pkt_count_system.bridge.master::total 39192 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83460 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::total 83460 # Packet count per connected master and slave (bytes)
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-system.iobus.pkt_count::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.tsunami.uart.pio 18148 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.tsunami.backdoor.pio 2474 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.iocache.cpu_side 83460 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total 122652 # Packet count per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 42328 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1920 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::total 68594 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661648 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661648 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.tsunami.cchip.pio 42328 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.tsunami.pchip.pio 1920 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.tsunami.backdoor.pio 9876 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.iocache.cpu_side 2661648 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::total 2730242 # Cumulative packet size per connected master and slave (bytes)
system.iobus.data_through_bus 2730242 # Total data (bytes)
system.iobus.reqLayer0.occupancy 9937000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer1.occupancy 43124750 # Layer occupancy (ticks)
system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.cpu0.icache.tags.replacements 920572 # number of replacements
-system.cpu0.icache.tags.tagsinuse 508.501962 # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs 53689788 # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs 921084 # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs 58.289785 # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle 39101383250 # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.replacements 920572 # number of replacements
+system.cpu0.icache.tags.tagsinuse 508.501962 # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs 53689788 # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs 921084 # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs 58.289785 # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle 39101383250 # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.501962 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.993168 # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total 0.993168 # Average percentage of cache occupancy
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system.cpu0.icache.ReadReq_hits::cpu0.inst 53689788 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 53689788 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 53689788 # number of demand (read+write) hits
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12037.609635 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 12037.609635 # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.dcache.tags.replacements 1349865 # number of replacements
-system.cpu0.dcache.tags.tagsinuse 506.612721 # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs 13528796 # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs 1350377 # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs 10.018533 # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle 105754250 # Cycle when the warmup percentage was hit.
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+system.cpu0.dcache.tags.total_refs 13528796 # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs 1350377 # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs 10.018533 # Average number of references to valid blocks.
+system.cpu0.dcache.tags.warmup_cycle 105754250 # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data 506.612721 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.989478 # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total 0.989478 # Average percentage of cache occupancy
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system.cpu0.dcache.ReadReq_hits::cpu0.data 7507195 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 7507195 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 5646858 # number of WriteReq hits
system.cpu1.kern.mode_ticks::user 1487213000 0.08% 0.22% # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::idle 1955685685000 99.78% 100.00% # number of ticks spent at the given mode
system.cpu1.kern.swap_context 284 # number of times the context was actually changed
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-system.cpu1.icache.tags.tagsinuse 421.213832 # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs 4672446 # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs 80140 # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs 58.303544 # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle 1959882431000 # Cycle when the warmup percentage was hit.
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+system.cpu1.icache.tags.warmup_cycle 1959882431000 # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst 421.213832 # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst 0.822683 # Average percentage of cache occupancy
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system.cpu1.icache.ReadReq_hits::cpu1.inst 4672446 # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total 4672446 # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst 4672446 # number of demand (read+write) hits
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11492.510608 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 11492.510608 # average overall mshr miss latency
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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-system.cpu1.dcache.tags.tagsinuse 416.865345 # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs 1457107 # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs 41228 # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs 35.342655 # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle 1941571028000 # Cycle when the warmup percentage was hit.
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+system.cpu1.dcache.tags.total_refs 1457107 # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs 41228 # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs 35.342655 # Average number of references to valid blocks.
+system.cpu1.dcache.tags.warmup_cycle 1941571028000 # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data 416.865345 # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data 0.814190 # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total 0.814190 # Average percentage of cache occupancy
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system.cpu1.dcache.ReadReq_hits::cpu1.data 917421 # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total 917421 # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data 531046 # number of WriteReq hits
sim_ticks 1918473094000 # Number of ticks simulated
final_tick 1918473094000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 813863 # Simulator instruction rate (inst/s)
-host_op_rate 813863 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 27788392408 # Simulator tick rate (ticks/s)
-host_mem_usage 306196 # Number of bytes of host memory used
-host_seconds 69.04 # Real time elapsed on the host
+host_inst_rate 948634 # Simulator instruction rate (inst/s)
+host_op_rate 948634 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 32389976926 # Simulator tick rate (ticks/s)
+host_mem_usage 304780 # Number of bytes of host memory used
+host_seconds 59.23 # Real time elapsed on the host
sim_insts 56188014 # Number of instructions simulated
sim_ops 56188014 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 850688 # Number of bytes read from this memory
system.physmem.bw_total::cpu.data 12951700 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::tsunami.ide 1382533 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 18629615 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 442977 # Total number of read requests seen
-system.physmem.writeReqs 115467 # Total number of write requests seen
-system.physmem.cpureqs 558574 # Reqs generatd by CPU via cache - shady
+system.physmem.readReqs 442977 # Total number of read requests accepted by DRAM controller
+system.physmem.writeReqs 115467 # Total number of write requests accepted by DRAM controller
+system.physmem.readBursts 442977 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
+system.physmem.writeBursts 115467 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
system.physmem.bytesRead 28350528 # Total number of bytes read from memory
system.physmem.bytesWritten 7389888 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 28350528 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 7389888 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 50 # Number of read reqs serviced by write Q
+system.physmem.servicedByWrQ 50 # Number of DRAM read bursts serviced by write Q
system.physmem.neitherReadNorWrite 130 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 27963 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 28090 # Track reads on a per bank basis
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 910714 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124680 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 124680 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::system.bridge.slave 33158 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::system.physmem.port 1002236 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 1035394 # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44556 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30431296 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 30475852 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5309120 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::total 5309120 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::system.bridge.slave 44556 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::system.physmem.port 35740416 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total 35784972 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 35784972 # Total data (bytes)
system.membus.snoop_data_through_bus 35392 # Total snoop data (bytes)
system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
system.membus.respLayer2.occupancy 376206000 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.iocache.tags.replacements 41685 # number of replacements
-system.iocache.tags.tagsinuse 1.345474 # Cycle average of tags in use
-system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks.
-system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle 1752558313000 # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::tsunami.ide 1.345474 # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::tsunami.ide 0.084092 # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total 0.084092 # Average percentage of cache occupancy
+system.iocache.tags.replacements 41685 # number of replacements
+system.iocache.tags.tagsinuse 1.345474 # Cycle average of tags in use
+system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
+system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks.
+system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
+system.iocache.tags.warmup_cycle 1752558313000 # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::tsunami.ide 1.345474 # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::tsunami.ide 0.084092 # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total 0.084092 # Average percentage of cache occupancy
system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses
system.iocache.ReadReq_misses::total 173 # number of ReadReq misses
system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses
system.iobus.pkt_count_system.bridge.master::total 33158 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.tsunami.cchip.pio 5154 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.tsunami.uart.pio 18120 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total 116608 # Packet count per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 20616 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::total 44556 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.tsunami.cchip.pio 20616 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::total 2706164 # Cumulative packet size per connected master and slave (bytes)
system.iobus.data_through_bus 2706164 # Total data (bytes)
system.iobus.reqLayer0.occupancy 4765000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer1.occupancy 43091000 # Layer occupancy (ticks)
system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.cpu.icache.tags.replacements 928665 # number of replacements
-system.cpu.icache.tags.tagsinuse 508.413691 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 55270512 # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs 929176 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 59.483362 # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle 38814414250 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 508.413691 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.992995 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.992995 # Average percentage of cache occupancy
+system.cpu.icache.tags.replacements 928665 # number of replacements
+system.cpu.icache.tags.tagsinuse 508.413691 # Cycle average of tags in use
+system.cpu.icache.tags.total_refs 55270512 # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs 929176 # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs 59.483362 # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle 38814414250 # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst 508.413691 # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst 0.992995 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total 0.992995 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 55270512 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 55270512 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 55270512 # number of demand (read+write) hits
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11998.051020 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 11998.051020 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements 336065 # number of replacements
-system.cpu.l2cache.tags.tagsinuse 65300.870394 # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs 2448301 # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs 401226 # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs 6.102050 # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle 6580892750 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.replacements 336065 # number of replacements
+system.cpu.l2cache.tags.tagsinuse 65300.870394 # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs 2448301 # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs 401226 # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs 6.102050 # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle 6580892750 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 55613.136753 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 4759.199410 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 4928.534231 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 4759.199410 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 4928.534231 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.848589 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.072620 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.075203 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total 0.996412 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total 0.996412 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 916024 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 814969 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 1730993 # number of ReadReq hits
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements 1390866 # number of replacements
-system.cpu.dcache.tags.tagsinuse 511.979110 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 14050029 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 1391378 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 10.097924 # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle 105729250 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 511.979110 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.999959 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.999959 # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements 1390866 # number of replacements
+system.cpu.dcache.tags.tagsinuse 511.979110 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 14050029 # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs 1391378 # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 10.097924 # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle 105729250 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data 511.979110 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data 0.999959 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total 0.999959 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 7815067 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 7815067 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 5852671 # number of WriteReq hits
system.cpu.toL2Bus.trans_dist::UpgradeResp 17 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 346045 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 304495 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1858652 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 3651517 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count 5510169 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 59476224 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 142569036 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size 202045260 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1858652 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3651517 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 5510169 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 59476224 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142569036 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total 202045260 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus 202035148 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 11392 # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy 2426591000 # Layer occupancy (ticks)
system.physmem.bw_total::cpu1.inst 235234 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 6988969 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 62341372 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 0 # Total number of read requests seen
-system.physmem.writeReqs 0 # Total number of write requests seen
-system.physmem.cpureqs 0 # Reqs generatd by CPU via cache - shady
+system.physmem.readReqs 0 # Total number of read requests accepted by DRAM controller
+system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller
+system.physmem.readBursts 0 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
+system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
system.physmem.bytesRead 0 # Total number of bytes read from memory
system.physmem.bytesWritten 0 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 0 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
+system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis
system.physmem.bw_total::cpu.inst 302262 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 5181496 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 54942169 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 0 # Total number of read requests seen
-system.physmem.writeReqs 0 # Total number of write requests seen
-system.physmem.cpureqs 0 # Reqs generatd by CPU via cache - shady
+system.physmem.readReqs 0 # Total number of read requests accepted by DRAM controller
+system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller
+system.physmem.readBursts 0 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
+system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
system.physmem.bytesRead 0 # Total number of bytes read from memory
system.physmem.bytesWritten 0 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 0 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
+system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis
---------- Begin Simulation Statistics ----------
-sim_seconds 1.194911 # Number of seconds simulated
-sim_ticks 1194911360500 # Number of ticks simulated
-final_tick 1194911360500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 1.194884 # Number of seconds simulated
+sim_ticks 1194883580500 # Number of ticks simulated
+final_tick 1194883580500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 773513 # Simulator instruction rate (inst/s)
-host_op_rate 985724 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 15060857671 # Simulator tick rate (ticks/s)
-host_mem_usage 403580 # Number of bytes of host memory used
-host_seconds 79.34 # Real time elapsed on the host
-sim_insts 61369589 # Number of instructions simulated
-sim_ops 78206230 # Number of ops (including micro ops) simulated
+host_inst_rate 298011 # Simulator instruction rate (inst/s)
+host_op_rate 379758 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 5802481089 # Simulator tick rate (ticks/s)
+host_mem_usage 399660 # Number of bytes of host memory used
+host_seconds 205.93 # Real time elapsed on the host
+sim_insts 61368273 # Number of instructions simulated
+sim_ops 78202205 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::realview.clcd 51904512 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.dtb.walker 256 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst 464036 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 6626228 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst 463716 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 6626292 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 256092 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 2904304 # Number of bytes read from this memory
-system.physmem.bytes_read::total 62155620 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 464036 # Number of instructions bytes read from this memory
+system.physmem.bytes_read::cpu1.data 2904240 # Number of bytes read from this memory
+system.physmem.bytes_read::total 62155300 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 463716 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 256092 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 720128 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 4136576 # Number of bytes written to this memory
+system.physmem.bytes_inst_read::total 719808 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 4136384 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data 3027304 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory
-system.physmem.bytes_written::total 7163920 # Number of bytes written to this memory
+system.physmem.bytes_written::total 7163728 # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd 6488064 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.dtb.walker 4 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst 13469 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 103607 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst 13464 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 103608 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 4083 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 45406 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 6654636 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 64634 # Number of write requests responded to by this memory
+system.physmem.num_reads::cpu1.data 45405 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 6654631 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 64631 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data 756826 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 821470 # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd 43437960 # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total 821467 # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd 43438970 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.dtb.walker 214 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 107 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst 388343 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 5545372 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst 388085 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 5545554 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker 54 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 214319 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 2430560 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 52016930 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 388343 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 214319 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 602662 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 3461827 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data 2533497 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 214324 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 2430563 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 52017871 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 388085 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 214324 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 602408 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 3461746 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data 2533556 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data 33 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 5995357 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 3461827 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd 43437960 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::total 5995336 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 3461746 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd 43438970 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker 214 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 107 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 388343 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 8078869 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 388085 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 8079110 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker 54 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 214319 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 2430594 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 58012286 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 6654636 # Total number of read requests seen
-system.physmem.writeReqs 821470 # Total number of write requests seen
-system.physmem.cpureqs 235013 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 425896704 # Total number of bytes read from memory
-system.physmem.bytesWritten 52574080 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 62155620 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 7163920 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 138 # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite 10632 # Reqs where no action is needed
+system.physmem.bw_total::cpu1.inst 214324 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 2430597 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 58013207 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 6654631 # Total number of read requests accepted by DRAM controller
+system.physmem.writeReqs 821467 # Total number of write requests accepted by DRAM controller
+system.physmem.readBursts 6654631 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
+system.physmem.writeBursts 821467 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
+system.physmem.bytesRead 425896384 # Total number of bytes read from memory
+system.physmem.bytesWritten 52573888 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 62155300 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 7163728 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 531 # Number of DRAM read bursts serviced by write Q
+system.physmem.neitherReadNorWrite 10643 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 415730 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 415559 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 414961 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 414958 # Track reads on a per bank basis
system.physmem.perBankRdReqs::3 415336 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 422399 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 415419 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 415520 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 415301 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 415351 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 422327 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 415339 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 415446 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 415286 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 415350 # Track reads on a per bank basis
system.physmem.perBankRdReqs::9 415631 # Track reads on a per bank basis
system.physmem.perBankRdReqs::10 415270 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 414902 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 414743 # Track reads on a per bank basis
system.physmem.perBankRdReqs::12 415547 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 416081 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 415762 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 415729 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 50036 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 49924 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2 51325 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 51581 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 51864 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5 51435 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6 51646 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 51467 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 51327 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 51592 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 51318 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11 51082 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12 51567 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13 51872 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14 51738 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15 51696 # Track writes on a per bank basis
+system.physmem.perBankRdReqs::13 416088 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 415759 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 415731 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 7326 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 7216 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 6699 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 6873 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 7393 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 6968 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 7176 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 6994 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 6995 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 7264 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 6985 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 6704 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 7238 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 7541 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 7391 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 7368 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 1194906959500 # Total gap between requests
+system.physmem.totGap 1194879167500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 6825 # Categorize read packet sizes
system.physmem.readPktSize::3 6488064 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 159747 # Categorize read packet sizes
+system.physmem.readPktSize::6 159742 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
system.physmem.writePktSize::2 756836 # Categorize write packet sizes
system.physmem.writePktSize::3 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
-system.physmem.writePktSize::6 64634 # Categorize write packet sizes
-system.physmem.rdQLenPdf::0 581277 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 421174 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 435266 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 1590102 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 1186915 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 1183214 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 1164468 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 13127 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 10448 # What read queue length does an incoming req see
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-system.physmem.bytesPerActivate::samples 34668 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 13801.223030 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 734.240341 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 27780.651463 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::64-127 7945 22.92% 22.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-191 4005 11.55% 34.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::192-255 2676 7.72% 42.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-319 1963 5.66% 47.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::320-383 1415 4.08% 51.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-447 1138 3.28% 55.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::448-511 895 2.58% 57.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-575 859 2.48% 60.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::576-639 666 1.92% 62.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-703 565 1.63% 63.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::704-767 463 1.34% 65.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-831 439 1.27% 66.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::832-895 280 0.81% 67.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-959 254 0.73% 67.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::960-1023 189 0.55% 68.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1087 312 0.90% 69.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1088-1151 134 0.39% 69.80% # Bytes accessed per row activation
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-system.physmem.bytesPerActivate::1472-1535 949 2.74% 74.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1536-1599 269 0.78% 75.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1600-1663 135 0.39% 75.48% # Bytes accessed per row activation
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-system.physmem.bytesPerActivate::2752-2815 7 0.02% 77.62% # Bytes accessed per row activation
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-system.physmem.bytesPerActivate::3008-3071 9 0.03% 77.74% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::12032-12095 1 0.00% 81.13% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::12288-12351 2 0.01% 81.13% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::12544-12607 1 0.00% 81.14% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::12800-12863 3 0.01% 81.14% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::13056-13119 1 0.00% 81.15% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::13312-13375 3 0.01% 81.16% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::13568-13631 1 0.00% 81.16% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::13824-13887 1 0.00% 81.16% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::14080-14143 1 0.00% 81.17% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::14208-14271 1 0.00% 81.17% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::14336-14399 1 0.00% 81.17% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::14848-14911 3 0.01% 81.18% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::15104-15167 2 0.01% 81.19% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::15360-15423 5 0.01% 81.20% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::15616-15679 1 0.00% 81.20% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::16128-16191 1 0.00% 81.21% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::16384-16447 1 0.00% 81.21% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::16640-16703 1 0.00% 81.21% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::16896-16959 1 0.00% 81.22% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::17152-17215 1 0.00% 81.22% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::17408-17471 4 0.01% 81.23% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::18176-18239 1 0.00% 81.23% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::18432-18495 3 0.01% 81.24% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::18688-18751 1 0.00% 81.24% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::18944-19007 1 0.00% 81.25% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::19136-19199 1 0.00% 81.25% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::19200-19263 1 0.00% 81.25% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::19328-19391 1 0.00% 81.26% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::19456-19519 3 0.01% 81.26% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::19712-19775 2 0.01% 81.27% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::19968-20031 2 0.01% 81.28% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::20480-20543 4 0.01% 81.29% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::20992-21055 1 0.00% 81.29% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::21248-21311 3 0.01% 81.30% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::21504-21567 5 0.01% 81.31% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::22272-22335 1 0.00% 81.32% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::23552-23615 2 0.01% 81.32% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::24064-24127 3 0.01% 81.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::24320-24383 1 0.00% 81.34% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::24576-24639 2 0.01% 81.34% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::25088-25151 1 0.00% 81.34% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::25600-25663 3 0.01% 81.35% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::26112-26175 2 0.01% 81.36% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::26368-26431 1 0.00% 81.36% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::26624-26687 1 0.00% 81.36% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::27136-27199 3 0.01% 81.37% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::27392-27455 4 0.01% 81.38% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::27648-27711 2 0.01% 81.39% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::28416-28479 1 0.00% 81.39% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::28672-28735 3 0.01% 81.40% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::28928-28991 1 0.00% 81.41% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::29184-29247 1 0.00% 81.41% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::29440-29503 1 0.00% 81.41% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::29696-29759 4 0.01% 81.42% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::29952-30015 1 0.00% 81.43% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::30208-30271 1 0.00% 81.43% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::30976-31039 3 0.01% 81.44% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::31232-31295 3 0.01% 81.45% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::31488-31551 2 0.01% 81.45% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::31744-31807 3 0.01% 81.46% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::32768-32831 4 0.01% 81.47% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::33024-33087 11 0.03% 81.50% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::33280-33343 42 0.12% 81.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::33792-33855 1 0.00% 81.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::34048-34111 1 0.00% 81.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::34112-34175 1 0.00% 81.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::35072-35135 1 0.00% 81.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::35840-35903 1 0.00% 81.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::36864-36927 1 0.00% 81.65% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::37120-37183 1 0.00% 81.65% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::37888-37951 2 0.01% 81.65% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::38144-38207 1 0.00% 81.66% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::38912-38975 1 0.00% 81.66% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::41472-41535 1 0.00% 81.66% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::41984-42047 1 0.00% 81.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::42240-42303 1 0.00% 81.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::44032-44095 1 0.00% 81.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::44800-44863 1 0.00% 81.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::45056-45119 2 0.01% 81.68% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::45568-45631 1 0.00% 81.68% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::45824-45887 1 0.00% 81.69% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::46208-46271 1 0.00% 81.69% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::47360-47423 1 0.00% 81.69% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::48128-48191 1 0.00% 81.70% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::48896-48959 1 0.00% 81.70% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::49152-49215 1 0.00% 81.70% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::49408-49471 1 0.00% 81.70% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::50176-50239 2 0.01% 81.71% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::50688-50751 1 0.00% 81.71% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::51328-51391 1 0.00% 81.72% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::52224-52287 1 0.00% 81.72% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::52480-52543 1 0.00% 81.72% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::52992-53055 1 0.00% 81.72% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::53248-53311 2 0.01% 81.73% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::55552-55615 1 0.00% 81.73% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::56128-56191 1 0.00% 81.74% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::57088-57151 1 0.00% 81.74% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::58112-58175 1 0.00% 81.74% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::58368-58431 1 0.00% 81.74% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::59392-59455 1 0.00% 81.75% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::60928-60991 1 0.00% 81.75% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::61440-61503 2 0.01% 81.76% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::61952-62015 1 0.00% 81.76% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::62464-62527 1 0.00% 81.76% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::62720-62783 1 0.00% 81.77% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::63680-63743 1 0.00% 81.77% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::65024-65087 39 0.11% 81.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::65280-65343 1 0.00% 81.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::65472-65535 1 0.00% 81.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::65536-65599 6180 18.09% 99.98% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::66880-66943 1 0.00% 99.99% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::66944-67007 1 0.00% 99.99% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::67904-67967 1 0.00% 99.99% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::74048-74111 1 0.00% 99.99% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::74112-74175 1 0.00% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::420352-420415 1 0.00% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 34668 # Bytes accessed per row activation
-system.physmem.totQLat 132807422500 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 174630638750 # Sum of mem lat for all requests
-system.physmem.totBusLat 33272490000 # Total cycles spent in databus access
-system.physmem.totBankLat 8550726250 # Total cycles spent in bank access
-system.physmem.avgQLat 19957.54 # Average queueing delay per request
-system.physmem.avgBankLat 1284.95 # Average bank access latency per request
+system.physmem.bytesPerActivate::total 34155 # Bytes accessed per row activation
+system.physmem.totQLat 126519681500 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 168380906500 # Sum of mem lat for all requests
+system.physmem.totBusLat 33270500000 # Total cycles spent in databus access
+system.physmem.totBankLat 8590725000 # Total cycles spent in bank access
+system.physmem.avgQLat 19013.79 # Average queueing delay per request
+system.physmem.avgBankLat 1291.04 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 26242.50 # Average memory access latency
+system.physmem.avgMemAccLat 25304.84 # Average memory access latency
system.physmem.avgRdBW 356.43 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 44.00 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 52.02 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 6.00 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 3.13 # Data bus utilization in percentage
-system.physmem.avgRdQLen 0.15 # Average read queue length over time
-system.physmem.avgWrQLen 11.97 # Average write queue length over time
-system.physmem.readRowHits 6636574 # Number of row buffer hits during reads
-system.physmem.writeRowHits 804724 # Number of row buffer hits during writes
+system.physmem.avgRdQLen 0.14 # Average read queue length over time
+system.physmem.avgWrQLen 14.04 # Average write queue length over time
+system.physmem.readRowHits 6636405 # Number of row buffer hits during reads
+system.physmem.writeRowHits 97666 # Number of row buffer hits during writes
system.physmem.readRowHitRate 99.73 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 97.96 # Row buffer hit rate for writes
-system.physmem.avgGap 159830.13 # Average gap between requests
+system.physmem.writeRowHitRate 11.89 # Row buffer hit rate for writes
+system.physmem.avgGap 159826.58 # Average gap between requests
system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory
system.realview.nvmem.bw_total::cpu0.inst 17 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst 40 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 57 # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput 60028739 # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq 7703151 # Transaction distribution
-system.membus.trans_dist::ReadResp 7703151 # Transaction distribution
-system.membus.trans_dist::WriteReq 767201 # Transaction distribution
-system.membus.trans_dist::WriteResp 767201 # Transaction distribution
-system.membus.trans_dist::Writeback 64634 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 27614 # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq 16407 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 10632 # Transaction distribution
-system.membus.trans_dist::ReadExReq 137758 # Transaction distribution
+system.membus.throughput 60029719 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 7703148 # Transaction distribution
+system.membus.trans_dist::ReadResp 7703148 # Transaction distribution
+system.membus.trans_dist::WriteReq 767203 # Transaction distribution
+system.membus.trans_dist::WriteResp 767203 # Transaction distribution
+system.membus.trans_dist::Writeback 64631 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 27692 # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq 16414 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 10643 # Transaction distribution
+system.membus.trans_dist::ReadExReq 137763 # Transaction distribution
system.membus.trans_dist::ReadExResp 137302 # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382564 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382562 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1966559 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 8856 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 8866 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 906 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total 4358923 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1966647 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total 4359019 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 12976128 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 12976128 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::system.bridge.slave 2382564 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::system.physmem.port 14942687 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::system.realview.gic.pio 8856 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::system.realview.local_cpu_timer.pio 906 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 17335051 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2389882 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count::total 17335147 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2389878 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17415028 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 17712 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 17732 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 1812 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::total 19824510 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17414516 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::total 19824014 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 51904512 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::total 51904512 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::system.bridge.slave 2389882 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::system.physmem.port 69319540 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::system.realview.gic.pio 17712 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::system.realview.local_cpu_timer.pio 1812 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 71729022 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 71729022 # Total data (bytes)
+system.membus.tot_pkt_size::total 71728526 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 71728526 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy 1208299500 # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy 1208318500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.membus.reqLayer1.occupancy 18000 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 9149149500 # Layer occupancy (ticks)
-system.membus.reqLayer2.utilization 0.8 # Layer utilization (%)
-system.membus.reqLayer3.occupancy 7960500 # Layer occupancy (ticks)
-system.membus.reqLayer3.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer5.occupancy 2500 # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy 7968000 # Layer occupancy (ticks)
+system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
+system.membus.reqLayer4.occupancy 2500 # Layer occupancy (ticks)
+system.membus.reqLayer4.utilization 0.0 # Layer utilization (%)
+system.membus.reqLayer5.occupancy 776500 # Layer occupancy (ticks)
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer6.occupancy 777000 # Layer occupancy (ticks)
-system.membus.reqLayer6.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer1.occupancy 5034294617 # Layer occupancy (ticks)
+system.membus.reqLayer6.occupancy 9149406000 # Layer occupancy (ticks)
+system.membus.reqLayer6.utilization 0.8 # Layer utilization (%)
+system.membus.respLayer1.occupancy 5034563338 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.4 # Layer utilization (%)
-system.membus.respLayer2.occupancy 14663453747 # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy 14646378749 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 1.2 # Layer utilization (%)
-system.l2c.tags.replacements 69629 # number of replacements
-system.l2c.tags.tagsinuse 53155.534639 # Cycle average of tags in use
-system.l2c.tags.total_refs 1651678 # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs 134776 # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs 12.254986 # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks 40041.185718 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.667860 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker 0.001521 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst 4638.655043 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data 5789.348152 # Average occupied blocks per requestor
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-system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma 6133 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma 11768 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count 7617950 # Packet count per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 31371320 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 53730420 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma 6036 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma 18516 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side 24083596 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side 27977862 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma 7228 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma 14216 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size 137209194 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.data_through_bus 137209194 # Total data (bytes)
-system.toL2Bus.snoop_data_through_bus 4306024 # Total snoop data (bytes)
-system.toL2Bus.reqLayer0.occupancy 4767819743 # Layer occupancy (ticks)
+system.toL2Bus.throughput 118384606 # Throughput (bytes/s)
+system.toL2Bus.trans_dist::ReadReq 2504676 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 2504676 # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq 767203 # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp 767203 # Transaction distribution
+system.toL2Bus.trans_dist::Writeback 576006 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 26963 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq 16769 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 43732 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 262452 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 262452 # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 993712 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2951029 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 5836 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 14921 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 753525 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 2879302 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side 6196 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 11995 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 7616516 # Packet count per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 31376632 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 53718524 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 5760 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 18112 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 24082060 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 27916814 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side 7480 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 15128 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size::total 137140510 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.data_through_bus 137140510 # Total data (bytes)
+system.toL2Bus.snoop_data_through_bus 4315312 # Total snoop data (bytes)
+system.toL2Bus.reqLayer0.occupancy 4764811697 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy 2217282985 # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy 2217607730 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy 2471819696 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy 2471552710 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy 4396500 # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy 10398000 # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy 10394000 # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer4.occupancy 1697865710 # Layer occupancy (ticks)
+system.toL2Bus.respLayer4.occupancy 1697838714 # Layer occupancy (ticks)
system.toL2Bus.respLayer4.utilization 0.1 # Layer utilization (%)
-system.toL2Bus.respLayer5.occupancy 2215426419 # Layer occupancy (ticks)
+system.toL2Bus.respLayer5.occupancy 2214012427 # Layer occupancy (ticks)
system.toL2Bus.respLayer5.utilization 0.2 # Layer utilization (%)
system.toL2Bus.respLayer6.occupancy 4326250 # Layer occupancy (ticks)
system.toL2Bus.respLayer6.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer7.occupancy 8214499 # Layer occupancy (ticks)
+system.toL2Bus.respLayer7.occupancy 8213499 # Layer occupancy (ticks)
system.toL2Bus.respLayer7.utilization 0.0 # Layer utilization (%)
-system.iobus.throughput 45438010 # Throughput (bytes/s)
-system.iobus.trans_dist::ReadReq 7671400 # Transaction distribution
-system.iobus.trans_dist::ReadResp 7671400 # Transaction distribution
+system.iobus.throughput 45439063 # Throughput (bytes/s)
+system.iobus.trans_dist::ReadReq 7671399 # Transaction distribution
+system.iobus.trans_dist::ReadResp 7671399 # Transaction distribution
system.iobus.trans_dist::WriteReq 7946 # Transaction distribution
system.iobus.trans_dist::WriteResp 7946 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30448 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8062 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8060 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 740 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 2382564 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 2382562 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 12976128 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.clcd.dma::total 12976128 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.uart.pio 30448 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.realview_io.pio 8062 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.timer1.pio 740 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.kmi1.pio 496 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.iocache.cpu_side 12976128 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 15358692 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 15358690 # Packet count per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 40166 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 16124 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 16120 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 1480 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::total 2389882 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::total 2389878 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 51904512 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.realview.clcd.dma::total 51904512 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.uart.pio 40166 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.realview_io.pio 16124 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.timer1.pio 1480 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.kmi1.pio 272 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.iocache.cpu_side 51904512 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::total 54294394 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.data_through_bus 54294394 # Total data (bytes)
+system.iobus.tot_pkt_size::total 54294390 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.data_through_bus 54294390 # Total data (bytes)
system.iobus.reqLayer0.occupancy 21350000 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer1.occupancy 4037000 # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy 4036000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.occupancy 34000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer25.occupancy 6488064000 # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization 0.5 # Layer utilization (%)
-system.iobus.respLayer0.occupancy 2374618000 # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy 2374616000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.2 # Layer utilization (%)
-system.iobus.respLayer1.occupancy 17765827253 # Layer occupancy (ticks)
+system.iobus.respLayer1.occupancy 17783069251 # Layer occupancy (ticks)
system.iobus.respLayer1.utilization 1.5 # Layer utilization (%)
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
-system.cpu0.dtb.read_hits 9651794 # DTB read hits
-system.cpu0.dtb.read_misses 3741 # DTB read misses
-system.cpu0.dtb.write_hits 7596285 # DTB write hits
+system.cpu0.dtb.read_hits 9653247 # DTB read hits
+system.cpu0.dtb.read_misses 3738 # DTB read misses
+system.cpu0.dtb.write_hits 7597488 # DTB write hits
system.cpu0.dtb.write_misses 1585 # DTB write misses
system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries 1811 # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults 138 # Number of TLB faults due to prefetch
+system.cpu0.dtb.prefetch_faults 134 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses 9655535 # DTB read accesses
-system.cpu0.dtb.write_accesses 7597870 # DTB write accesses
+system.cpu0.dtb.read_accesses 9656985 # DTB read accesses
+system.cpu0.dtb.write_accesses 7599073 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu0.dtb.hits 17248079 # DTB hits
-system.cpu0.dtb.misses 5326 # DTB misses
-system.cpu0.dtb.accesses 17253405 # DTB accesses
-system.cpu0.itb.inst_hits 43295611 # ITB inst hits
+system.cpu0.dtb.hits 17250735 # DTB hits
+system.cpu0.dtb.misses 5323 # DTB misses
+system.cpu0.dtb.accesses 17256058 # DTB accesses
+system.cpu0.itb.inst_hits 43297764 # ITB inst hits
system.cpu0.itb.inst_misses 2205 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
-system.cpu0.itb.inst_accesses 43297816 # ITB inst accesses
-system.cpu0.itb.hits 43295611 # DTB hits
+system.cpu0.itb.inst_accesses 43299969 # ITB inst accesses
+system.cpu0.itb.hits 43297764 # DTB hits
system.cpu0.itb.misses 2205 # DTB misses
-system.cpu0.itb.accesses 43297816 # DTB accesses
-system.cpu0.numCycles 2389822721 # number of cpu cycles simulated
+system.cpu0.itb.accesses 43299969 # DTB accesses
+system.cpu0.numCycles 2389767161 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.committedInsts 42568710 # Number of instructions committed
-system.cpu0.committedOps 53298123 # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses 48055390 # Number of integer alu accesses
+system.cpu0.committedInsts 42570861 # Number of instructions committed
+system.cpu0.committedOps 53303375 # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses 48060351 # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses 3860 # Number of float alu accesses
-system.cpu0.num_func_calls 1403445 # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts 5582451 # number of instructions that are conditional controls
-system.cpu0.num_int_insts 48055390 # number of integer instructions
+system.cpu0.num_func_calls 1403492 # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts 5582702 # number of instructions that are conditional controls
+system.cpu0.num_int_insts 48060351 # number of integer instructions
system.cpu0.num_fp_insts 3860 # number of float instructions
-system.cpu0.num_int_register_reads 272420788 # number of times the integer registers were read
-system.cpu0.num_int_register_writes 52266741 # number of times the integer registers were written
+system.cpu0.num_int_register_reads 272449792 # number of times the integer registers were read
+system.cpu0.num_int_register_writes 52270848 # number of times the integer registers were written
system.cpu0.num_fp_register_reads 3022 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 840 # number of times the floating registers were written
-system.cpu0.num_mem_refs 18017454 # number of memory refs
-system.cpu0.num_load_insts 10035613 # Number of load instructions
-system.cpu0.num_store_insts 7981841 # Number of store instructions
-system.cpu0.num_idle_cycles 2150296210.870201 # Number of idle cycles
-system.cpu0.num_busy_cycles 239526510.129800 # Number of busy cycles
-system.cpu0.not_idle_fraction 0.100228 # Percentage of non-idle cycles
-system.cpu0.idle_fraction 0.899772 # Percentage of idle cycles
+system.cpu0.num_mem_refs 18020156 # number of memory refs
+system.cpu0.num_load_insts 10037111 # Number of load instructions
+system.cpu0.num_store_insts 7983045 # Number of store instructions
+system.cpu0.num_idle_cycles 2150298949.878201 # Number of idle cycles
+system.cpu0.num_busy_cycles 239468211.121800 # Number of busy cycles
+system.cpu0.not_idle_fraction 0.100206 # Percentage of non-idle cycles
+system.cpu0.idle_fraction 0.899794 # Percentage of idle cycles
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
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+system.cpu0.dcache.overall_avg_miss_latency::total 25930.269819 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks 376581 # number of writebacks
-system.cpu0.dcache.writebacks::total 376581 # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 263761 # number of ReadReq MSHR misses
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-system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9920 # number of LoadLockedReq MSHR misses
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-system.cpu0.dcache.StoreCondReq_mshr_misses::total 7371 # number of StoreCondReq MSHR misses
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-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12700.742346 # average ReadReq mshr miss latency
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+system.cpu0.dcache.overall_mshr_uncacheable_latency::total 39571335961 # number of overall MSHR uncacheable cycles
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+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12685.907342 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12685.907342 # average ReadReq mshr miss latency
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+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7956.432896 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7956.432896 # average LoadLockedReq mshr miss latency
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+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3489.851606 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23841.276069 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23841.276069 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23841.276069 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23841.276069 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23815.082783 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23815.082783 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23815.082783 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23815.082783 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 5707792 # DTB read hits
-system.cpu1.dtb.read_misses 3579 # DTB read misses
-system.cpu1.dtb.write_hits 3874264 # DTB write hits
-system.cpu1.dtb.write_misses 643 # DTB write misses
+system.cpu1.dtb.read_hits 5705173 # DTB read hits
+system.cpu1.dtb.read_misses 3576 # DTB read misses
+system.cpu1.dtb.write_hits 3872049 # DTB write hits
+system.cpu1.dtb.write_misses 645 # DTB write misses
system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries 1989 # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults 150 # Number of TLB faults due to prefetch
+system.cpu1.dtb.prefetch_faults 144 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses 5711371 # DTB read accesses
-system.cpu1.dtb.write_accesses 3874907 # DTB write accesses
+system.cpu1.dtb.read_accesses 5708749 # DTB read accesses
+system.cpu1.dtb.write_accesses 3872694 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dtb.hits 9582056 # DTB hits
-system.cpu1.dtb.misses 4222 # DTB misses
-system.cpu1.dtb.accesses 9586278 # DTB accesses
-system.cpu1.itb.inst_hits 19381456 # ITB inst hits
+system.cpu1.dtb.hits 9577222 # DTB hits
+system.cpu1.dtb.misses 4221 # DTB misses
+system.cpu1.dtb.accesses 9581443 # DTB accesses
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system.cpu1.itb.inst_misses 2171 # ITB inst misses
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system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks 200060 # number of writebacks
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system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1000 # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles
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system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
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+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19773.388688 # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.iocache.tags.replacements 0 # number of replacements
-system.iocache.tags.tagsinuse 0 # Cycle average of tags in use
-system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks.
-system.iocache.tags.avg_refs nan # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.iocache.tags.replacements 0 # number of replacements
+system.iocache.tags.tagsinuse 0 # Cycle average of tags in use
+system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
+system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks.
+system.iocache.tags.avg_refs nan # Average number of references to valid blocks.
+system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 624927975253 # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 624927975253 # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 624927975253 # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 624927975253 # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 618710198251 # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 618710198251 # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 618710198251 # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 618710198251 # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
---------- Begin Simulation Statistics ----------
-sim_seconds 2.615733 # Number of seconds simulated
-sim_ticks 2615733285000 # Number of ticks simulated
-final_tick 2615733285000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 2.615716 # Number of seconds simulated
+sim_ticks 2615716222000 # Number of ticks simulated
+final_tick 2615716222000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 250012 # Simulator instruction rate (inst/s)
-host_op_rate 318151 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 10863402189 # Simulator tick rate (ticks/s)
-host_mem_usage 396412 # Number of bytes of host memory used
-host_seconds 240.78 # Real time elapsed on the host
-sim_insts 60198861 # Number of instructions simulated
-sim_ops 76605713 # Number of ops (including micro ops) simulated
+host_inst_rate 250038 # Simulator instruction rate (inst/s)
+host_op_rate 318184 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 10864403710 # Simulator tick rate (ticks/s)
+host_mem_usage 394540 # Number of bytes of host memory used
+host_seconds 240.76 # Real time elapsed on the host
+sim_insts 60199078 # Number of instructions simulated
+sim_ops 76605946 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::realview.clcd 122683392 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst 704864 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst 704928 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 9093712 # Number of bytes read from this memory
-system.physmem.bytes_read::total 132482416 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 704864 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 704864 # Number of instructions bytes read from this memory
+system.physmem.bytes_read::total 132482480 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 704928 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 704928 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 3710144 # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory
system.physmem.bytes_written::total 6726216 # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd 15335424 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.dtb.walker 5 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst 17216 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst 17217 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 142123 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 15494770 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 15494771 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 57971 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory
system.physmem.num_writes::total 811989 # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd 46902103 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.clcd 46902409 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.dtb.walker 122 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker 49 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst 269471 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 3476544 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 50648289 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 269471 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 269471 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1418395 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data 1153050 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 2571446 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1418395 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd 46902103 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 269497 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 3476567 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 50648644 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 269497 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 269497 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 1418405 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data 1153058 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 2571462 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 1418405 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd 46902409 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker 122 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker 49 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 269471 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 4629594 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 53219735 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 15494770 # Total number of read requests seen
-system.physmem.writeReqs 811989 # Total number of write requests seen
-system.physmem.cpureqs 215180 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 991665280 # Total number of bytes read from memory
+system.physmem.bw_total::cpu.inst 269497 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 4629625 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 53220107 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 15494771 # Total number of read requests accepted by DRAM controller
+system.physmem.writeReqs 811989 # Total number of write requests accepted by DRAM controller
+system.physmem.readBursts 15494771 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
+system.physmem.writeBursts 811989 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
+system.physmem.bytesRead 991665344 # Total number of bytes read from memory
system.physmem.bytesWritten 51967296 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 132482416 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedRd 132482480 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 6726216 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 299 # Number of read reqs serviced by write Q
+system.physmem.servicedByWrQ 1656 # Number of DRAM read bursts serviced by write Q
system.physmem.neitherReadNorWrite 4515 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 968107 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::0 968108 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 967905 # Track reads on a per bank basis
system.physmem.perBankRdReqs::2 967771 # Track reads on a per bank basis
system.physmem.perBankRdReqs::3 967944 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 974725 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 968490 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 967971 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 967840 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 974355 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 968114 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 967591 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 967671 # Track reads on a per bank basis
system.physmem.perBankRdReqs::8 968519 # Track reads on a per bank basis
system.physmem.perBankRdReqs::9 968300 # Track reads on a per bank basis
system.physmem.perBankRdReqs::10 967957 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 967809 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 967810 # Track reads on a per bank basis
system.physmem.perBankRdReqs::12 967935 # Track reads on a per bank basis
system.physmem.perBankRdReqs::13 967629 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 967887 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 967682 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 49150 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 49013 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2 50857 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 50909 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 51128 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5 51425 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6 51159 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 51254 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 51364 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 51157 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 50876 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11 50797 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12 50874 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13 50522 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14 50827 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15 50677 # Track writes on a per bank basis
+system.physmem.perBankRdReqs::14 967816 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 967690 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 6734 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 6600 # Track writes on a per bank basis
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+system.physmem.perBankWrReqs::3 6493 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 6702 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 6993 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 6729 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 6823 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 7180 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 6976 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 6694 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 6614 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 6691 # Track writes on a per bank basis
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+system.physmem.perBankWrReqs::14 6636 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 6497 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 2615728912000 # Total gap between requests
+system.physmem.totGap 2615711849000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 6652 # Categorize read packet sizes
system.physmem.readPktSize::3 15335424 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 152694 # Categorize read packet sizes
+system.physmem.readPktSize::6 152695 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
system.physmem.writePktSize::2 754018 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
system.physmem.writePktSize::6 57971 # Categorize write packet sizes
-system.physmem.rdQLenPdf::0 1128832 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 975833 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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-system.physmem.wrQLenPdf::25 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 38488 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 27115.229266 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 2500.122459 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 33119.773163 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::64-127 5498 14.28% 14.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-191 3288 8.54% 22.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::192-255 2221 5.77% 28.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-319 1687 4.38% 32.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::320-383 1187 3.08% 36.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-447 1056 2.74% 38.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::448-511 814 2.11% 40.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-575 739 1.92% 42.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::576-639 550 1.43% 44.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-703 512 1.33% 45.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::704-767 421 1.09% 46.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-831 397 1.03% 47.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::832-895 314 0.82% 48.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-959 250 0.65% 49.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::960-1023 198 0.51% 49.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1087 236 0.61% 50.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1088-1151 133 0.35% 50.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1152-1215 138 0.36% 51.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1216-1279 98 0.25% 51.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1280-1343 109 0.28% 51.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1344-1407 78 0.20% 51.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1408-1471 154 0.40% 52.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1472-1535 969 2.52% 54.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1536-1599 195 0.51% 55.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1600-1663 143 0.37% 55.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1664-1727 120 0.31% 55.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1728-1791 89 0.23% 56.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1792-1855 73 0.19% 56.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1856-1919 63 0.16% 56.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1920-1983 55 0.14% 56.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1984-2047 51 0.13% 56.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2048-2111 51 0.13% 56.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2112-2175 31 0.08% 56.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2176-2239 29 0.08% 57.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2240-2303 27 0.07% 57.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2304-2367 16 0.04% 57.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2368-2431 18 0.05% 57.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2432-2495 16 0.04% 57.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2496-2559 22 0.06% 57.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2560-2623 11 0.03% 57.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2624-2687 16 0.04% 57.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2688-2751 9 0.02% 57.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2752-2815 14 0.04% 57.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2816-2879 16 0.04% 57.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2880-2943 11 0.03% 57.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2944-3007 14 0.04% 57.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3008-3071 8 0.02% 57.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3072-3135 19 0.05% 57.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3136-3199 9 0.02% 57.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3200-3263 4 0.01% 57.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3264-3327 13 0.03% 57.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3328-3391 10 0.03% 57.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3392-3455 6 0.02% 57.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3456-3519 7 0.02% 57.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3520-3583 3 0.01% 57.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3584-3647 6 0.02% 57.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3648-3711 13 0.03% 57.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3712-3775 10 0.03% 57.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3776-3839 5 0.01% 57.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3840-3903 10 0.03% 57.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3904-3967 3 0.01% 57.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3968-4031 7 0.02% 57.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4032-4095 8 0.02% 57.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4096-4159 40 0.10% 57.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4160-4223 2 0.01% 57.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4224-4287 4 0.01% 58.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4288-4351 3 0.01% 58.01% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4352-4415 6 0.02% 58.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4416-4479 4 0.01% 58.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4480-4543 3 0.01% 58.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4544-4607 5 0.01% 58.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4608-4671 6 0.02% 58.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4672-4735 1 0.00% 58.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4736-4799 1 0.00% 58.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4800-4863 3 0.01% 58.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4864-4927 9 0.02% 58.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4928-4991 2 0.01% 58.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4992-5055 3 0.01% 58.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5056-5119 2 0.01% 58.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5120-5183 9 0.02% 58.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5184-5247 2 0.01% 58.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5248-5311 5 0.01% 58.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5312-5375 4 0.01% 58.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5376-5439 3 0.01% 58.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5440-5503 5 0.01% 58.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5504-5567 4 0.01% 58.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5568-5631 4 0.01% 58.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5632-5695 6 0.02% 58.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5696-5759 2 0.01% 58.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5888-5951 4 0.01% 58.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5952-6015 1 0.00% 58.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6016-6079 2 0.01% 58.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6080-6143 1 0.00% 58.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6144-6207 184 0.48% 58.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6208-6271 2 0.01% 58.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6272-6335 1 0.00% 58.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6400-6463 2 0.01% 58.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6464-6527 3 0.01% 58.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6528-6591 4 0.01% 58.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6592-6655 1 0.00% 58.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6656-6719 2 0.01% 58.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6720-6783 1 0.00% 58.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6784-6847 15 0.04% 58.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6848-6911 3 0.01% 58.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6912-6975 1 0.00% 58.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6976-7039 2 0.01% 58.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7040-7103 3 0.01% 58.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7168-7231 4 0.01% 58.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7232-7295 4 0.01% 58.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7296-7359 1 0.00% 58.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7424-7487 2 0.01% 58.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7488-7551 3 0.01% 58.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7552-7615 5 0.01% 58.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7616-7679 3 0.01% 58.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7680-7743 6 0.02% 58.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7744-7807 4 0.01% 58.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7808-7871 4 0.01% 58.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7872-7935 4 0.01% 58.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7936-7999 1 0.00% 58.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8000-8063 1 0.00% 58.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8064-8127 6 0.02% 58.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8128-8191 3 0.01% 58.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8192-8255 327 0.85% 59.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8256-8319 1 0.00% 59.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8576-8639 1 0.00% 59.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8704-8767 1 0.00% 59.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8832-8895 1 0.00% 59.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9216-9279 5 0.01% 59.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9728-9791 1 0.00% 59.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9856-9919 1 0.00% 59.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9984-10047 1 0.00% 59.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10112-10175 2 0.01% 59.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10240-10303 20 0.05% 59.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10624-10687 1 0.00% 59.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11008-11071 1 0.00% 59.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12032-12095 1 0.00% 59.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12288-12351 2 0.01% 59.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12544-12607 1 0.00% 59.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12672-12735 1 0.00% 59.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12800-12863 1 0.00% 59.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13056-13119 1 0.00% 59.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13696-13759 1 0.00% 59.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13824-13887 1 0.00% 59.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14080-14143 2 0.01% 59.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14336-14399 3 0.01% 59.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15360-15423 4 0.01% 59.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15616-15679 1 0.00% 59.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15680-15743 1 0.00% 59.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16128-16191 1 0.00% 59.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16384-16447 1 0.00% 59.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::17024-17087 1 0.00% 59.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::17152-17215 3 0.01% 59.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::17920-17983 1 0.00% 59.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::18048-18111 1 0.00% 59.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::18176-18239 1 0.00% 60.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::18304-18367 1 0.00% 60.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::18432-18495 3 0.01% 60.01% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::18688-18751 1 0.00% 60.01% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::19200-19263 1 0.00% 60.01% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::19456-19519 1 0.00% 60.01% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::19712-19775 2 0.01% 60.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::19968-20031 1 0.00% 60.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::20096-20159 1 0.00% 60.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::20288-20351 1 0.00% 60.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::20480-20543 1 0.00% 60.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::20736-20799 1 0.00% 60.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::21248-21311 1 0.00% 60.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::21504-21567 1 0.00% 60.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::21760-21823 1 0.00% 60.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::22016-22079 1 0.00% 60.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::22272-22335 2 0.01% 60.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::22400-22463 1 0.00% 60.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::22528-22591 3 0.01% 60.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::23040-23103 2 0.01% 60.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::23296-23359 1 0.00% 60.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::23424-23487 1 0.00% 60.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::23552-23615 2 0.01% 60.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::23808-23871 1 0.00% 60.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::24064-24127 1 0.00% 60.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::24576-24639 2 0.01% 60.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::24832-24895 2 0.01% 60.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::25088-25151 2 0.01% 60.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::25216-25279 1 0.00% 60.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::25344-25407 2 0.01% 60.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::25600-25663 1 0.00% 60.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::25664-25727 1 0.00% 60.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::25792-25855 1 0.00% 60.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::26112-26175 1 0.00% 60.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::26240-26303 1 0.00% 60.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::26368-26431 2 0.01% 60.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::26624-26687 1 0.00% 60.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::26880-26943 2 0.01% 60.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::27392-27455 1 0.00% 60.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::27648-27711 3 0.01% 60.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::28672-28735 2 0.01% 60.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::28928-28991 2 0.01% 60.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::29184-29247 1 0.00% 60.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::29312-29375 1 0.00% 60.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::29440-29503 1 0.00% 60.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::29632-29695 1 0.00% 60.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::29696-29759 2 0.01% 60.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::30272-30335 1 0.00% 60.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::30464-30527 1 0.00% 60.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::30720-30783 4 0.01% 60.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::30848-30911 1 0.00% 60.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::31424-31487 1 0.00% 60.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::31488-31551 1 0.00% 60.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::31744-31807 3 0.01% 60.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::32256-32319 1 0.00% 60.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::32512-32575 1 0.00% 60.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::32768-32831 2 0.01% 60.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::33024-33087 16 0.04% 60.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::33088-33151 1 0.00% 60.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::33152-33215 24 0.06% 60.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::33280-33343 16 0.04% 60.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::33792-33855 1 0.00% 60.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::34816-34879 1 0.00% 60.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::35072-35135 1 0.00% 60.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::36864-36927 1 0.00% 60.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::37888-37951 1 0.00% 60.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::39168-39231 1 0.00% 60.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::39424-39487 1 0.00% 60.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::40704-40767 1 0.00% 60.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::40960-41023 1 0.00% 60.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::41984-42047 2 0.01% 60.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::42496-42559 1 0.00% 60.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::42752-42815 1 0.00% 60.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::43008-43071 1 0.00% 60.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::43264-43327 1 0.00% 60.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::44032-44095 1 0.00% 60.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::44992-45055 1 0.00% 60.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::47104-47167 2 0.01% 60.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::47616-47679 1 0.00% 60.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::48128-48191 1 0.00% 60.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::49152-49215 1 0.00% 60.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::49920-49983 1 0.00% 60.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::50176-50239 1 0.00% 60.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::50432-50495 1 0.00% 60.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::51200-51263 2 0.01% 60.42% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::26624-26687 1 0.00% 60.56% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::26880-26943 2 0.01% 60.57% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::27392-27455 2 0.01% 60.57% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::27648-27711 4 0.01% 60.58% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::28160-28223 2 0.01% 60.59% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::28416-28479 1 0.00% 60.59% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::28672-28735 2 0.01% 60.60% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::28800-28863 1 0.00% 60.60% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::29184-29247 3 0.01% 60.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::29440-29503 1 0.00% 60.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::29696-29759 3 0.01% 60.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::29952-30015 1 0.00% 60.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::30208-30271 1 0.00% 60.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::30336-30399 1 0.00% 60.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::30720-30783 1 0.00% 60.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::30976-31039 1 0.00% 60.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::31104-31167 1 0.00% 60.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::31168-31231 1 0.00% 60.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::31232-31295 2 0.01% 60.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::31360-31423 1 0.00% 60.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::31488-31551 2 0.01% 60.65% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::31680-31743 1 0.00% 60.65% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::31744-31807 6 0.02% 60.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::32000-32063 1 0.00% 60.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::32256-32319 1 0.00% 60.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::33024-33087 16 0.04% 60.72% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::33152-33215 19 0.05% 60.76% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::33280-33343 23 0.06% 60.83% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::33536-33599 1 0.00% 60.83% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::34816-34879 1 0.00% 60.83% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::35840-35903 1 0.00% 60.83% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::36352-36415 2 0.01% 60.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::36864-36927 1 0.00% 60.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::37888-37951 1 0.00% 60.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::40192-40255 1 0.00% 60.85% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::41216-41279 2 0.01% 60.85% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::41728-41791 1 0.00% 60.85% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::41984-42047 1 0.00% 60.86% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::43264-43327 1 0.00% 60.86% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::46080-46143 1 0.00% 60.86% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::46336-46399 1 0.00% 60.86% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::46528-46591 1 0.00% 60.87% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::47104-47167 3 0.01% 60.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::47872-47935 1 0.00% 60.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::48128-48191 1 0.00% 60.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::48384-48447 1 0.00% 60.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::48896-48959 1 0.00% 60.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::49664-49727 1 0.00% 60.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::51200-51263 2 0.01% 60.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::52224-52287 2 0.01% 60.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::56320-56383 1 0.00% 60.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::56576-56639 1 0.00% 60.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::57344-57407 1 0.00% 60.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::57600-57663 1 0.00% 60.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::58368-58431 2 0.01% 60.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::60416-60479 1 0.00% 60.92% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::60672-60735 1 0.00% 60.92% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::61184-61247 1 0.00% 60.92% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::61696-61759 1 0.00% 60.93% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::63488-63551 1 0.00% 60.93% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::65024-65087 190 0.50% 61.43% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::65088-65151 6 0.02% 61.44% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::65216-65279 6 0.02% 61.46% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::65280-65343 1 0.00% 61.46% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::65472-65535 1 0.00% 61.46% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::65536-65599 14664 38.52% 99.98% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::67392-67455 1 0.00% 99.99% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::69760-69823 1 0.00% 99.99% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::71744-71807 2 0.01% 99.99% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::73984-74047 1 0.00% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::420352-420415 1 0.00% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 38488 # Bytes accessed per row activation
-system.physmem.totQLat 303199099750 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 396944112250 # Sum of mem lat for all requests
-system.physmem.totBusLat 77472355000 # Total cycles spent in databus access
-system.physmem.totBankLat 16272657500 # Total cycles spent in bank access
-system.physmem.avgQLat 19568.21 # Average queueing delay per request
-system.physmem.avgBankLat 1050.22 # Average bank access latency per request
+system.physmem.bytesPerActivate::total 38068 # Bytes accessed per row activation
+system.physmem.totQLat 296768605750 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 390592239500 # Sum of mem lat for all requests
+system.physmem.totBusLat 77465575000 # Total cycles spent in databus access
+system.physmem.totBankLat 16358058750 # Total cycles spent in bank access
+system.physmem.avgQLat 19154.87 # Average queueing delay per request
+system.physmem.avgBankLat 1055.83 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 25618.44 # Average memory access latency
+system.physmem.avgMemAccLat 25210.70 # Average memory access latency
system.physmem.avgRdBW 379.12 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 19.87 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 50.65 # Average consumed read bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 3.12 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.15 # Average read queue length over time
-system.physmem.avgWrQLen 10.84 # Average write queue length over time
-system.physmem.readRowHits 15469547 # Number of row buffer hits during reads
-system.physmem.writeRowHits 798405 # Number of row buffer hits during writes
+system.physmem.avgWrQLen 13.76 # Average write queue length over time
+system.physmem.readRowHits 15468398 # Number of row buffer hits during reads
+system.physmem.writeRowHits 93875 # Number of row buffer hits during writes
system.physmem.readRowHitRate 99.84 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 98.33 # Row buffer hit rate for writes
-system.physmem.avgGap 160407.65 # Average gap between requests
+system.physmem.writeRowHitRate 11.56 # Row buffer hit rate for writes
+system.physmem.avgGap 160406.60 # Average gap between requests
system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory
system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput 54136540 # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq 16546595 # Transaction distribution
-system.membus.trans_dist::ReadResp 16546595 # Transaction distribution
+system.membus.throughput 54136917 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 16546596 # Transaction distribution
+system.membus.trans_dist::ReadResp 16546596 # Transaction distribution
system.membus.trans_dist::WriteReq 763368 # Transaction distribution
system.membus.trans_dist::WriteResp 763368 # Transaction distribution
system.membus.trans_dist::Writeback 57971 # Transaction distribution
system.membus.trans_dist::ReadExResp 132250 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2382988 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1893729 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3850 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4280579 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1893731 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4280581 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30670848 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 30670848 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::system.bridge.slave 2382988 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::system.physmem.port 32564577 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::system.realview.gic.pio 3850 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 34951427 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 34951429 # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390393 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16525240 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7700 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 18923357 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16525304 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 18923421 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 122683392 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::total 122683392 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::system.bridge.slave 2390393 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::system.physmem.port 139208632 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::system.realview.gic.pio 7700 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 141606749 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 141606749 # Total data (bytes)
+system.membus.tot_pkt_size::total 141606813 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 141606813 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy 1206151500 # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy 1206151000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer1.occupancy 5000 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 17903854000 # Layer occupancy (ticks)
-system.membus.reqLayer2.utilization 0.7 # Layer utilization (%)
-system.membus.reqLayer3.occupancy 3613000 # Layer occupancy (ticks)
-system.membus.reqLayer3.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer5.occupancy 1000 # Layer occupancy (ticks)
-system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer1.occupancy 4944443675 # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy 3613000 # Layer occupancy (ticks)
+system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
+system.membus.reqLayer4.occupancy 1000 # Layer occupancy (ticks)
+system.membus.reqLayer4.utilization 0.0 # Layer utilization (%)
+system.membus.reqLayer6.occupancy 17904160000 # Layer occupancy (ticks)
+system.membus.reqLayer6.utilization 0.7 # Layer utilization (%)
+system.membus.respLayer1.occupancy 4944878700 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
-system.membus.respLayer2.occupancy 34633310000 # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy 34615555500 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 1.3 # Layer utilization (%)
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
-system.iobus.throughput 47815955 # Throughput (bytes/s)
+system.iobus.throughput 47816267 # Throughput (bytes/s)
system.iobus.trans_dist::ReadReq 16518752 # Transaction distribution
system.iobus.trans_dist::ReadResp 16518752 # Transaction distribution
system.iobus.trans_dist::WriteReq 8166 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::total 2382988 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30670848 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.clcd.dma::total 30670848 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.realview_io.pio 7946 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.timer0.pio 534 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.timer1.pio 1042 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.iocache.cpu_side 30670848 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total 33053836 # Packet count per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15892 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::total 2390393 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 122683392 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.realview.clcd.dma::total 122683392 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.realview_io.pio 15892 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.timer0.pio 1068 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.timer1.pio 2084 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.iocache.cpu_side 122683392 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::total 125073785 # Cumulative packet size per connected master and slave (bytes)
system.iobus.data_through_bus 125073785 # Total data (bytes)
system.iobus.reqLayer0.occupancy 21043000 # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%)
system.iobus.respLayer0.occupancy 2374822000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.1 # Layer utilization (%)
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system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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-system.cpu.dcache.overall_mshr_uncacheable_latency::total 208285933940 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027166 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027166 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024477 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024477 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_misses::cpu.data 618715 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 618715 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 618715 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 618715 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4642816500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 4642816500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10058410735 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 10058410735 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 135673500 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 135673500 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14701227235 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 14701227235 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14701227235 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 14701227235 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182050836250 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182050836250 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26234094465 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26234094465 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 208284930715 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total 208284930715 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027167 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027167 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024476 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024476 # mshr miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.046408 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.046408 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026010 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.026010 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026010 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.026010 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12605.239519 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12605.239519 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40200.175782 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40200.175782 # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11897.065217 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11897.065217 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23765.410594 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 23765.410594 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23765.410594 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 23765.410594 # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12599.264856 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12599.264856 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40198.911081 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40198.911081 # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11797.695652 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11797.695652 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23760.903219 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 23760.903219 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23760.903219 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 23760.903219 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.toL2Bus.throughput 53012095 # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq 2455185 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 2455185 # Transaction distribution
+system.cpu.toL2Bus.throughput 53011951 # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq 2455175 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 2455175 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq 763368 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp 763368 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback 595786 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 595785 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq 2898 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp 2898 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 247327 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 247327 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1725213 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 5751160 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma 12463 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma 27463 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count 7516299 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 54757044 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 83692777 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma 14148 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma 34900 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size 138498869 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus 138498869 # Total data (bytes)
+system.cpu.toL2Bus.trans_dist::ReadExReq 247318 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 247318 # Transaction distribution
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+system.cpu.toL2Bus.pkt_count::total 7516260 # Packet count per connected master and slave (bytes)
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+system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 14148 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 34900 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total 138497589 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus 138497589 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 166632 # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy 3009752500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.occupancy 3009741500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 1296058500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy 1296026750 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 2542947575 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy 2542955300 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
system.cpu.toL2Bus.respLayer2.occupancy 8926500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer3.occupancy 18739250 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.iocache.tags.replacements 0 # number of replacements
-system.iocache.tags.tagsinuse 0 # Cycle average of tags in use
-system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks.
-system.iocache.tags.avg_refs nan # Average number of references to valid blocks.
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system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
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-system.iocache.ReadReq_mshr_uncacheable_latency::total 1466807214000 # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1466807214000 # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 1466807214000 # number of overall MSHR uncacheable cycles
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+system.iocache.overall_mshr_uncacheable_latency::total 1460469685500 # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
sim_ticks 2332810264000 # Number of ticks simulated
final_tick 2332810264000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 662335 # Simulator instruction rate (inst/s)
-host_op_rate 851722 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 25577480180 # Simulator tick rate (ticks/s)
-host_mem_usage 396424 # Number of bytes of host memory used
-host_seconds 91.21 # Real time elapsed on the host
+host_inst_rate 691261 # Simulator instruction rate (inst/s)
+host_op_rate 888919 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 26694508777 # Simulator tick rate (ticks/s)
+host_mem_usage 395580 # Number of bytes of host memory used
+host_seconds 87.39 # Real time elapsed on the host
sim_insts 60408639 # Number of instructions simulated
sim_ops 77681819 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::realview.clcd 111673344 # Number of bytes read from this memory
system.physmem.bw_total::cpu1.inst 91056 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 1794913 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 54942145 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 0 # Total number of read requests seen
-system.physmem.writeReqs 0 # Total number of write requests seen
-system.physmem.cpureqs 0 # Reqs generatd by CPU via cache - shady
+system.physmem.readReqs 0 # Total number of read requests accepted by DRAM controller
+system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller
+system.physmem.readBursts 0 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
+system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
system.physmem.bytesRead 0 # Total number of bytes read from memory
system.physmem.bytesWritten 0 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 0 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
+system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis
system.membus.throughput 55969561 # Throughput (bytes/s)
system.membus.data_through_bus 130566366 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
-system.l2c.tags.replacements 62242 # number of replacements
-system.l2c.tags.tagsinuse 50006.300222 # Cycle average of tags in use
-system.l2c.tags.total_refs 1678485 # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs 127627 # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs 13.151488 # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle 2316901489000 # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks 36900.571453 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.993823 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker 0.993931 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst 4917.298419 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data 3152.525311 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst 2097.421525 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data 2936.495759 # Average occupied blocks per requestor
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+system.l2c.tags.avg_refs 13.151488 # Average number of references to valid blocks.
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+system.l2c.tags.occ_blocks::cpu0.data 3152.525311 # Average occupied blocks per requestor
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system.l2c.ReadReq_hits::cpu0.dtb.walker 9005 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker 3277 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.inst 473134 # number of ReadReq hits
system.cpu0.num_mem_refs 15013057 # number of memory refs
system.cpu0.num_load_insts 8304661 # Number of load instructions
system.cpu0.num_store_insts 6708396 # Number of store instructions
-system.cpu0.num_idle_cycles 186586201.060505 # Number of idle cycles
-system.cpu0.num_busy_cycles 4447003463.939495 # Number of busy cycles
-system.cpu0.not_idle_fraction 0.959732 # Percentage of non-idle cycles
-system.cpu0.idle_fraction 0.040268 # Percentage of idle cycles
+system.cpu0.num_idle_cycles 4555625120.147407 # Number of idle cycles
+system.cpu0.num_busy_cycles 77964544.852593 # Number of busy cycles
+system.cpu0.not_idle_fraction 0.016826 # Percentage of non-idle cycles
+system.cpu0.idle_fraction 0.983174 # Percentage of idle cycles
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
system.cpu0.kern.inst.quiesce 82795 # number of quiesce instructions executed
-system.cpu0.icache.tags.replacements 850590 # number of replacements
-system.cpu0.icache.tags.tagsinuse 511.678593 # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs 60583498 # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs 851102 # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs 71.182418 # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle 5709383000 # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.replacements 850590 # number of replacements
+system.cpu0.icache.tags.tagsinuse 511.678593 # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs 60583498 # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs 851102 # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs 71.182418 # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle 5709383000 # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst 444.510252 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu1.inst 67.168341 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.868184 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu1.inst 0.131188 # Average percentage of cache occupancy
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system.cpu0.icache.ReadReq_hits::cpu0.inst 32064735 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst 28518763 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 60583498 # number of ReadReq hits
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu0.dcache.tags.occ_blocks::cpu0.data 451.298938 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu1.data 60.698093 # Average occupied blocks per requestor
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system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
sim_ticks 5112102211000 # Number of ticks simulated
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system.physmem.bw_total::total 4527271 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bytesRead 0 # Total number of bytes read from memory
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system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis
system.membus.throughput 9632725 # Throughput (bytes/s)
system.membus.data_through_bus 49243475 # Total data (bytes)
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system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.042449 # Average occupied blocks per requestor
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system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses
system.cpu.idle_fraction 0.955626 # Percentage of idle cycles
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system.cpu.icache.demand_hits::cpu.inst 243495984 # number of demand (read+write) hits
system.cpu.icache.cache_copies 0 # number of cache copies performed
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system.cpu.dcache.ReadReq_hits::total 12074025 # number of ReadReq hits
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system.cpu.toL2Bus.data_through_bus 279212819 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 25472 # Total snoop data (bytes)
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system.cpu.l2cache.tags.occ_blocks::writebacks 51906.795355 # Average occupied blocks per requestor
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sim_ticks 5196173457000 # Number of ticks simulated
final_tick 5196173457000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 128277551 # Number of instructions simulated
sim_ops 247287193 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::pc.south_bridge.ide 2879808 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 159034 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 1730209 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 4005815 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bytesRead 12697024 # Total number of bytes read from memory
system.physmem.bytesWritten 8117888 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 12697024 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 8117888 # bytesWritten derated as per pkt->getSize()
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system.physmem.neitherReadNorWrite 1638 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 12755 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 12192 # Track reads on a per bank basis
system.membus.trans_dist::MessageResp 1655 # Transaction distribution
system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3310 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.apicbridge.master::total 3310 # Packet count per connected master and slave (bytes)
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system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 480072 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 710114 # Packet count per connected master and slave (bytes)
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system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1581576 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 139223 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 139223 # Packet count per connected master and slave (bytes)
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system.membus.pkt_count::total 1724109 # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6620 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.apicbridge.master::total 6620 # Cumulative packet size per connected master and slave (bytes)
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system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 246316 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1420225 # Cumulative packet size per connected master and slave (bytes)
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system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 16614957 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5866496 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::total 5866496 # Cumulative packet size per connected master and slave (bytes)
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system.membus.tot_pkt_size::total 22488073 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 22488073 # Total data (bytes)
system.membus.snoop_data_through_bus 205568 # Total snoop data (bytes)
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system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
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system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
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system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
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system.membus.reqLayer3.utilization 0.0 # Layer utilization (%)
system.membus.respLayer0.occupancy 1655000 # Layer occupancy (ticks)
system.membus.respLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95118 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3310 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3310 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.apicbridge.slave 3310 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.pc.south_bridge.ide.pio 11088 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.pc.south_bridge.speaker.pio 436684 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.pc.i_dont_exist.pio 170 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.pc.com_1.pio 26980 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.iocache.cpu_side 95118 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total 578500 # Packet count per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 3027256 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6620 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 6620 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.apicbridge.slave 6620 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.pc.south_bridge.ide.pio 6686 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.pc.south_bridge.speaker.pio 218342 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.pc.i_dont_exist.pio 85 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.pc.com_1.pio 13490 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.iocache.cpu_side 3027256 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::total 3280192 # Cumulative packet size per connected master and slave (bytes)
system.iobus.data_through_bus 3280192 # Total data (bytes)
system.iobus.reqLayer0.occupancy 3949164 # Layer occupancy (ticks)
system.cpu.toL2Bus.trans_dist::UpgradeResp 2190 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 359066 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 312361 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1584265 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 5972620 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side 8122 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side 18187 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count 7583194 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 50696064 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 203753837 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb_walker_cache.mem_side 242368 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb_walker_cache.mem_side 606720 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size 255298989 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1584265 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5972620 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 8122 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 18187 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 7583194 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50696064 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 203753837 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 242368 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 606720 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total 255298989 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus 255278509 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 309568 # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy 3830199000 # Layer occupancy (ticks)
sim_ticks 25046000 # Number of ticks simulated
final_tick 25046000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 25238 # Simulator instruction rate (inst/s)
-host_op_rate 25236 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 98905790 # Simulator tick rate (ticks/s)
-host_mem_usage 225424 # Number of bytes of host memory used
-host_seconds 0.25 # Real time elapsed on the host
+host_inst_rate 22373 # Simulator instruction rate (inst/s)
+host_op_rate 22372 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 87684145 # Simulator tick rate (ticks/s)
+host_mem_usage 225308 # Number of bytes of host memory used
+host_seconds 0.29 # Real time elapsed on the host
sim_insts 6390 # Number of instructions simulated
sim_ops 6390 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 19200 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 766589475 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 429290106 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 1195879582 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 469 # Total number of read requests seen
-system.physmem.writeReqs 0 # Total number of write requests seen
-system.physmem.cpureqs 469 # Reqs generatd by CPU via cache - shady
+system.physmem.readReqs 469 # Total number of read requests accepted by DRAM controller
+system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller
+system.physmem.readBursts 469 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
+system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
system.physmem.bytesRead 29952 # Total number of bytes read from memory
system.physmem.bytesWritten 0 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 29952 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
+system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 65 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 29 # Track reads on a per bank basis
system.membus.trans_dist::ReadResp 395 # Transaction distribution
system.membus.trans_dist::ReadExReq 73 # Transaction distribution
system.membus.trans_dist::ReadExResp 73 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side 937 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count 937 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 29952 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size 29952 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 937 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 937 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 29952 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total 29952 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 29952 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.membus.reqLayer0.occupancy 559000 # Layer occupancy (ticks)
system.cpu.stage4.idleCycles 45635 # Number of cycles 0 instructions are processed.
system.cpu.stage4.runCycles 4458 # Number of cycles 1+ instructions are processed.
system.cpu.stage4.utilization 8.899447 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.icache.tags.replacements 0 # number of replacements
-system.cpu.icache.tags.tagsinuse 141.294375 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 560 # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs 301 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 1.860465 # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 141.294375 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.068991 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.068991 # Average percentage of cache occupancy
+system.cpu.icache.tags.replacements 0 # number of replacements
+system.cpu.icache.tags.tagsinuse 141.294375 # Cycle average of tags in use
+system.cpu.icache.tags.total_refs 560 # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs 301 # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs 1.860465 # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst 141.294375 # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst 0.068991 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total 0.068991 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 560 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 560 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 560 # number of demand (read+write) hits
system.cpu.toL2Bus.trans_dist::ReadResp 396 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 73 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 603 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 336 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count 939 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 19264 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 10752 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size 30016 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 603 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 336 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 939 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19264 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10752 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total 30016 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus 30016 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy 235000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 2.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 278750 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%)
-system.cpu.l2cache.tags.replacements 0 # number of replacements
-system.cpu.l2cache.tags.tagsinuse 197.784355 # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs 395 # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs 0.002532 # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 141.343624 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 56.440731 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.replacements 0 # number of replacements
+system.cpu.l2cache.tags.tagsinuse 197.784355 # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs 395 # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs 0.002532 # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 141.343624 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 56.440731 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004313 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.001722 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total 0.006036 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total 0.006036 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits
system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58120.535714 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56425.373134 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements 0 # number of replacements
-system.cpu.dcache.tags.tagsinuse 103.103023 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 1601 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 168 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 9.529762 # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 103.103023 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.025172 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.025172 # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements 0 # number of replacements
+system.cpu.dcache.tags.tagsinuse 103.103023 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 1601 # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs 168 # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 9.529762 # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data 103.103023 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data 0.025172 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total 0.025172 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 1086 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 1086 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 515 # number of WriteReq hits
sim_ticks 20671000 # Number of ticks simulated
final_tick 20671000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 25591 # Simulator instruction rate (inst/s)
-host_op_rate 25589 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 83008053 # Simulator tick rate (ticks/s)
-host_mem_usage 227468 # Number of bytes of host memory used
-host_seconds 0.25 # Real time elapsed on the host
+host_inst_rate 24570 # Simulator instruction rate (inst/s)
+host_op_rate 24568 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 79697022 # Simulator tick rate (ticks/s)
+host_mem_usage 227340 # Number of bytes of host memory used
+host_seconds 0.26 # Real time elapsed on the host
sim_insts 6372 # Number of instructions simulated
sim_ops 6372 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 20032 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 969087127 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 538725751 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 1507812878 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 488 # Total number of read requests seen
-system.physmem.writeReqs 0 # Total number of write requests seen
-system.physmem.cpureqs 488 # Reqs generatd by CPU via cache - shady
+system.physmem.readReqs 488 # Total number of read requests accepted by DRAM controller
+system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller
+system.physmem.readBursts 488 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
+system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
system.physmem.bytesRead 31168 # Total number of bytes read from memory
system.physmem.bytesWritten 0 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 31168 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
+system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 69 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 34 # Track reads on a per bank basis
system.membus.trans_dist::ReadResp 414 # Transaction distribution
system.membus.trans_dist::ReadExReq 73 # Transaction distribution
system.membus.trans_dist::ReadExResp 73 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side 975 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count 975 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 31168 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size 31168 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 975 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 975 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 31168 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total 31168 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 31168 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.membus.reqLayer0.occupancy 619500 # Layer occupancy (ticks)
system.cpu.toL2Bus.trans_dist::ReadResp 415 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 73 # Transaction distribution
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system.cpu.toL2Bus.data_through_bus 31232 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy 244500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 2.6 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 281250 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%)
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system.cpu.icache.ReadReq_hits::cpu.inst 1898 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 1898 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 1898 # number of demand (read+write) hits
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67819.841270 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 67819.841270 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits
system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62693.965517 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57354.508197 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.ReadReq_hits::cpu.data 1730 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 1730 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 506 # number of WriteReq hits
sim_ticks 32544000 # Number of ticks simulated
final_tick 32544000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 6390 # Number of instructions simulated
sim_ops 6390 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory
system.membus.trans_dist::ReadResp 373 # Transaction distribution
system.membus.trans_dist::ReadExReq 73 # Transaction distribution
system.membus.trans_dist::ReadExResp 73 # Transaction distribution
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system.membus.data_through_bus 28544 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.membus.reqLayer0.occupancy 446000 # Layer occupancy (ticks)
system.cpu.num_busy_cycles 65088 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
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system.cpu.icache.ReadReq_hits::total 6122 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 6122 # number of demand (read+write) hits
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52849.462366 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 52849.462366 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits
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system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.ReadReq_hits::cpu.data 1088 # number of ReadReq hits
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system.cpu.dcache.WriteReq_hits::cpu.data 792 # number of WriteReq hits
system.cpu.toL2Bus.trans_dist::ReadResp 374 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 73 # Transaction distribution
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system.cpu.toL2Bus.data_through_bus 28608 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy 223500 # Layer occupancy (ticks)
sim_ticks 11933500 # Number of ticks simulated
final_tick 11933500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 492 # Simulator instruction rate (inst/s)
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sim_insts 2387 # Number of instructions simulated
sim_ops 2387 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 12032 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 1008254075 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 455859555 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 1464113630 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bytesRead 17472 # Total number of bytes read from memory
system.physmem.bytesWritten 0 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 17472 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
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system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 1 # Track reads on a per bank basis
system.membus.trans_dist::ReadResp 249 # Transaction distribution
system.membus.trans_dist::ReadExReq 24 # Transaction distribution
system.membus.trans_dist::ReadExResp 24 # Transaction distribution
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system.membus.data_through_bus 17472 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.membus.reqLayer0.occupancy 344000 # Layer occupancy (ticks)
system.cpu.toL2Bus.trans_dist::ReadResp 249 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 24 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 24 # Transaction distribution
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system.cpu.toL2Bus.data_through_bus 17472 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy 136500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 2.7 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 135500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%)
-system.cpu.icache.tags.replacements 0 # number of replacements
-system.cpu.icache.tags.tagsinuse 91.523450 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 816 # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs 188 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 4.340426 # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68062.494681 # average overall mshr miss latency
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system.membus.trans_dist::ReadExResp 27 # Transaction distribution
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system.cpu.toL2Bus.trans_dist::ReadExResp 27 # Transaction distribution
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final_tick 16494000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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system.physmem.bw_total::total 1524918152 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bytesRead 25152 # Total number of bytes read from memory
system.physmem.bytesWritten 0 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 25152 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
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system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 86 # Track reads on a per bank basis
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system.membus.trans_dist::ReadExResp 41 # Transaction distribution
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system.membus.data_through_bus 25152 # Total data (bytes)
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system.cpu.toL2Bus.trans_dist::ReadExResp 41 # Transaction distribution
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system.cpu.toL2Bus.data_through_bus 27968 # Total data (bytes)
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system.cpu.toL2Bus.reqLayer0.occupancy 219000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 2.9 # Layer utilization (%)
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system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 64263.745704 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 64263.745704 # average overall mshr miss latency
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+system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 136.957008 # Average occupied blocks per requestor
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system.cpu.l2cache.ReadReq_hits::cpu.inst 20 # number of ReadReq hits
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final_tick 16494000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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system.physmem.bw_total::total 1524918152 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bytesRead 25152 # Total number of bytes read from memory
system.physmem.bytesWritten 0 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 25152 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
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system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 86 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 46 # Track reads on a per bank basis
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system.membus.trans_dist::ReadExResp 41 # Transaction distribution
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system.membus.data_through_bus 25152 # Total data (bytes)
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system.membus.reqLayer0.occupancy 487500 # Layer occupancy (ticks)
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system.cpu.toL2Bus.trans_dist::ReadExResp 41 # Transaction distribution
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sim_ticks 25969000 # Number of ticks simulated
final_tick 25969000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
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host_seconds 0.02 # Real time elapsed on the host
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system.membus.trans_dist::ReadExResp 43 # Transaction distribution
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system.membus.data_through_bus 22400 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.membus.reqLayer0.occupancy 350000 # Layer occupancy (ticks)
system.cpu.num_busy_cycles 51938 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
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system.cpu.icache.overall_avg_mshr_miss_latency::total 50211.618257 # average overall mshr miss latency
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system.cpu.toL2Bus.trans_dist::ReadResp 339 # Transaction distribution
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system.cpu.toL2Bus.trans_dist::ReadExResp 43 # Transaction distribution
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system.cpu.toL2Bus.data_through_bus 24448 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy 191000 # Layer occupancy (ticks)
sim_ticks 24587000 # Number of ticks simulated
final_tick 24587000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
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-host_op_rate 41253 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 174426700 # Simulator tick rate (ticks/s)
-host_mem_usage 226212 # Number of bytes of host memory used
-host_seconds 0.14 # Real time elapsed on the host
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sim_insts 5814 # Number of instructions simulated
sim_ops 5814 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 20288 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 825151503 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 359214219 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 1184365722 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 455 # Total number of read requests seen
-system.physmem.writeReqs 0 # Total number of write requests seen
-system.physmem.cpureqs 455 # Reqs generatd by CPU via cache - shady
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system.physmem.bytesRead 29120 # Total number of bytes read from memory
system.physmem.bytesWritten 0 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 29120 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
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system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 28 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis
system.membus.trans_dist::ReadResp 404 # Transaction distribution
system.membus.trans_dist::ReadExReq 51 # Transaction distribution
system.membus.trans_dist::ReadExResp 51 # Transaction distribution
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-system.membus.tot_pkt_size 29120 # Cumulative packet size per connected master and slave (bytes)
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system.membus.data_through_bus 29120 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.membus.reqLayer0.occupancy 551500 # Layer occupancy (ticks)
system.cpu.stage4.idleCycles 46285 # Number of cycles 0 instructions are processed.
system.cpu.stage4.runCycles 2890 # Number of cycles 1+ instructions are processed.
system.cpu.stage4.utilization 5.876970 # Percentage of cycles stage was utilized (processing insts).
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system.cpu.icache.ReadReq_hits::cpu.inst 428 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 428 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 428 # number of demand (read+write) hits
system.cpu.toL2Bus.trans_dist::ReadResp 406 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 51 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 51 # Transaction distribution
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system.cpu.toL2Bus.data_through_bus 29248 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy 228500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 2.2 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 228000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%)
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system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004640 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.001708 # Average percentage of cache occupancy
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system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits
system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62804.347826 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59360.439560 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
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-system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.ReadReq_hits::cpu.data 1066 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 1066 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 572 # number of WriteReq hits
sim_ticks 21805500 # Number of ticks simulated
final_tick 21805500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
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-host_op_rate 79828 # Simulator op (including micro ops) rate (op/s)
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sim_insts 5156 # Number of instructions simulated
sim_ops 5156 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 21440 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 983238174 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 416775584 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 1400013758 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 477 # Total number of read requests seen
-system.physmem.writeReqs 0 # Total number of write requests seen
-system.physmem.cpureqs 477 # Reqs generatd by CPU via cache - shady
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system.physmem.bytesRead 30528 # Total number of bytes read from memory
system.physmem.bytesWritten 0 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 30528 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
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system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 30 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis
system.membus.trans_dist::ReadResp 426 # Transaction distribution
system.membus.trans_dist::ReadExReq 51 # Transaction distribution
system.membus.trans_dist::ReadExResp 51 # Transaction distribution
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system.membus.data_through_bus 30528 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.membus.reqLayer0.occupancy 605000 # Layer occupancy (ticks)
system.cpu.toL2Bus.trans_dist::ReadResp 429 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 51 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 51 # Transaction distribution
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-system.cpu.toL2Bus.pkt_count 960 # Packet count per connected master and slave (bytes)
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-system.cpu.toL2Bus.tot_pkt_size 30720 # Cumulative packet size per connected master and slave (bytes)
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system.cpu.toL2Bus.data_through_bus 30720 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy 240000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 2.6 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 230000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%)
-system.cpu.icache.tags.replacements 17 # number of replacements
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system.cpu.icache.ReadReq_hits::cpu.inst 1531 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 1531 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 1531 # number of demand (read+write) hits
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 70585.798817 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 70585.798817 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004978 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.001760 # Average percentage of cache occupancy
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system.cpu.l2cache.ReadReq_hits::cpu.inst 3 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits
system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64862.676056 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59663.522013 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements 0 # number of replacements
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-system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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-system.cpu.dcache.tags.occ_percent::total 0.022292 # Average percentage of cache occupancy
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+system.cpu.dcache.tags.tagsinuse 91.308892 # Cycle average of tags in use
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+system.cpu.dcache.tags.avg_refs 16.866197 # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.ReadReq_hits::cpu.data 1832 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 1832 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 563 # number of WriteReq hits
sim_ticks 31633000 # Number of ticks simulated
final_tick 31633000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 482351 # Simulator instruction rate (inst/s)
-host_op_rate 481309 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2613274672 # Simulator tick rate (ticks/s)
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-host_seconds 0.01 # Real time elapsed on the host
+host_inst_rate 304637 # Simulator instruction rate (inst/s)
+host_op_rate 304230 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1653175117 # Simulator tick rate (ticks/s)
+host_mem_usage 224940 # Number of bytes of host memory used
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sim_insts 5814 # Number of instructions simulated
sim_ops 5814 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 19264 # Number of bytes read from this memory
system.membus.trans_dist::ReadResp 388 # Transaction distribution
system.membus.trans_dist::ReadExReq 51 # Transaction distribution
system.membus.trans_dist::ReadExResp 51 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side 878 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count 878 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 28096 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size 28096 # Cumulative packet size per connected master and slave (bytes)
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system.membus.data_through_bus 28096 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.membus.reqLayer0.occupancy 439000 # Layer occupancy (ticks)
system.cpu.num_busy_cycles 63266 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
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system.cpu.icache.ReadReq_hits::cpu.inst 5513 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 5513 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 5513 # number of demand (read+write) hits
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52722.772277 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 52722.772277 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.l2cache.tags.occ_percent::cpu.data 0.001655 # Average percentage of cache occupancy
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system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits
system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.ReadReq_hits::cpu.data 1076 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 1076 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 874 # number of WriteReq hits
system.cpu.toL2Bus.trans_dist::ReadResp 390 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 51 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 51 # Transaction distribution
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system.cpu.toL2Bus.data_through_bus 28224 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy 220500 # Layer occupancy (ticks)
sim_ticks 18469500 # Number of ticks simulated
final_tick 18469500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
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-host_op_rate 54916 # Simulator op (including micro ops) rate (op/s)
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sim_insts 5792 # Number of instructions simulated
sim_ops 5792 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 22080 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 1195484447 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 349982403 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 1545466851 # Total bandwidth to/from this memory (bytes/s)
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-system.physmem.cpureqs 446 # Reqs generatd by CPU via cache - shady
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system.physmem.bytesRead 28544 # Total number of bytes read from memory
system.physmem.bytesWritten 0 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 28544 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
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system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 70 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 42 # Track reads on a per bank basis
system.membus.trans_dist::ReadResp 399 # Transaction distribution
system.membus.trans_dist::ReadExReq 47 # Transaction distribution
system.membus.trans_dist::ReadExResp 47 # Transaction distribution
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-system.membus.tot_pkt_size 28544 # Cumulative packet size per connected master and slave (bytes)
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system.membus.data_through_bus 28544 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.membus.reqLayer0.occupancy 565000 # Layer occupancy (ticks)
system.cpu.toL2Bus.trans_dist::ReadResp 406 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 47 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 47 # Transaction distribution
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-system.cpu.toL2Bus.pkt_count 906 # Packet count per connected master and slave (bytes)
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system.cpu.toL2Bus.data_through_bus 28992 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy 226500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 3.2 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 163000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%)
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system.cpu.icache.ReadReq_hits::cpu.inst 1372 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 1372 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 1372 # number of demand (read+write) hits
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66831.196581 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 66831.196581 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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-system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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+system.cpu.l2cache.tags.avg_refs 0.017544 # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 166.141608 # Average occupied blocks per requestor
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system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005070 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.000954 # Average percentage of cache occupancy
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system.cpu.l2cache.ReadReq_hits::cpu.inst 6 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 1 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 7 # number of ReadReq hits
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64608.910891 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56546.524664 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
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-system.cpu.dcache.tags.tagsinuse 63.117277 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 2192 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 102 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 21.490196 # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 63.117277 # Average occupied blocks per requestor
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+system.cpu.dcache.tags.tagsinuse 63.117277 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 2192 # Total number of references to valid blocks.
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+system.cpu.dcache.tags.avg_refs 21.490196 # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data 63.117277 # Average occupied blocks per requestor
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system.cpu.dcache.ReadReq_hits::cpu.data 1473 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 1473 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 719 # number of WriteReq hits
sim_ticks 20802500 # Number of ticks simulated
final_tick 20802500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 39959 # Simulator instruction rate (inst/s)
-host_op_rate 39952 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 155990706 # Simulator tick rate (ticks/s)
-host_mem_usage 232536 # Number of bytes of host memory used
-host_seconds 0.13 # Real time elapsed on the host
+host_inst_rate 86492 # Simulator instruction rate (inst/s)
+host_op_rate 86452 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 337526822 # Simulator tick rate (ticks/s)
+host_mem_usage 231936 # Number of bytes of host memory used
+host_seconds 0.06 # Real time elapsed on the host
sim_insts 5327 # Number of instructions simulated
sim_ops 5327 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 18496 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 889123903 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 412258142 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 1301382045 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 423 # Total number of read requests seen
-system.physmem.writeReqs 0 # Total number of write requests seen
-system.physmem.cpureqs 423 # Reqs generatd by CPU via cache - shady
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system.physmem.bytesRead 27072 # Total number of bytes read from memory
system.physmem.bytesWritten 0 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 27072 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
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system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 24 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 7 # Track reads on a per bank basis
system.membus.trans_dist::ReadResp 342 # Transaction distribution
system.membus.trans_dist::ReadExReq 81 # Transaction distribution
system.membus.trans_dist::ReadExResp 81 # Transaction distribution
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-system.membus.pkt_count 846 # Packet count per connected master and slave (bytes)
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-system.membus.tot_pkt_size 27072 # Cumulative packet size per connected master and slave (bytes)
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+system.membus.pkt_count::total 846 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 27072 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total 27072 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 27072 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.membus.reqLayer0.occupancy 502000 # Layer occupancy (ticks)
system.cpu.stage4.idleCycles 38449 # Number of cycles 0 instructions are processed.
system.cpu.stage4.runCycles 3157 # Number of cycles 1+ instructions are processed.
system.cpu.stage4.utilization 7.587848 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.icache.tags.replacements 0 # number of replacements
-system.cpu.icache.tags.tagsinuse 142.145699 # Cycle average of tags in use
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system.cpu.toL2Bus.trans_dist::ReadResp 345 # Transaction distribution
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system.cpu.toL2Bus.trans_dist::ReadExResp 81 # Transaction distribution
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system.cpu.toL2Bus.data_through_bus 27264 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy 213000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 2.4 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 219500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%)
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final_tick 27800000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
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host_seconds 0.01 # Real time elapsed on the host
sim_insts 5327 # Number of instructions simulated
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system.membus.trans_dist::ReadExReq 81 # Transaction distribution
system.membus.trans_dist::ReadExResp 81 # Transaction distribution
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system.membus.data_through_bus 24896 # Total data (bytes)
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system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
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system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52673.151751 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 52673.151751 # average overall mshr miss latency
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system.cpu.toL2Bus.trans_dist::ReadResp 311 # Transaction distribution
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system.cpu.toL2Bus.trans_dist::ReadExResp 81 # Transaction distribution
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system.cpu.toL2Bus.data_through_bus 25088 # Total data (bytes)
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system.cpu.toL2Bus.reqLayer0.occupancy 196000 # Layer occupancy (ticks)
sim_ticks 19639500 # Number of ticks simulated
final_tick 19639500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 5380 # Number of instructions simulated
sim_ops 9747 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 17536 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 892894422 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 462740905 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 1355635327 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bytesRead 26624 # Total number of bytes read from memory
system.physmem.bytesWritten 0 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 26624 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
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system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 34 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 1 # Track reads on a per bank basis
system.membus.trans_dist::ReadExResp 77 # Transaction distribution
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system.membus.pkt_count::total 833 # Packet count per connected master and slave (bytes)
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system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 26624 # Cumulative packet size per connected master and slave (bytes)
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system.membus.tot_pkt_size::total 26624 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 26624 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.toL2Bus.trans_dist::ReadResp 341 # Transaction distribution
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system.cpu.toL2Bus.trans_dist::ReadExResp 77 # Transaction distribution
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system.cpu.toL2Bus.data_through_bus 26752 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy 209500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 2.4 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 239750 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%)
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+system.cpu.icache.tags.tagsinuse 130.740950 # Cycle average of tags in use
+system.cpu.icache.tags.total_refs 1608 # Total number of references to valid blocks.
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+system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69288.181818 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 69288.181818 # average overall mshr miss latency
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final_tick 28358000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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system.membus.data_through_bus 23104 # Total data (bytes)
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system.cpu.toL2Bus.trans_dist::ReadExResp 79 # Transaction distribution
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system.cpu.toL2Bus.data_through_bus 23168 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy 181000 # Layer occupancy (ticks)
sim_ticks 24404000 # Number of ticks simulated
final_tick 24404000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 12745 # Number of instructions simulated
sim_ops 12745 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 39936 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 1636453040 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 917882314 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 2554335355 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bytesRead 62336 # Total number of bytes read from memory
system.physmem.bytesWritten 0 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 62336 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
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system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 83 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 153 # Track reads on a per bank basis
system.membus.trans_dist::ReadResp 828 # Transaction distribution
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system.membus.trans_dist::ReadExResp 146 # Transaction distribution
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system.membus.data_through_bus 62336 # Total data (bytes)
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system.membus.reqLayer0.occupancy 1227000 # Layer occupancy (ticks)
system.cpu.iq.FU_type_1::IprAccess 0 0.00% 100.00% # Type of FU issued
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system.cpu.iq.rate 0.446557 # Inst issue rate
system.cpu.iq.fu_busy_cnt::0 89 # FU busy when requested
system.cpu.iq.fu_busy_cnt::1 86 # FU busy when requested
system.cpu.toL2Bus.trans_dist::ReadResp 830 # Transaction distribution
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system.cpu.toL2Bus.trans_dist::ReadExResp 146 # Transaction distribution
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-system.cpu.toL2Bus.tot_pkt_size 62464 # Cumulative packet size per connected master and slave (bytes)
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system.cpu.toL2Bus.data_through_bus 62464 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy 488000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 4.2 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 566500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 2.3 # Layer utilization (%)
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system.cpu.icache.ReadReq_hits::cpu.inst 4375 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 4375 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 4375 # number of demand (read+write) hits
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75077.070288 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 75077.070288 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits
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system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64037.987680 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.ReadReq_hits::total 3469 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 1024 # number of WriteReq hits
sim_ticks 27282000 # Number of ticks simulated
final_tick 27282000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 15162 # Number of instructions simulated
sim_ops 15162 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 19072 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 699068983 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 323729932 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 1022798915 # Total bandwidth to/from this memory (bytes/s)
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-system.physmem.cpureqs 436 # Reqs generatd by CPU via cache - shady
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system.physmem.bytesRead 27904 # Total number of bytes read from memory
system.physmem.bytesWritten 0 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 27904 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
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system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 97 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 28 # Track reads on a per bank basis
system.membus.trans_dist::ReadResp 350 # Transaction distribution
system.membus.trans_dist::ReadExReq 85 # Transaction distribution
system.membus.trans_dist::ReadExResp 85 # Transaction distribution
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-system.membus.tot_pkt_size 27840 # Cumulative packet size per connected master and slave (bytes)
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system.membus.data_through_bus 27840 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.membus.reqLayer0.occupancy 519000 # Layer occupancy (ticks)
system.cpu.stage4.idleCycles 45256 # Number of cycles 0 instructions are processed.
system.cpu.stage4.runCycles 9309 # Number of cycles 1+ instructions are processed.
system.cpu.stage4.utilization 17.060387 # Percentage of cycles stage was utilized (processing insts).
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system.cpu.toL2Bus.trans_dist::ReadResp 352 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 85 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 85 # Transaction distribution
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system.cpu.toL2Bus.data_through_bus 27968 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy 219500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 1.9 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 223250 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%)
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+system.cpu.l2cache.tags.tagsinuse 199.371038 # Cycle average of tags in use
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+system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.l2cache.tags.occ_percent::cpu.data 0.000965 # Average percentage of cache occupancy
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system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits
system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57367.753623 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54586.384439 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
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+system.cpu.dcache.tags.tagsinuse 98.106033 # Cycle average of tags in use
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+system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.ReadReq_hits::cpu.data 2167 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 2167 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 1020 # number of WriteReq hits
sim_ticks 26524500 # Number of ticks simulated
final_tick 26524500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 52714 # Simulator instruction rate (inst/s)
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+host_inst_rate 95044 # Simulator instruction rate (inst/s)
+host_op_rate 95035 # Simulator op (including micro ops) rate (op/s)
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+host_mem_usage 232868 # Number of bytes of host memory used
+host_seconds 0.15 # Real time elapsed on the host
sim_insts 14436 # Number of instructions simulated
sim_ops 14436 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 21440 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 808309299 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 354690946 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 1163000245 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 482 # Total number of read requests seen
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-system.physmem.cpureqs 482 # Reqs generatd by CPU via cache - shady
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system.physmem.bytesRead 30848 # Total number of bytes read from memory
system.physmem.bytesWritten 0 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 30848 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
+system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 102 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 29 # Track reads on a per bank basis
system.membus.trans_dist::ReadResp 399 # Transaction distribution
system.membus.trans_dist::ReadExReq 83 # Transaction distribution
system.membus.trans_dist::ReadExResp 83 # Transaction distribution
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-system.membus.tot_pkt_size 30848 # Cumulative packet size per connected master and slave (bytes)
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+system.membus.tot_pkt_size::total 30848 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 30848 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.membus.reqLayer0.occupancy 608000 # Layer occupancy (ticks)
system.cpu.toL2Bus.trans_dist::ReadResp 401 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 83 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 83 # Transaction distribution
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-system.cpu.toL2Bus.tot_pkt_size 30976 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 674 # Packet count per connected master and slave (bytes)
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+system.cpu.toL2Bus.pkt_count::total 968 # Packet count per connected master and slave (bytes)
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+system.cpu.toL2Bus.tot_pkt_size::total 30976 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus 30976 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy 242000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 2.1 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 235750 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%)
-system.cpu.icache.tags.replacements 0 # number of replacements
-system.cpu.icache.tags.tagsinuse 187.665560 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 4873 # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs 337 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 14.459941 # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 187.665560 # Average occupied blocks per requestor
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+system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst 187.665560 # Average occupied blocks per requestor
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system.cpu.icache.ReadReq_hits::cpu.inst 4873 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 4873 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 4873 # number of demand (read+write) hits
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66274.480712 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 66274.480712 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements 0 # number of replacements
-system.cpu.l2cache.tags.tagsinuse 221.542392 # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs 399 # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs 0.005013 # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 187.054257 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 34.488135 # Average occupied blocks per requestor
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+system.cpu.l2cache.tags.tagsinuse 221.542392 # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks.
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+system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 187.054257 # Average occupied blocks per requestor
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system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005708 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.001052 # Average percentage of cache occupancy
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system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits
system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57909.863946 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54491.182573 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements 0 # number of replacements
-system.cpu.dcache.tags.tagsinuse 98.809715 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 4001 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 147 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 27.217687 # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 98.809715 # Average occupied blocks per requestor
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-system.cpu.dcache.tags.occ_percent::total 0.024123 # Average percentage of cache occupancy
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+system.cpu.dcache.tags.tagsinuse 98.809715 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 4001 # Total number of references to valid blocks.
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+system.cpu.dcache.tags.avg_refs 27.217687 # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data 98.809715 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data 0.024123 # Average percentage of cache occupancy
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system.cpu.dcache.ReadReq_hits::cpu.data 2962 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 2962 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 1033 # number of WriteReq hits
sim_ticks 41368000 # Number of ticks simulated
final_tick 41368000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 479032 # Simulator instruction rate (inst/s)
-host_op_rate 478642 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1304958787 # Simulator tick rate (ticks/s)
-host_mem_usage 231320 # Number of bytes of host memory used
+host_inst_rate 554996 # Simulator instruction rate (inst/s)
+host_op_rate 554737 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1512828488 # Simulator tick rate (ticks/s)
+host_mem_usage 230824 # Number of bytes of host memory used
host_seconds 0.03 # Real time elapsed on the host
sim_insts 15162 # Number of instructions simulated
sim_ops 15162 # Number of ops (including micro ops) simulated
system.membus.trans_dist::ReadResp 331 # Transaction distribution
system.membus.trans_dist::ReadExReq 85 # Transaction distribution
system.membus.trans_dist::ReadExResp 85 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side 832 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count 832 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 26624 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size 26624 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 832 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 832 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26624 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total 26624 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 26624 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.membus.reqLayer0.occupancy 416000 # Layer occupancy (ticks)
system.cpu.num_busy_cycles 82736 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.icache.tags.replacements 0 # number of replacements
-system.cpu.icache.tags.tagsinuse 153.782734 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 14928 # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs 280 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 53.314286 # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 153.782734 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.075089 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.075089 # Average percentage of cache occupancy
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+system.cpu.icache.tags.tagsinuse 153.782734 # Cycle average of tags in use
+system.cpu.icache.tags.total_refs 14928 # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs 280 # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs 53.314286 # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst 153.782734 # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst 0.075089 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total 0.075089 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 14928 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 14928 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 14928 # number of demand (read+write) hits
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52700 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 52700 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements 0 # number of replacements
-system.cpu.l2cache.tags.tagsinuse 184.632038 # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs 331 # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs 0.006042 # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 153.110886 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 31.521152 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.replacements 0 # number of replacements
+system.cpu.l2cache.tags.tagsinuse 184.632038 # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs 331 # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs 0.006042 # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 153.110886 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 31.521152 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004673 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.000962 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total 0.005635 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total 0.005635 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits
system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements 0 # number of replacements
-system.cpu.dcache.tags.tagsinuse 97.994344 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 3535 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 25.615942 # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 97.994344 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.023924 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.023924 # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements 0 # number of replacements
+system.cpu.dcache.tags.tagsinuse 97.994344 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 3535 # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 25.615942 # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data 97.994344 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data 0.023924 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total 0.023924 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 2172 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 2172 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 1357 # number of WriteReq hits
system.cpu.toL2Bus.trans_dist::ReadResp 333 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 85 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 85 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 560 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 276 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count 836 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 17920 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 8832 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size 26752 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 560 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 276 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 836 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17920 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8832 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total 26752 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus 26752 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy 209000 # Layer occupancy (ticks)
sim_ticks 110804500 # Number of ticks simulated
final_tick 110804500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 110530 # Simulator instruction rate (inst/s)
-host_op_rate 110530 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 11745373 # Simulator tick rate (ticks/s)
-host_mem_usage 249508 # Number of bytes of host memory used
-host_seconds 9.43 # Real time elapsed on the host
+host_inst_rate 170931 # Simulator instruction rate (inst/s)
+host_op_rate 170931 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 18163832 # Simulator tick rate (ticks/s)
+host_mem_usage 247816 # Number of bytes of host memory used
+host_seconds 6.10 # Real time elapsed on the host
sim_insts 1042724 # Number of instructions simulated
sim_ops 1042724 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu0.inst 22784 # Number of bytes read from this memory
system.physmem.bw_total::cpu3.inst 3465563 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3.data 7508720 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 380634361 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 660 # Total number of read requests seen
-system.physmem.writeReqs 0 # Total number of write requests seen
-system.physmem.cpureqs 736 # Reqs generatd by CPU via cache - shady
+system.physmem.readReqs 660 # Total number of read requests accepted by DRAM controller
+system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller
+system.physmem.readBursts 660 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
+system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
system.physmem.bytesRead 42176 # Total number of bytes read from memory
system.physmem.bytesWritten 0 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 42176 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
+system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q
system.physmem.neitherReadNorWrite 76 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 115 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 39 # Track reads on a per bank basis
system.membus.trans_dist::UpgradeResp 76 # Transaction distribution
system.membus.trans_dist::ReadExReq 163 # Transaction distribution
system.membus.trans_dist::ReadExResp 131 # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side 1714 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count 1714 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side 42176 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size 42176 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1714 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 1714 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 42176 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total 42176 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 42176 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.membus.reqLayer0.occupancy 929000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.8 # Layer utilization (%)
system.membus.respLayer1.occupancy 6308925 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 5.7 # Layer utilization (%)
-system.toL2Bus.throughput 1691772446 # Throughput (bytes/s)
-system.toL2Bus.trans_dist::ReadReq 2536 # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp 2535 # Transaction distribution
-system.toL2Bus.trans_dist::Writeback 1 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq 290 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp 290 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 393 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 393 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 1175 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 586 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.icache.mem_side 856 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side 365 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu2.icache.mem_side 850 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side 371 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu3.icache.mem_side 860 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side 352 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count 5415 # Packet count per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 37568 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 11136 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side 27392 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side 1536 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu2.icache.mem_side 27200 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu2.dcache.mem_side 1600 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu3.icache.mem_side 27520 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu3.dcache.mem_side 1536 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size 135488 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.data_through_bus 135488 # Total data (bytes)
-system.toL2Bus.snoop_data_through_bus 51968 # Total snoop data (bytes)
-system.toL2Bus.reqLayer0.occupancy 1623982 # Layer occupancy (ticks)
-system.toL2Bus.reqLayer0.utilization 1.5 # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy 2710248 # Layer occupancy (ticks)
-system.toL2Bus.respLayer0.utilization 2.4 # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy 1462515 # Layer occupancy (ticks)
-system.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy 1929494 # Layer occupancy (ticks)
-system.toL2Bus.respLayer2.utilization 1.7 # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy 1189495 # Layer occupancy (ticks)
-system.toL2Bus.respLayer3.utilization 1.1 # Layer utilization (%)
-system.toL2Bus.respLayer4.occupancy 1927246 # Layer occupancy (ticks)
-system.toL2Bus.respLayer4.utilization 1.7 # Layer utilization (%)
-system.toL2Bus.respLayer5.occupancy 1192987 # Layer occupancy (ticks)
-system.toL2Bus.respLayer5.utilization 1.1 # Layer utilization (%)
-system.toL2Bus.respLayer6.occupancy 1937245 # Layer occupancy (ticks)
-system.toL2Bus.respLayer6.utilization 1.7 # Layer utilization (%)
-system.toL2Bus.respLayer7.occupancy 1118007 # Layer occupancy (ticks)
-system.toL2Bus.respLayer7.utilization 1.0 # Layer utilization (%)
-system.cpu0.branchPred.lookups 82992 # Number of BP lookups
-system.cpu0.branchPred.condPredicted 80791 # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect 1218 # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups 80321 # Number of BTB lookups
-system.cpu0.branchPred.BTBHits 78273 # Number of BTB hits
-system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct 97.450231 # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS 512 # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect 132 # Number of incorrect RAS predictions.
-system.cpu0.workload.num_syscalls 89 # Number of system calls
-system.cpu0.numCycles 221610 # number of cpu cycles simulated
-system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.fetch.icacheStallCycles 17247 # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts 492529 # Number of instructions fetch has processed
-system.cpu0.fetch.Branches 82992 # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches 78785 # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles 161677 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles 3808 # Number of cycles fetch has spent squashing
-system.cpu0.fetch.BlockedCycles 13819 # Number of cycles fetch has spent blocked
-system.cpu0.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingTrapStallCycles 1570 # Number of stall cycles due to pending traps
-system.cpu0.fetch.CacheLines 5835 # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes 493 # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.rateDist::samples 196760 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean 2.503197 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev 2.215126 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0 35083 17.83% 17.83% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1 80084 40.70% 58.53% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2 578 0.29% 58.83% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3 973 0.49% 59.32% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::4 477 0.24% 59.56% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::5 76189 38.72% 98.28% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::6 571 0.29% 98.57% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::7 349 0.18% 98.75% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::8 2456 1.25% 100.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total 196760 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate 0.374496 # Number of branch fetches per cycle
-system.cpu0.fetch.rate 2.222503 # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles 17898 # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles 15432 # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles 160701 # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles 287 # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles 2442 # Number of cycles decode is squashing
-system.cpu0.decode.DecodedInsts 489694 # Number of instructions handled by decode
-system.cpu0.rename.SquashCycles 2442 # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles 18563 # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles 848 # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles 13994 # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles 160355 # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles 558 # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts 486837 # Number of instructions processed by rename
-system.cpu0.rename.LSQFullEvents 188 # Number of times rename has blocked due to LSQ full
-system.cpu0.rename.RenamedOperands 332900 # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups 970872 # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups 970872 # Number of integer rename lookups
-system.cpu0.rename.CommittedMaps 319955 # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps 12945 # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts 867 # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts 888 # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts 3605 # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads 155755 # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores 78714 # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads 75965 # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores 75781 # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded 407125 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded 911 # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued 404423 # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued 128 # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined 10748 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined 9686 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved 352 # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples 196760 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean 2.055413 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev 1.097364 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0 34065 17.31% 17.31% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1 4908 2.49% 19.81% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2 77935 39.61% 59.42% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3 77266 39.27% 98.69% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4 1571 0.80% 99.48% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5 648 0.33% 99.81% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::6 262 0.13% 99.95% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::7 89 0.05% 99.99% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::8 16 0.01% 100.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total 196760 # Number of insts issued each cycle
-system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu 57 25.91% 25.91% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult 0 0.00% 25.91% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv 0 0.00% 25.91% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd 0 0.00% 25.91% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp 0 0.00% 25.91% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt 0 0.00% 25.91% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult 0 0.00% 25.91% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv 0 0.00% 25.91% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 25.91% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd 0 0.00% 25.91% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 25.91% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu 0 0.00% 25.91% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp 0 0.00% 25.91% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt 0 0.00% 25.91% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc 0 0.00% 25.91% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult 0 0.00% 25.91% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 25.91% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift 0 0.00% 25.91% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 25.91% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 25.91% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 25.91% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 25.91% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 25.91% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 25.91% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 25.91% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 25.91% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 25.91% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.91% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 25.91% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead 51 23.18% 49.09% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite 112 50.91% 100.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu 170994 42.28% 42.28% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.28% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.28% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.28% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.28% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.28% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.28% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.28% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.28% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.28% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.28% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.28% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.28% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.28% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.28% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.28% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.28% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.28% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.28% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.28% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.28% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.28% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.28% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.28% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.28% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.28% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.28% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.28% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.28% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead 155300 38.40% 80.68% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite 78129 19.32% 100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total 404423 # Type of FU issued
-system.cpu0.iq.rate 1.824931 # Inst issue rate
-system.cpu0.iq.fu_busy_cnt 220 # FU busy when requested
-system.cpu0.iq.fu_busy_rate 0.000544 # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads 1005954 # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes 418838 # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses 402603 # Number of integer instruction queue wakeup accesses
-system.cpu0.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
-system.cpu0.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
-system.cpu0.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses 404643 # Number of integer alu accesses
-system.cpu0.iq.fp_alu_accesses 0 # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads 75498 # Number of loads that had data forwarded from stores
-system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads 2188 # Number of loads squashed
-system.cpu0.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread0.memOrderViolation 54 # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores 1424 # Number of stores squashed
-system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu0.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked 19 # Number of times an access to memory failed due to the cache being blocked
-system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles 2442 # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles 391 # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles 33 # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts 484551 # Number of instructions dispatched to IQ
-system.cpu0.iew.iewDispSquashedInsts 313 # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts 155755 # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts 78714 # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts 799 # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents 38 # Number of times the IQ has become full, causing a stall
-system.cpu0.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.memOrderViolationEvents 54 # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect 343 # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect 1106 # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts 1449 # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts 403352 # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts 154964 # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts 1071 # Number of squashed instructions skipped in execute
-system.cpu0.iew.exec_swp 0 # number of swp insts executed
-system.cpu0.iew.exec_nop 76515 # number of nop insts executed
-system.cpu0.iew.exec_refs 232993 # number of memory reference insts executed
-system.cpu0.iew.exec_branches 80132 # Number of branches executed
-system.cpu0.iew.exec_stores 78029 # Number of stores executed
-system.cpu0.iew.exec_rate 1.820098 # Inst execution rate
-system.cpu0.iew.wb_sent 402944 # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count 402603 # cumulative count of insts written-back
-system.cpu0.iew.wb_producers 238549 # num instructions producing a value
-system.cpu0.iew.wb_consumers 241004 # num instructions consuming a value
-system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu0.iew.wb_rate 1.816719 # insts written-back per cycle
-system.cpu0.iew.wb_fanout 0.989813 # average fanout of values written-back
-system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu0.commit.commitSquashedInsts 12240 # The number of squashed insts skipped by commit
-system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts 1218 # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples 194318 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean 2.430470 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev 2.136197 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0 34493 17.75% 17.75% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1 79895 41.12% 58.87% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2 2401 1.24% 60.10% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3 689 0.35% 60.46% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4 530 0.27% 60.73% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5 75316 38.76% 99.49% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6 445 0.23% 99.72% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7 242 0.12% 99.84% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8 307 0.16% 100.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total 194318 # Number of insts commited each cycle
-system.cpu0.commit.committedInsts 472284 # Number of instructions committed
-system.cpu0.commit.committedOps 472284 # Number of ops (including micro ops) committed
-system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu0.commit.refs 230857 # Number of memory references committed
-system.cpu0.commit.loads 153567 # Number of loads committed
-system.cpu0.commit.membars 84 # Number of memory barriers committed
-system.cpu0.commit.branches 79177 # Number of branches committed
-system.cpu0.commit.fp_insts 0 # Number of committed floating point instructions.
-system.cpu0.commit.int_insts 318286 # Number of committed integer instructions.
-system.cpu0.commit.function_calls 223 # Number of function calls committed.
-system.cpu0.commit.bw_lim_events 307 # number cycles where commit BW limit reached
-system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu0.rob.rob_reads 677374 # The number of ROB reads
-system.cpu0.rob.rob_writes 971507 # The number of ROB writes
-system.cpu0.timesIdled 326 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu0.idleCycles 24850 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.committedInsts 396291 # Number of Instructions Simulated
-system.cpu0.committedOps 396291 # Number of Ops (including micro ops) Simulated
-system.cpu0.committedInsts_total 396291 # Number of Instructions Simulated
-system.cpu0.cpi 0.559210 # CPI: Cycles Per Instruction
-system.cpu0.cpi_total 0.559210 # CPI: Total CPI of All Threads
-system.cpu0.ipc 1.788236 # IPC: Instructions Per Cycle
-system.cpu0.ipc_total 1.788236 # IPC: Total IPC of All Threads
-system.cpu0.int_regfile_reads 721592 # number of integer regfile reads
-system.cpu0.int_regfile_writes 325227 # number of integer regfile writes
-system.cpu0.fp_regfile_reads 192 # number of floating regfile reads
-system.cpu0.misc_regfile_reads 234817 # number of misc regfile reads
-system.cpu0.misc_regfile_writes 564 # number of misc regfile writes
-system.cpu0.icache.tags.replacements 297 # number of replacements
-system.cpu0.icache.tags.tagsinuse 241.148232 # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs 5079 # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs 587 # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs 8.652470 # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst 241.148232 # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst 0.470993 # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total 0.470993 # Average percentage of cache occupancy
-system.cpu0.icache.ReadReq_hits::cpu0.inst 5079 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total 5079 # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst 5079 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total 5079 # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst 5079 # number of overall hits
-system.cpu0.icache.overall_hits::total 5079 # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst 756 # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total 756 # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst 756 # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total 756 # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst 756 # number of overall misses
-system.cpu0.icache.overall_misses::total 756 # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 35147245 # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total 35147245 # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst 35147245 # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total 35147245 # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst 35147245 # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total 35147245 # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst 5835 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total 5835 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst 5835 # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total 5835 # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst 5835 # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total 5835 # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.129563 # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total 0.129563 # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst 0.129563 # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total 0.129563 # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst 0.129563 # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total 0.129563 # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 46491.064815 # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 46491.064815 # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 46491.064815 # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 46491.064815 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 46491.064815 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 46491.064815 # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu0.icache.fast_writes 0 # number of fast writes performed
-system.cpu0.icache.cache_copies 0 # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 168 # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total 168 # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu0.inst 168 # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total 168 # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu0.inst 168 # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total 168 # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 588 # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total 588 # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst 588 # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total 588 # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst 588 # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total 588 # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 27250252 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total 27250252 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 27250252 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total 27250252 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 27250252 # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total 27250252 # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.100771 # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.100771 # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.100771 # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total 0.100771 # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.100771 # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total 0.100771 # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 46343.965986 # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 46343.965986 # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 46343.965986 # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 46343.965986 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 46343.965986 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 46343.965986 # average overall mshr miss latency
-system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.dcache.tags.replacements 2 # number of replacements
-system.cpu0.dcache.tags.tagsinuse 141.869283 # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs 155614 # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs 170 # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs 915.376471 # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data 141.869283 # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data 0.277088 # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total 0.277088 # Average percentage of cache occupancy
-system.cpu0.dcache.ReadReq_hits::cpu0.data 78995 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total 78995 # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data 76703 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total 76703 # number of WriteReq hits
-system.cpu0.dcache.SwapReq_hits::cpu0.data 21 # number of SwapReq hits
-system.cpu0.dcache.SwapReq_hits::total 21 # number of SwapReq hits
-system.cpu0.dcache.demand_hits::cpu0.data 155698 # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total 155698 # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data 155698 # number of overall hits
-system.cpu0.dcache.overall_hits::total 155698 # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data 410 # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total 410 # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data 545 # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total 545 # number of WriteReq misses
-system.cpu0.dcache.SwapReq_misses::cpu0.data 21 # number of SwapReq misses
-system.cpu0.dcache.SwapReq_misses::total 21 # number of SwapReq misses
-system.cpu0.dcache.demand_misses::cpu0.data 955 # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total 955 # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data 955 # number of overall misses
-system.cpu0.dcache.overall_misses::total 955 # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 13319205 # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total 13319205 # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 35150505 # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total 35150505 # number of WriteReq miss cycles
-system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 418750 # number of SwapReq miss cycles
-system.cpu0.dcache.SwapReq_miss_latency::total 418750 # number of SwapReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data 48469710 # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 48469710 # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data 48469710 # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 48469710 # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data 79405 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total 79405 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data 77248 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total 77248 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses)
-system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data 156653 # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total 156653 # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data 156653 # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total 156653 # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.005163 # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total 0.005163 # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007055 # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total 0.007055 # miss rate for WriteReq accesses
-system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.500000 # miss rate for SwapReq accesses
-system.cpu0.dcache.SwapReq_miss_rate::total 0.500000 # miss rate for SwapReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006096 # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total 0.006096 # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006096 # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total 0.006096 # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 32485.865854 # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 32485.865854 # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 64496.339450 # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 64496.339450 # average WriteReq miss latency
-system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 19940.476190 # average SwapReq miss latency
-system.cpu0.dcache.SwapReq_avg_miss_latency::total 19940.476190 # average SwapReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 50753.623037 # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 50753.623037 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 50753.623037 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 50753.623037 # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs 503 # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs 21 # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs 23.952381 # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu0.dcache.fast_writes 0 # number of fast writes performed
-system.cpu0.dcache.cache_copies 0 # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks
-system.cpu0.dcache.writebacks::total 1 # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 223 # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total 223 # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 370 # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total 370 # number of WriteReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data 593 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total 593 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data 593 # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total 593 # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 187 # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total 187 # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 175 # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total 175 # number of WriteReq MSHR misses
-system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 21 # number of SwapReq MSHR misses
-system.cpu0.dcache.SwapReq_mshr_misses::total 21 # number of SwapReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data 362 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total 362 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data 362 # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total 362 # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 6285007 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6285007 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7788228 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7788228 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 375250 # number of SwapReq MSHR miss cycles
-system.cpu0.dcache.SwapReq_mshr_miss_latency::total 375250 # number of SwapReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 14073235 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total 14073235 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 14073235 # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total 14073235 # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002355 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002355 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002265 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002265 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.500000 # mshr miss rate for SwapReq accesses
-system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SwapReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002311 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total 0.002311 # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002311 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total 0.002311 # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 33609.663102 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 33609.663102 # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 44504.160000 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 44504.160000 # average WriteReq mshr miss latency
-system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 17869.047619 # average SwapReq mshr miss latency
-system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 17869.047619 # average SwapReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 38876.339779 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 38876.339779 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 38876.339779 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 38876.339779 # average overall mshr miss latency
-system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.branchPred.lookups 43495 # Number of BP lookups
-system.cpu1.branchPred.condPredicted 40766 # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect 1279 # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups 37360 # Number of BTB lookups
-system.cpu1.branchPred.BTBHits 36580 # Number of BTB hits
-system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct 97.912206 # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS 665 # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions.
-system.cpu1.numCycles 177681 # number of cpu cycles simulated
-system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.fetch.icacheStallCycles 34028 # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts 233746 # Number of instructions fetch has processed
-system.cpu1.fetch.Branches 43495 # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches 37245 # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles 88254 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles 3762 # Number of cycles fetch has spent squashing
-system.cpu1.fetch.BlockedCycles 42089 # Number of cycles fetch has spent blocked
-system.cpu1.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.NoActiveThreadStallCycles 7739 # Number of stall cycles due to no active thread to fetch from
-system.cpu1.fetch.PendingTrapStallCycles 785 # Number of stall cycles due to pending traps
-system.cpu1.fetch.CacheLines 25656 # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes 258 # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.rateDist::samples 175306 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean 1.333360 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev 1.985884 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0 87052 49.66% 49.66% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1 46435 26.49% 76.15% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2 9084 5.18% 81.33% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3 3194 1.82% 83.15% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::4 686 0.39% 83.54% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::5 23635 13.48% 97.02% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::6 1173 0.67% 97.69% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::7 772 0.44% 98.13% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::8 3275 1.87% 100.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total 175306 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate 0.244793 # Number of branch fetches per cycle
-system.cpu1.fetch.rate 1.315537 # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles 41969 # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles 35783 # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles 79597 # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles 7812 # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles 2406 # Number of cycles decode is squashing
-system.cpu1.decode.DecodedInsts 230200 # Number of instructions handled by decode
-system.cpu1.rename.SquashCycles 2406 # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles 42677 # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles 23059 # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles 11946 # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles 72053 # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles 15426 # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts 227940 # Number of instructions processed by rename
-system.cpu1.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LSQFullEvents 19 # Number of times rename has blocked due to LSQ full
-system.cpu1.rename.RenamedOperands 156532 # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups 420697 # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups 420697 # Number of integer rename lookups
-system.cpu1.rename.CommittedMaps 143693 # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps 12839 # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts 1114 # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts 1240 # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts 18203 # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads 60713 # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores 26873 # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads 30033 # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores 21821 # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded 184781 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded 9329 # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued 189617 # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued 108 # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined 10957 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined 10934 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved 690 # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples 175306 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean 1.081634 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev 1.264768 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0 84668 48.30% 48.30% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1 30997 17.68% 65.98% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2 27119 15.47% 81.45% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3 27768 15.84% 97.29% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4 3226 1.84% 99.13% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5 1160 0.66% 99.79% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::6 259 0.15% 99.94% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::7 52 0.03% 99.97% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::8 57 0.03% 100.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total 175306 # Number of insts issued each cycle
-system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu 12 4.55% 4.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult 0 0.00% 4.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntDiv 0 0.00% 4.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatAdd 0 0.00% 4.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCmp 0 0.00% 4.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCvt 0 0.00% 4.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMult 0 0.00% 4.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatDiv 0 0.00% 4.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 4.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAdd 0 0.00% 4.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 4.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAlu 0 0.00% 4.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCmp 0 0.00% 4.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCvt 0 0.00% 4.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMisc 0 0.00% 4.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMult 0 0.00% 4.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 4.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShift 0 0.00% 4.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 4.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 4.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 4.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 4.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 4.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 4.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 4.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 4.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 4.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 4.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead 42 15.91% 20.45% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite 210 79.55% 100.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu 95616 50.43% 50.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult 0 0.00% 50.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 50.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 50.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 50.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 50.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 50.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 50.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 50.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 50.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 50.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 50.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 50.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 50.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 50.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 50.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 50.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 50.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 50.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 50.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 50.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 50.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 50.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 50.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 50.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 50.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 50.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 50.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 50.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead 67820 35.77% 86.19% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite 26181 13.81% 100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total 189617 # Type of FU issued
-system.cpu1.iq.rate 1.067177 # Inst issue rate
-system.cpu1.iq.fu_busy_cnt 264 # FU busy when requested
-system.cpu1.iq.fu_busy_rate 0.001392 # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads 554912 # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes 205110 # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses 187814 # Number of integer instruction queue wakeup accesses
-system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
-system.cpu1.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
-system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses 189881 # Number of integer alu accesses
-system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads 21562 # Number of loads that had data forwarded from stores
-system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads 2474 # Number of loads squashed
-system.cpu1.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation 43 # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores 1439 # Number of stores squashed
-system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu1.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
-system.cpu1.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
-system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles 2406 # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles 736 # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles 43 # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts 225068 # Number of instructions dispatched to IQ
-system.cpu1.iew.iewDispSquashedInsts 373 # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts 60713 # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts 26873 # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts 1076 # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents 42 # Number of times the IQ has become full, causing a stall
-system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents 43 # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect 453 # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect 939 # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts 1392 # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts 188449 # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts 59619 # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts 1168 # Number of squashed instructions skipped in execute
-system.cpu1.iew.exec_swp 0 # number of swp insts executed
-system.cpu1.iew.exec_nop 30958 # number of nop insts executed
-system.cpu1.iew.exec_refs 85720 # number of memory reference insts executed
-system.cpu1.iew.exec_branches 40129 # Number of branches executed
-system.cpu1.iew.exec_stores 26101 # Number of stores executed
-system.cpu1.iew.exec_rate 1.060603 # Inst execution rate
-system.cpu1.iew.wb_sent 188127 # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count 187814 # cumulative count of insts written-back
-system.cpu1.iew.wb_producers 102456 # num instructions producing a value
-system.cpu1.iew.wb_consumers 107134 # num instructions consuming a value
-system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu1.iew.wb_rate 1.057029 # insts written-back per cycle
-system.cpu1.iew.wb_fanout 0.956335 # average fanout of values written-back
-system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu1.commit.commitSquashedInsts 12618 # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls 8639 # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts 1279 # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples 165161 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean 1.286212 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev 1.860966 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0 85256 51.62% 51.62% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1 38272 23.17% 74.79% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2 6084 3.68% 78.48% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3 9527 5.77% 84.24% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4 1571 0.95% 85.20% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5 22201 13.44% 98.64% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6 436 0.26% 98.90% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7 1006 0.61% 99.51% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8 808 0.49% 100.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total 165161 # Number of insts commited each cycle
-system.cpu1.commit.committedInsts 212432 # Number of instructions committed
-system.cpu1.commit.committedOps 212432 # Number of ops (including micro ops) committed
-system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu1.commit.refs 83673 # Number of memory references committed
-system.cpu1.commit.loads 58239 # Number of loads committed
-system.cpu1.commit.membars 7917 # Number of memory barriers committed
-system.cpu1.commit.branches 39308 # Number of branches committed
-system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions.
-system.cpu1.commit.int_insts 145097 # Number of committed integer instructions.
-system.cpu1.commit.function_calls 322 # Number of function calls committed.
-system.cpu1.commit.bw_lim_events 808 # number cycles where commit BW limit reached
-system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu1.rob.rob_reads 388816 # The number of ROB reads
-system.cpu1.rob.rob_writes 452512 # The number of ROB writes
-system.cpu1.timesIdled 218 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles 2375 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.quiesceCycles 43927 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts 174425 # Number of Instructions Simulated
-system.cpu1.committedOps 174425 # Number of Ops (including micro ops) Simulated
-system.cpu1.committedInsts_total 174425 # Number of Instructions Simulated
-system.cpu1.cpi 1.018667 # CPI: Cycles Per Instruction
-system.cpu1.cpi_total 1.018667 # CPI: Total CPI of All Threads
-system.cpu1.ipc 0.981675 # IPC: Instructions Per Cycle
-system.cpu1.ipc_total 0.981675 # IPC: Total IPC of All Threads
-system.cpu1.int_regfile_reads 315718 # number of integer regfile reads
-system.cpu1.int_regfile_writes 148477 # number of integer regfile writes
-system.cpu1.fp_regfile_writes 64 # number of floating regfile writes
-system.cpu1.misc_regfile_reads 87269 # number of misc regfile reads
-system.cpu1.misc_regfile_writes 648 # number of misc regfile writes
-system.cpu1.icache.tags.replacements 318 # number of replacements
-system.cpu1.icache.tags.tagsinuse 79.958659 # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs 25178 # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs 428 # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs 58.827103 # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst 79.958659 # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst 0.156169 # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total 0.156169 # Average percentage of cache occupancy
-system.cpu1.icache.ReadReq_hits::cpu1.inst 25178 # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total 25178 # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst 25178 # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total 25178 # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst 25178 # number of overall hits
-system.cpu1.icache.overall_hits::total 25178 # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst 478 # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total 478 # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst 478 # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total 478 # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst 478 # number of overall misses
-system.cpu1.icache.overall_misses::total 478 # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7224243 # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total 7224243 # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst 7224243 # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total 7224243 # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst 7224243 # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total 7224243 # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst 25656 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total 25656 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst 25656 # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total 25656 # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst 25656 # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total 25656 # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.018631 # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total 0.018631 # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst 0.018631 # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total 0.018631 # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst 0.018631 # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total 0.018631 # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15113.479079 # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 15113.479079 # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15113.479079 # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 15113.479079 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15113.479079 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 15113.479079 # average overall miss latency
-system.cpu1.icache.blocked_cycles::no_mshrs 26 # number of cycles access was blocked
-system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu1.icache.blocked::no_mshrs 2 # number of cycles access was blocked
-system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_mshrs 13 # average number of cycles each access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu1.icache.fast_writes 0 # number of fast writes performed
-system.cpu1.icache.cache_copies 0 # number of cache copies performed
-system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 50 # number of ReadReq MSHR hits
-system.cpu1.icache.ReadReq_mshr_hits::total 50 # number of ReadReq MSHR hits
-system.cpu1.icache.demand_mshr_hits::cpu1.inst 50 # number of demand (read+write) MSHR hits
-system.cpu1.icache.demand_mshr_hits::total 50 # number of demand (read+write) MSHR hits
-system.cpu1.icache.overall_mshr_hits::cpu1.inst 50 # number of overall MSHR hits
-system.cpu1.icache.overall_mshr_hits::total 50 # number of overall MSHR hits
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 428 # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total 428 # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst 428 # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total 428 # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst 428 # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total 428 # number of overall MSHR misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5769006 # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total 5769006 # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5769006 # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total 5769006 # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5769006 # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total 5769006 # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016682 # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.016682 # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.016682 # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total 0.016682 # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.016682 # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total 0.016682 # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13478.985981 # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13478.985981 # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13478.985981 # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total 13478.985981 # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13478.985981 # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total 13478.985981 # average overall mshr miss latency
-system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.dcache.tags.replacements 0 # number of replacements
-system.cpu1.dcache.tags.tagsinuse 24.742100 # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs 31558 # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs 1088.206897 # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data 24.742100 # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data 0.048324 # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total 0.048324 # Average percentage of cache occupancy
-system.cpu1.dcache.ReadReq_hits::cpu1.data 37722 # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total 37722 # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data 25226 # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total 25226 # number of WriteReq hits
-system.cpu1.dcache.SwapReq_hits::cpu1.data 16 # number of SwapReq hits
-system.cpu1.dcache.SwapReq_hits::total 16 # number of SwapReq hits
-system.cpu1.dcache.demand_hits::cpu1.data 62948 # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total 62948 # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data 62948 # number of overall hits
-system.cpu1.dcache.overall_hits::total 62948 # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data 319 # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total 319 # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data 132 # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total 132 # number of WriteReq misses
-system.cpu1.dcache.SwapReq_misses::cpu1.data 60 # number of SwapReq misses
-system.cpu1.dcache.SwapReq_misses::total 60 # number of SwapReq misses
-system.cpu1.dcache.demand_misses::cpu1.data 451 # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total 451 # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data 451 # number of overall misses
-system.cpu1.dcache.overall_misses::total 451 # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3919891 # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total 3919891 # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2617261 # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total 2617261 # number of WriteReq miss cycles
-system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 548504 # number of SwapReq miss cycles
-system.cpu1.dcache.SwapReq_miss_latency::total 548504 # number of SwapReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data 6537152 # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total 6537152 # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data 6537152 # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total 6537152 # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data 38041 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total 38041 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data 25358 # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total 25358 # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.SwapReq_accesses::cpu1.data 76 # number of SwapReq accesses(hits+misses)
-system.cpu1.dcache.SwapReq_accesses::total 76 # number of SwapReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data 63399 # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total 63399 # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data 63399 # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total 63399 # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.008386 # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total 0.008386 # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.005205 # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total 0.005205 # miss rate for WriteReq accesses
-system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.789474 # miss rate for SwapReq accesses
-system.cpu1.dcache.SwapReq_miss_rate::total 0.789474 # miss rate for SwapReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data 0.007114 # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total 0.007114 # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data 0.007114 # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total 0.007114 # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12288.059561 # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 12288.059561 # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 19827.734848 # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 19827.734848 # average WriteReq miss latency
-system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 9141.733333 # average SwapReq miss latency
-system.cpu1.dcache.SwapReq_avg_miss_latency::total 9141.733333 # average SwapReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14494.793792 # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 14494.793792 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14494.793792 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 14494.793792 # average overall miss latency
-system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu1.dcache.fast_writes 0 # number of fast writes performed
-system.cpu1.dcache.cache_copies 0 # number of cache copies performed
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 154 # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total 154 # number of ReadReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 32 # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::total 32 # number of WriteReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits::cpu1.data 186 # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_hits::total 186 # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.data 186 # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total 186 # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 165 # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total 165 # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 100 # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total 100 # number of WriteReq MSHR misses
-system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 60 # number of SwapReq MSHR misses
-system.cpu1.dcache.SwapReq_mshr_misses::total 60 # number of SwapReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data 265 # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total 265 # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data 265 # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total 265 # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1138770 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1138770 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1290739 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1290739 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 428496 # number of SwapReq MSHR miss cycles
-system.cpu1.dcache.SwapReq_mshr_miss_latency::total 428496 # number of SwapReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2429509 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total 2429509 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2429509 # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total 2429509 # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.004337 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.004337 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.003944 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.003944 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.789474 # mshr miss rate for SwapReq accesses
-system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.789474 # mshr miss rate for SwapReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.004180 # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total 0.004180 # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.004180 # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total 0.004180 # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 6901.636364 # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 6901.636364 # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 12907.390000 # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 12907.390000 # average WriteReq mshr miss latency
-system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 7141.600000 # average SwapReq mshr miss latency
-system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 7141.600000 # average SwapReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 9167.958491 # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 9167.958491 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 9167.958491 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 9167.958491 # average overall mshr miss latency
-system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu2.branchPred.lookups 51236 # Number of BP lookups
-system.cpu2.branchPred.condPredicted 48519 # Number of conditional branches predicted
-system.cpu2.branchPred.condIncorrect 1308 # Number of conditional branches incorrect
-system.cpu2.branchPred.BTBLookups 45052 # Number of BTB lookups
-system.cpu2.branchPred.BTBHits 44357 # Number of BTB hits
-system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu2.branchPred.BTBHitPct 98.457338 # BTB Hit Percentage
-system.cpu2.branchPred.usedRAS 684 # Number of times the RAS was used to get a target.
-system.cpu2.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions.
-system.cpu2.numCycles 177316 # number of cpu cycles simulated
-system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu2.fetch.icacheStallCycles 28846 # Number of cycles fetch is stalled on an Icache miss
-system.cpu2.fetch.Insts 286216 # Number of instructions fetch has processed
-system.cpu2.fetch.Branches 51236 # Number of branches that fetch encountered
-system.cpu2.fetch.predictedBranches 45041 # Number of branches that fetch has predicted taken
-system.cpu2.fetch.Cycles 100902 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu2.fetch.SquashCycles 3805 # Number of cycles fetch has spent squashing
-system.cpu2.fetch.BlockedCycles 31210 # Number of cycles fetch has spent blocked
-system.cpu2.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu2.fetch.NoActiveThreadStallCycles 7739 # Number of stall cycles due to no active thread to fetch from
-system.cpu2.fetch.PendingTrapStallCycles 775 # Number of stall cycles due to pending traps
-system.cpu2.fetch.CacheLines 19767 # Number of cache lines fetched
-system.cpu2.fetch.IcacheSquashes 276 # Number of outstanding Icache misses that were squashed
-system.cpu2.fetch.rateDist::samples 171898 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::mean 1.665034 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::stdev 2.139289 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::0 70996 41.30% 41.30% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::1 51338 29.87% 71.17% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::2 6125 3.56% 74.73% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::3 3190 1.86% 76.59% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::4 695 0.40% 76.99% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::5 34353 19.98% 96.97% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::6 1162 0.68% 97.65% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::7 771 0.45% 98.10% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::8 3268 1.90% 100.00% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::total 171898 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.branchRate 0.288953 # Number of branch fetches per cycle
-system.cpu2.fetch.rate 1.614158 # Number of inst fetches per cycle
-system.cpu2.decode.IdleCycles 33770 # Number of cycles decode is idle
-system.cpu2.decode.BlockedCycles 27924 # Number of cycles decode is blocked
-system.cpu2.decode.RunCycles 94988 # Number of cycles decode is running
-system.cpu2.decode.UnblockCycles 5055 # Number of cycles decode is unblocking
-system.cpu2.decode.SquashCycles 2422 # Number of cycles decode is squashing
-system.cpu2.decode.DecodedInsts 282690 # Number of instructions handled by decode
-system.cpu2.rename.SquashCycles 2422 # Number of cycles rename is squashing
-system.cpu2.rename.IdleCycles 34480 # Number of cycles rename is idle
-system.cpu2.rename.BlockCycles 14885 # Number of cycles rename is blocking
-system.cpu2.rename.serializeStallCycles 12280 # count of cycles rename stalled for serializing inst
-system.cpu2.rename.RunCycles 90190 # Number of cycles rename is running
-system.cpu2.rename.UnblockCycles 9902 # Number of cycles rename is unblocking
-system.cpu2.rename.RenamedInsts 280450 # Number of instructions processed by rename
-system.cpu2.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full
-system.cpu2.rename.LSQFullEvents 24 # Number of times rename has blocked due to LSQ full
-system.cpu2.rename.RenamedOperands 196553 # Number of destination operands rename has renamed
-system.cpu2.rename.RenameLookups 537620 # Number of register rename lookups that rename has made
-system.cpu2.rename.int_rename_lookups 537620 # Number of integer rename lookups
-system.cpu2.rename.CommittedMaps 183508 # Number of HB maps that are committed
-system.cpu2.rename.UndoneMaps 13045 # Number of HB maps that are undone due to squashing
-system.cpu2.rename.serializingInsts 1112 # count of serializing insts renamed
-system.cpu2.rename.tempSerializingInsts 1237 # count of temporary serializing insts renamed
-system.cpu2.rename.skidInsts 12513 # count of insts added to the skid buffer
-system.cpu2.memDep0.insertedLoads 79191 # Number of loads inserted to the mem dependence unit.
-system.cpu2.memDep0.insertedStores 37564 # Number of stores inserted to the mem dependence unit.
-system.cpu2.memDep0.conflictingLoads 37796 # Number of conflicting loads.
-system.cpu2.memDep0.conflictingStores 32512 # Number of conflicting stores.
-system.cpu2.iq.iqInstsAdded 232563 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu2.iq.iqNonSpecInstsAdded 6341 # Number of non-speculative instructions added to the IQ
-system.cpu2.iq.iqInstsIssued 234561 # Number of instructions issued
-system.cpu2.iq.iqSquashedInstsIssued 83 # Number of squashed instructions issued
-system.cpu2.iq.iqSquashedInstsExamined 11040 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu2.iq.iqSquashedOperandsExamined 10888 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu2.iq.iqSquashedNonSpecRemoved 602 # Number of squashed non-spec instructions that were removed
-system.cpu2.iq.issued_per_cycle::samples 171898 # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::mean 1.364536 # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::stdev 1.313534 # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::0 68441 39.81% 39.81% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::1 22472 13.07% 52.89% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::2 37788 21.98% 74.87% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::3 38389 22.33% 97.20% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::4 3254 1.89% 99.10% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::5 1164 0.68% 99.77% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::6 277 0.16% 99.93% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::7 56 0.03% 99.97% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::8 57 0.03% 100.00% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::total 171898 # Number of insts issued each cycle
-system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntAlu 17 6.14% 6.14% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntMult 0 0.00% 6.14% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntDiv 0 0.00% 6.14% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatAdd 0 0.00% 6.14% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCmp 0 0.00% 6.14% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCvt 0 0.00% 6.14% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatMult 0 0.00% 6.14% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatDiv 0 0.00% 6.14% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 6.14% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAdd 0 0.00% 6.14% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 6.14% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAlu 0 0.00% 6.14% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCmp 0 0.00% 6.14% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCvt 0 0.00% 6.14% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMisc 0 0.00% 6.14% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMult 0 0.00% 6.14% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 6.14% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShift 0 0.00% 6.14% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 6.14% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 6.14% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 6.14% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 6.14% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 6.14% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 6.14% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 6.14% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 6.14% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 6.14% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.14% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 6.14% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemRead 50 18.05% 24.19% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemWrite 210 75.81% 100.00% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntAlu 114217 48.69% 48.69% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntMult 0 0.00% 48.69% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 48.69% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 48.69% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 48.69% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 48.69% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 48.69% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 48.69% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 48.69% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 48.69% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 48.69% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 48.69% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 48.69% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 48.69% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 48.69% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 48.69% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 48.69% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 48.69% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.69% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 48.69% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.69% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.69% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.69% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.69% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.69% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.69% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 48.69% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.69% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.69% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemRead 83468 35.58% 84.28% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemWrite 36876 15.72% 100.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::total 234561 # Type of FU issued
-system.cpu2.iq.rate 1.322842 # Inst issue rate
-system.cpu2.iq.fu_busy_cnt 277 # FU busy when requested
-system.cpu2.iq.fu_busy_rate 0.001181 # FU busy rate (busy events/executed inst)
-system.cpu2.iq.int_inst_queue_reads 641380 # Number of integer instruction queue reads
-system.cpu2.iq.int_inst_queue_writes 249989 # Number of integer instruction queue writes
-system.cpu2.iq.int_inst_queue_wakeup_accesses 232740 # Number of integer instruction queue wakeup accesses
-system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
-system.cpu2.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
-system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
-system.cpu2.iq.int_alu_accesses 234838 # Number of integer alu accesses
-system.cpu2.iq.fp_alu_accesses 0 # Number of floating point alu accesses
-system.cpu2.iew.lsq.thread0.forwLoads 32248 # Number of loads that had data forwarded from stores
-system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu2.iew.lsq.thread0.squashedLoads 2484 # Number of loads squashed
-system.cpu2.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
-system.cpu2.iew.lsq.thread0.memOrderViolation 45 # Number of memory ordering violations
-system.cpu2.iew.lsq.thread0.squashedStores 1465 # Number of stores squashed
-system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu2.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
-system.cpu2.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
-system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu2.iew.iewSquashCycles 2422 # Number of cycles IEW is squashing
-system.cpu2.iew.iewBlockCycles 851 # Number of cycles IEW is blocking
-system.cpu2.iew.iewUnblockCycles 46 # Number of cycles IEW is unblocking
-system.cpu2.iew.iewDispatchedInsts 277610 # Number of instructions dispatched to IQ
-system.cpu2.iew.iewDispSquashedInsts 365 # Number of squashed instructions skipped by dispatch
-system.cpu2.iew.iewDispLoadInsts 79191 # Number of dispatched load instructions
-system.cpu2.iew.iewDispStoreInsts 37564 # Number of dispatched store instructions
-system.cpu2.iew.iewDispNonSpecInsts 1068 # Number of dispatched non-speculative instructions
-system.cpu2.iew.iewIQFullEvents 46 # Number of times the IQ has become full, causing a stall
-system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
-system.cpu2.iew.memOrderViolationEvents 45 # Number of memory order violations
-system.cpu2.iew.predictedTakenIncorrect 466 # Number of branches that were predicted taken incorrectly
-system.cpu2.iew.predictedNotTakenIncorrect 970 # Number of branches that were predicted not taken incorrectly
-system.cpu2.iew.branchMispredicts 1436 # Number of branch mispredicts detected at execute
-system.cpu2.iew.iewExecutedInsts 233403 # Number of executed instructions
-system.cpu2.iew.iewExecLoadInsts 78158 # Number of load instructions executed
-system.cpu2.iew.iewExecSquashedInsts 1158 # Number of squashed instructions skipped in execute
-system.cpu2.iew.exec_swp 0 # number of swp insts executed
-system.cpu2.iew.exec_nop 38706 # number of nop insts executed
-system.cpu2.iew.exec_refs 114950 # number of memory reference insts executed
-system.cpu2.iew.exec_branches 47927 # Number of branches executed
-system.cpu2.iew.exec_stores 36792 # Number of stores executed
-system.cpu2.iew.exec_rate 1.316311 # Inst execution rate
-system.cpu2.iew.wb_sent 233070 # cumulative count of insts sent to commit
-system.cpu2.iew.wb_count 232740 # cumulative count of insts written-back
-system.cpu2.iew.wb_producers 131730 # num instructions producing a value
-system.cpu2.iew.wb_consumers 136434 # num instructions consuming a value
-system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu2.iew.wb_rate 1.312572 # insts written-back per cycle
-system.cpu2.iew.wb_fanout 0.965522 # average fanout of values written-back
-system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu2.commit.commitSquashedInsts 12692 # The number of squashed insts skipped by commit
-system.cpu2.commit.commitNonSpecStalls 5739 # The number of times commit has been forced to stall to communicate backwards
-system.cpu2.commit.branchMispredicts 1308 # The number of times a branch was mispredicted
-system.cpu2.commit.committed_per_cycle::samples 161737 # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::mean 1.637943 # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::stdev 2.020354 # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::0 66243 40.96% 40.96% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::1 46082 28.49% 69.45% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::2 6100 3.77% 73.22% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::3 6659 4.12% 77.34% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::4 1556 0.96% 78.30% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::5 32794 20.28% 98.58% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::6 480 0.30% 98.87% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::7 1001 0.62% 99.49% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::8 822 0.51% 100.00% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::total 161737 # Number of insts commited each cycle
-system.cpu2.commit.committedInsts 264916 # Number of instructions committed
-system.cpu2.commit.committedOps 264916 # Number of ops (including micro ops) committed
-system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu2.commit.refs 112806 # Number of memory references committed
-system.cpu2.commit.loads 76707 # Number of loads committed
-system.cpu2.commit.membars 5024 # Number of memory barriers committed
-system.cpu2.commit.branches 47088 # Number of branches committed
-system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions.
-system.cpu2.commit.int_insts 182014 # Number of committed integer instructions.
-system.cpu2.commit.function_calls 322 # Number of function calls committed.
-system.cpu2.commit.bw_lim_events 822 # number cycles where commit BW limit reached
-system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu2.rob.rob_reads 437936 # The number of ROB reads
-system.cpu2.rob.rob_writes 557643 # The number of ROB writes
-system.cpu2.timesIdled 224 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu2.idleCycles 5418 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu2.quiesceCycles 44292 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu2.committedInsts 222015 # Number of Instructions Simulated
-system.cpu2.committedOps 222015 # Number of Ops (including micro ops) Simulated
-system.cpu2.committedInsts_total 222015 # Number of Instructions Simulated
-system.cpu2.cpi 0.798667 # CPI: Cycles Per Instruction
-system.cpu2.cpi_total 0.798667 # CPI: Total CPI of All Threads
-system.cpu2.ipc 1.252087 # IPC: Instructions Per Cycle
-system.cpu2.ipc_total 1.252087 # IPC: Total IPC of All Threads
-system.cpu2.int_regfile_reads 403571 # number of integer regfile reads
-system.cpu2.int_regfile_writes 188531 # number of integer regfile writes
-system.cpu2.fp_regfile_writes 64 # number of floating regfile writes
-system.cpu2.misc_regfile_reads 116514 # number of misc regfile reads
-system.cpu2.misc_regfile_writes 648 # number of misc regfile writes
-system.cpu2.icache.tags.replacements 317 # number of replacements
-system.cpu2.icache.tags.tagsinuse 82.351710 # Cycle average of tags in use
-system.cpu2.icache.tags.total_refs 19274 # Total number of references to valid blocks.
-system.cpu2.icache.tags.sampled_refs 425 # Sample count of references to valid blocks.
-system.cpu2.icache.tags.avg_refs 45.350588 # Average number of references to valid blocks.
-system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu2.icache.tags.occ_blocks::cpu2.inst 82.351710 # Average occupied blocks per requestor
-system.cpu2.icache.tags.occ_percent::cpu2.inst 0.160843 # Average percentage of cache occupancy
-system.cpu2.icache.tags.occ_percent::total 0.160843 # Average percentage of cache occupancy
-system.cpu2.icache.ReadReq_hits::cpu2.inst 19274 # number of ReadReq hits
-system.cpu2.icache.ReadReq_hits::total 19274 # number of ReadReq hits
-system.cpu2.icache.demand_hits::cpu2.inst 19274 # number of demand (read+write) hits
-system.cpu2.icache.demand_hits::total 19274 # number of demand (read+write) hits
-system.cpu2.icache.overall_hits::cpu2.inst 19274 # number of overall hits
-system.cpu2.icache.overall_hits::total 19274 # number of overall hits
-system.cpu2.icache.ReadReq_misses::cpu2.inst 493 # number of ReadReq misses
-system.cpu2.icache.ReadReq_misses::total 493 # number of ReadReq misses
-system.cpu2.icache.demand_misses::cpu2.inst 493 # number of demand (read+write) misses
-system.cpu2.icache.demand_misses::total 493 # number of demand (read+write) misses
-system.cpu2.icache.overall_misses::cpu2.inst 493 # number of overall misses
-system.cpu2.icache.overall_misses::total 493 # number of overall misses
-system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 11521742 # number of ReadReq miss cycles
-system.cpu2.icache.ReadReq_miss_latency::total 11521742 # number of ReadReq miss cycles
-system.cpu2.icache.demand_miss_latency::cpu2.inst 11521742 # number of demand (read+write) miss cycles
-system.cpu2.icache.demand_miss_latency::total 11521742 # number of demand (read+write) miss cycles
-system.cpu2.icache.overall_miss_latency::cpu2.inst 11521742 # number of overall miss cycles
-system.cpu2.icache.overall_miss_latency::total 11521742 # number of overall miss cycles
-system.cpu2.icache.ReadReq_accesses::cpu2.inst 19767 # number of ReadReq accesses(hits+misses)
-system.cpu2.icache.ReadReq_accesses::total 19767 # number of ReadReq accesses(hits+misses)
-system.cpu2.icache.demand_accesses::cpu2.inst 19767 # number of demand (read+write) accesses
-system.cpu2.icache.demand_accesses::total 19767 # number of demand (read+write) accesses
-system.cpu2.icache.overall_accesses::cpu2.inst 19767 # number of overall (read+write) accesses
-system.cpu2.icache.overall_accesses::total 19767 # number of overall (read+write) accesses
-system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.024941 # miss rate for ReadReq accesses
-system.cpu2.icache.ReadReq_miss_rate::total 0.024941 # miss rate for ReadReq accesses
-system.cpu2.icache.demand_miss_rate::cpu2.inst 0.024941 # miss rate for demand accesses
-system.cpu2.icache.demand_miss_rate::total 0.024941 # miss rate for demand accesses
-system.cpu2.icache.overall_miss_rate::cpu2.inst 0.024941 # miss rate for overall accesses
-system.cpu2.icache.overall_miss_rate::total 0.024941 # miss rate for overall accesses
-system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 23370.673428 # average ReadReq miss latency
-system.cpu2.icache.ReadReq_avg_miss_latency::total 23370.673428 # average ReadReq miss latency
-system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 23370.673428 # average overall miss latency
-system.cpu2.icache.demand_avg_miss_latency::total 23370.673428 # average overall miss latency
-system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 23370.673428 # average overall miss latency
-system.cpu2.icache.overall_avg_miss_latency::total 23370.673428 # average overall miss latency
-system.cpu2.icache.blocked_cycles::no_mshrs 85 # number of cycles access was blocked
-system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu2.icache.blocked::no_mshrs 1 # number of cycles access was blocked
-system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu2.icache.avg_blocked_cycles::no_mshrs 85 # average number of cycles each access was blocked
-system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu2.icache.fast_writes 0 # number of fast writes performed
-system.cpu2.icache.cache_copies 0 # number of cache copies performed
-system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 68 # number of ReadReq MSHR hits
-system.cpu2.icache.ReadReq_mshr_hits::total 68 # number of ReadReq MSHR hits
-system.cpu2.icache.demand_mshr_hits::cpu2.inst 68 # number of demand (read+write) MSHR hits
-system.cpu2.icache.demand_mshr_hits::total 68 # number of demand (read+write) MSHR hits
-system.cpu2.icache.overall_mshr_hits::cpu2.inst 68 # number of overall MSHR hits
-system.cpu2.icache.overall_mshr_hits::total 68 # number of overall MSHR hits
-system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 425 # number of ReadReq MSHR misses
-system.cpu2.icache.ReadReq_mshr_misses::total 425 # number of ReadReq MSHR misses
-system.cpu2.icache.demand_mshr_misses::cpu2.inst 425 # number of demand (read+write) MSHR misses
-system.cpu2.icache.demand_mshr_misses::total 425 # number of demand (read+write) MSHR misses
-system.cpu2.icache.overall_mshr_misses::cpu2.inst 425 # number of overall MSHR misses
-system.cpu2.icache.overall_mshr_misses::total 425 # number of overall MSHR misses
-system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 9201754 # number of ReadReq MSHR miss cycles
-system.cpu2.icache.ReadReq_mshr_miss_latency::total 9201754 # number of ReadReq MSHR miss cycles
-system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 9201754 # number of demand (read+write) MSHR miss cycles
-system.cpu2.icache.demand_mshr_miss_latency::total 9201754 # number of demand (read+write) MSHR miss cycles
-system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 9201754 # number of overall MSHR miss cycles
-system.cpu2.icache.overall_mshr_miss_latency::total 9201754 # number of overall MSHR miss cycles
-system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.021500 # mshr miss rate for ReadReq accesses
-system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.021500 # mshr miss rate for ReadReq accesses
-system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.021500 # mshr miss rate for demand accesses
-system.cpu2.icache.demand_mshr_miss_rate::total 0.021500 # mshr miss rate for demand accesses
-system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.021500 # mshr miss rate for overall accesses
-system.cpu2.icache.overall_mshr_miss_rate::total 0.021500 # mshr miss rate for overall accesses
-system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 21651.185882 # average ReadReq mshr miss latency
-system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 21651.185882 # average ReadReq mshr miss latency
-system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 21651.185882 # average overall mshr miss latency
-system.cpu2.icache.demand_avg_mshr_miss_latency::total 21651.185882 # average overall mshr miss latency
-system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 21651.185882 # average overall mshr miss latency
-system.cpu2.icache.overall_avg_mshr_miss_latency::total 21651.185882 # average overall mshr miss latency
-system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu2.dcache.tags.replacements 0 # number of replacements
-system.cpu2.dcache.tags.tagsinuse 26.191522 # Cycle average of tags in use
-system.cpu2.dcache.tags.total_refs 42135 # Total number of references to valid blocks.
-system.cpu2.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks.
-system.cpu2.dcache.tags.avg_refs 1504.821429 # Average number of references to valid blocks.
-system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu2.dcache.tags.occ_blocks::cpu2.data 26.191522 # Average occupied blocks per requestor
-system.cpu2.dcache.tags.occ_percent::cpu2.data 0.051155 # Average percentage of cache occupancy
-system.cpu2.dcache.tags.occ_percent::total 0.051155 # Average percentage of cache occupancy
-system.cpu2.dcache.ReadReq_hits::cpu2.data 45549 # number of ReadReq hits
-system.cpu2.dcache.ReadReq_hits::total 45549 # number of ReadReq hits
-system.cpu2.dcache.WriteReq_hits::cpu2.data 35887 # number of WriteReq hits
-system.cpu2.dcache.WriteReq_hits::total 35887 # number of WriteReq hits
-system.cpu2.dcache.SwapReq_hits::cpu2.data 12 # number of SwapReq hits
-system.cpu2.dcache.SwapReq_hits::total 12 # number of SwapReq hits
-system.cpu2.dcache.demand_hits::cpu2.data 81436 # number of demand (read+write) hits
-system.cpu2.dcache.demand_hits::total 81436 # number of demand (read+write) hits
-system.cpu2.dcache.overall_hits::cpu2.data 81436 # number of overall hits
-system.cpu2.dcache.overall_hits::total 81436 # number of overall hits
-system.cpu2.dcache.ReadReq_misses::cpu2.data 344 # number of ReadReq misses
-system.cpu2.dcache.ReadReq_misses::total 344 # number of ReadReq misses
-system.cpu2.dcache.WriteReq_misses::cpu2.data 143 # number of WriteReq misses
-system.cpu2.dcache.WriteReq_misses::total 143 # number of WriteReq misses
-system.cpu2.dcache.SwapReq_misses::cpu2.data 57 # number of SwapReq misses
-system.cpu2.dcache.SwapReq_misses::total 57 # number of SwapReq misses
-system.cpu2.dcache.demand_misses::cpu2.data 487 # number of demand (read+write) misses
-system.cpu2.dcache.demand_misses::total 487 # number of demand (read+write) misses
-system.cpu2.dcache.overall_misses::cpu2.data 487 # number of overall misses
-system.cpu2.dcache.overall_misses::total 487 # number of overall misses
-system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 5599802 # number of ReadReq miss cycles
-system.cpu2.dcache.ReadReq_miss_latency::total 5599802 # number of ReadReq miss cycles
-system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 3105260 # number of WriteReq miss cycles
-system.cpu2.dcache.WriteReq_miss_latency::total 3105260 # number of WriteReq miss cycles
-system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 575007 # number of SwapReq miss cycles
-system.cpu2.dcache.SwapReq_miss_latency::total 575007 # number of SwapReq miss cycles
-system.cpu2.dcache.demand_miss_latency::cpu2.data 8705062 # number of demand (read+write) miss cycles
-system.cpu2.dcache.demand_miss_latency::total 8705062 # number of demand (read+write) miss cycles
-system.cpu2.dcache.overall_miss_latency::cpu2.data 8705062 # number of overall miss cycles
-system.cpu2.dcache.overall_miss_latency::total 8705062 # number of overall miss cycles
-system.cpu2.dcache.ReadReq_accesses::cpu2.data 45893 # number of ReadReq accesses(hits+misses)
-system.cpu2.dcache.ReadReq_accesses::total 45893 # number of ReadReq accesses(hits+misses)
-system.cpu2.dcache.WriteReq_accesses::cpu2.data 36030 # number of WriteReq accesses(hits+misses)
-system.cpu2.dcache.WriteReq_accesses::total 36030 # number of WriteReq accesses(hits+misses)
-system.cpu2.dcache.SwapReq_accesses::cpu2.data 69 # number of SwapReq accesses(hits+misses)
-system.cpu2.dcache.SwapReq_accesses::total 69 # number of SwapReq accesses(hits+misses)
-system.cpu2.dcache.demand_accesses::cpu2.data 81923 # number of demand (read+write) accesses
-system.cpu2.dcache.demand_accesses::total 81923 # number of demand (read+write) accesses
-system.cpu2.dcache.overall_accesses::cpu2.data 81923 # number of overall (read+write) accesses
-system.cpu2.dcache.overall_accesses::total 81923 # number of overall (read+write) accesses
-system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.007496 # miss rate for ReadReq accesses
-system.cpu2.dcache.ReadReq_miss_rate::total 0.007496 # miss rate for ReadReq accesses
-system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.003969 # miss rate for WriteReq accesses
-system.cpu2.dcache.WriteReq_miss_rate::total 0.003969 # miss rate for WriteReq accesses
-system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.826087 # miss rate for SwapReq accesses
-system.cpu2.dcache.SwapReq_miss_rate::total 0.826087 # miss rate for SwapReq accesses
-system.cpu2.dcache.demand_miss_rate::cpu2.data 0.005945 # miss rate for demand accesses
-system.cpu2.dcache.demand_miss_rate::total 0.005945 # miss rate for demand accesses
-system.cpu2.dcache.overall_miss_rate::cpu2.data 0.005945 # miss rate for overall accesses
-system.cpu2.dcache.overall_miss_rate::total 0.005945 # miss rate for overall accesses
-system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 16278.494186 # average ReadReq miss latency
-system.cpu2.dcache.ReadReq_avg_miss_latency::total 16278.494186 # average ReadReq miss latency
-system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 21715.104895 # average WriteReq miss latency
-system.cpu2.dcache.WriteReq_avg_miss_latency::total 21715.104895 # average WriteReq miss latency
-system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 10087.842105 # average SwapReq miss latency
-system.cpu2.dcache.SwapReq_avg_miss_latency::total 10087.842105 # average SwapReq miss latency
-system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 17874.870637 # average overall miss latency
-system.cpu2.dcache.demand_avg_miss_latency::total 17874.870637 # average overall miss latency
-system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 17874.870637 # average overall miss latency
-system.cpu2.dcache.overall_avg_miss_latency::total 17874.870637 # average overall miss latency
-system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu2.dcache.fast_writes 0 # number of fast writes performed
-system.cpu2.dcache.cache_copies 0 # number of cache copies performed
-system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 182 # number of ReadReq MSHR hits
-system.cpu2.dcache.ReadReq_mshr_hits::total 182 # number of ReadReq MSHR hits
-system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 34 # number of WriteReq MSHR hits
-system.cpu2.dcache.WriteReq_mshr_hits::total 34 # number of WriteReq MSHR hits
-system.cpu2.dcache.demand_mshr_hits::cpu2.data 216 # number of demand (read+write) MSHR hits
-system.cpu2.dcache.demand_mshr_hits::total 216 # number of demand (read+write) MSHR hits
-system.cpu2.dcache.overall_mshr_hits::cpu2.data 216 # number of overall MSHR hits
-system.cpu2.dcache.overall_mshr_hits::total 216 # number of overall MSHR hits
-system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 162 # number of ReadReq MSHR misses
-system.cpu2.dcache.ReadReq_mshr_misses::total 162 # number of ReadReq MSHR misses
-system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 109 # number of WriteReq MSHR misses
-system.cpu2.dcache.WriteReq_mshr_misses::total 109 # number of WriteReq MSHR misses
-system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 57 # number of SwapReq MSHR misses
-system.cpu2.dcache.SwapReq_mshr_misses::total 57 # number of SwapReq MSHR misses
-system.cpu2.dcache.demand_mshr_misses::cpu2.data 271 # number of demand (read+write) MSHR misses
-system.cpu2.dcache.demand_mshr_misses::total 271 # number of demand (read+write) MSHR misses
-system.cpu2.dcache.overall_mshr_misses::cpu2.data 271 # number of overall MSHR misses
-system.cpu2.dcache.overall_mshr_misses::total 271 # number of overall MSHR misses
-system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1526780 # number of ReadReq MSHR miss cycles
-system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1526780 # number of ReadReq MSHR miss cycles
-system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1514240 # number of WriteReq MSHR miss cycles
-system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1514240 # number of WriteReq MSHR miss cycles
-system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 460993 # number of SwapReq MSHR miss cycles
-system.cpu2.dcache.SwapReq_mshr_miss_latency::total 460993 # number of SwapReq MSHR miss cycles
-system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3041020 # number of demand (read+write) MSHR miss cycles
-system.cpu2.dcache.demand_mshr_miss_latency::total 3041020 # number of demand (read+write) MSHR miss cycles
-system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3041020 # number of overall MSHR miss cycles
-system.cpu2.dcache.overall_mshr_miss_latency::total 3041020 # number of overall MSHR miss cycles
-system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003530 # mshr miss rate for ReadReq accesses
-system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003530 # mshr miss rate for ReadReq accesses
-system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.003025 # mshr miss rate for WriteReq accesses
-system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.003025 # mshr miss rate for WriteReq accesses
-system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.826087 # mshr miss rate for SwapReq accesses
-system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.826087 # mshr miss rate for SwapReq accesses
-system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003308 # mshr miss rate for demand accesses
-system.cpu2.dcache.demand_mshr_miss_rate::total 0.003308 # mshr miss rate for demand accesses
-system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003308 # mshr miss rate for overall accesses
-system.cpu2.dcache.overall_mshr_miss_rate::total 0.003308 # mshr miss rate for overall accesses
-system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 9424.567901 # average ReadReq mshr miss latency
-system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 9424.567901 # average ReadReq mshr miss latency
-system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 13892.110092 # average WriteReq mshr miss latency
-system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 13892.110092 # average WriteReq mshr miss latency
-system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 8087.596491 # average SwapReq mshr miss latency
-system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 8087.596491 # average SwapReq mshr miss latency
-system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 11221.476015 # average overall mshr miss latency
-system.cpu2.dcache.demand_avg_mshr_miss_latency::total 11221.476015 # average overall mshr miss latency
-system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 11221.476015 # average overall mshr miss latency
-system.cpu2.dcache.overall_avg_mshr_miss_latency::total 11221.476015 # average overall mshr miss latency
-system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu3.branchPred.lookups 56317 # Number of BP lookups
-system.cpu3.branchPred.condPredicted 53592 # Number of conditional branches predicted
-system.cpu3.branchPred.condIncorrect 1257 # Number of conditional branches incorrect
-system.cpu3.branchPred.BTBLookups 50318 # Number of BTB lookups
-system.cpu3.branchPred.BTBHits 49441 # Number of BTB hits
-system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu3.branchPred.BTBHitPct 98.257085 # BTB Hit Percentage
-system.cpu3.branchPred.usedRAS 649 # Number of times the RAS was used to get a target.
-system.cpu3.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions.
-system.cpu3.numCycles 176970 # number of cpu cycles simulated
-system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu3.fetch.icacheStallCycles 26467 # Number of cycles fetch is stalled on an Icache miss
-system.cpu3.fetch.Insts 318235 # Number of instructions fetch has processed
-system.cpu3.fetch.Branches 56317 # Number of branches that fetch encountered
-system.cpu3.fetch.predictedBranches 50090 # Number of branches that fetch has predicted taken
-system.cpu3.fetch.Cycles 110248 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu3.fetch.SquashCycles 3629 # Number of cycles fetch has spent squashing
-system.cpu3.fetch.BlockedCycles 28039 # Number of cycles fetch has spent blocked
-system.cpu3.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu3.fetch.NoActiveThreadStallCycles 7739 # Number of stall cycles due to no active thread to fetch from
-system.cpu3.fetch.PendingTrapStallCycles 790 # Number of stall cycles due to pending traps
-system.cpu3.fetch.CacheLines 18199 # Number of cache lines fetched
-system.cpu3.fetch.IcacheSquashes 258 # Number of outstanding Icache misses that were squashed
-system.cpu3.fetch.rateDist::samples 175582 # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::mean 1.812458 # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::stdev 2.180606 # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::0 65334 37.21% 37.21% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::1 55610 31.67% 68.88% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::2 5389 3.07% 71.95% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::3 3177 1.81% 73.76% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::4 669 0.38% 74.14% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::5 40119 22.85% 96.99% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::6 1237 0.70% 97.70% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::7 753 0.43% 98.12% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::8 3294 1.88% 100.00% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::total 175582 # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.branchRate 0.318229 # Number of branch fetches per cycle
-system.cpu3.fetch.rate 1.798243 # Number of inst fetches per cycle
-system.cpu3.decode.IdleCycles 31057 # Number of cycles decode is idle
-system.cpu3.decode.BlockedCycles 25106 # Number of cycles decode is blocked
-system.cpu3.decode.RunCycles 104911 # Number of cycles decode is running
-system.cpu3.decode.UnblockCycles 4475 # Number of cycles decode is unblocking
-system.cpu3.decode.SquashCycles 2294 # Number of cycles decode is squashing
-system.cpu3.decode.DecodedInsts 314540 # Number of instructions handled by decode
-system.cpu3.rename.SquashCycles 2294 # Number of cycles rename is squashing
-system.cpu3.rename.IdleCycles 31713 # Number of cycles rename is idle
-system.cpu3.rename.BlockCycles 12844 # Number of cycles rename is blocking
-system.cpu3.rename.serializeStallCycles 11527 # count of cycles rename stalled for serializing inst
-system.cpu3.rename.RunCycles 100723 # Number of cycles rename is running
-system.cpu3.rename.UnblockCycles 8742 # Number of cycles rename is unblocking
-system.cpu3.rename.RenamedInsts 312369 # Number of instructions processed by rename
-system.cpu3.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full
-system.cpu3.rename.LSQFullEvents 22 # Number of times rename has blocked due to LSQ full
-system.cpu3.rename.RenamedOperands 219058 # Number of destination operands rename has renamed
-system.cpu3.rename.RenameLookups 604346 # Number of register rename lookups that rename has made
-system.cpu3.rename.int_rename_lookups 604346 # Number of integer rename lookups
-system.cpu3.rename.CommittedMaps 206290 # Number of HB maps that are committed
-system.cpu3.rename.UndoneMaps 12768 # Number of HB maps that are undone due to squashing
-system.cpu3.rename.serializingInsts 1082 # count of serializing insts renamed
-system.cpu3.rename.tempSerializingInsts 1202 # count of temporary serializing insts renamed
-system.cpu3.rename.skidInsts 11332 # count of insts added to the skid buffer
-system.cpu3.memDep0.insertedLoads 90084 # Number of loads inserted to the mem dependence unit.
-system.cpu3.memDep0.insertedStores 43367 # Number of stores inserted to the mem dependence unit.
-system.cpu3.memDep0.conflictingLoads 42837 # Number of conflicting loads.
-system.cpu3.memDep0.conflictingStores 38342 # Number of conflicting stores.
-system.cpu3.iq.iqInstsAdded 260031 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu3.iq.iqNonSpecInstsAdded 5573 # Number of non-speculative instructions added to the IQ
-system.cpu3.iq.iqInstsIssued 261645 # Number of instructions issued
-system.cpu3.iq.iqSquashedInstsIssued 62 # Number of squashed instructions issued
-system.cpu3.iq.iqSquashedInstsExamined 10424 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu3.iq.iqSquashedOperandsExamined 10297 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu3.iq.iqSquashedNonSpecRemoved 498 # Number of squashed non-spec instructions that were removed
-system.cpu3.iq.issued_per_cycle::samples 175582 # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::mean 1.490158 # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::stdev 1.307816 # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::0 62519 35.61% 35.61% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::1 20435 11.64% 47.25% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::2 43580 24.82% 72.07% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::3 44218 25.18% 97.25% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::4 3288 1.87% 99.12% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::5 1176 0.67% 99.79% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::6 257 0.15% 99.94% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::7 50 0.03% 99.97% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::8 59 0.03% 100.00% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::total 175582 # Number of insts issued each cycle
-system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu3.iq.fu_full::IntAlu 17 6.25% 6.25% # attempts to use FU when none available
-system.cpu3.iq.fu_full::IntMult 0 0.00% 6.25% # attempts to use FU when none available
-system.cpu3.iq.fu_full::IntDiv 0 0.00% 6.25% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatAdd 0 0.00% 6.25% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatCmp 0 0.00% 6.25% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatCvt 0 0.00% 6.25% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatMult 0 0.00% 6.25% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatDiv 0 0.00% 6.25% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 6.25% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdAdd 0 0.00% 6.25% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 6.25% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdAlu 0 0.00% 6.25% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdCmp 0 0.00% 6.25% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdCvt 0 0.00% 6.25% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdMisc 0 0.00% 6.25% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdMult 0 0.00% 6.25% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 6.25% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdShift 0 0.00% 6.25% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 6.25% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 6.25% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 6.25% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 6.25% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 6.25% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 6.25% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 6.25% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 6.25% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 6.25% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.25% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 6.25% # attempts to use FU when none available
-system.cpu3.iq.fu_full::MemRead 45 16.54% 22.79% # attempts to use FU when none available
-system.cpu3.iq.fu_full::MemWrite 210 77.21% 100.00% # attempts to use FU when none available
-system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu3.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu3.iq.FU_type_0::IntAlu 125105 47.81% 47.81% # Type of FU issued
-system.cpu3.iq.FU_type_0::IntMult 0 0.00% 47.81% # Type of FU issued
-system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 47.81% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 47.81% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 47.81% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 47.81% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 47.81% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 47.81% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 47.81% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 47.81% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 47.81% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 47.81% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 47.81% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 47.81% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 47.81% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 47.81% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 47.81% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 47.81% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 47.81% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 47.81% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.81% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.81% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.81% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.81% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.81% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 47.81% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 47.81% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.81% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.81% # Type of FU issued
-system.cpu3.iq.FU_type_0::MemRead 93850 35.87% 83.68% # Type of FU issued
-system.cpu3.iq.FU_type_0::MemWrite 42690 16.32% 100.00% # Type of FU issued
-system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
-system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu3.iq.FU_type_0::total 261645 # Type of FU issued
-system.cpu3.iq.rate 1.478471 # Inst issue rate
-system.cpu3.iq.fu_busy_cnt 272 # FU busy when requested
-system.cpu3.iq.fu_busy_rate 0.001040 # FU busy rate (busy events/executed inst)
-system.cpu3.iq.int_inst_queue_reads 699206 # Number of integer instruction queue reads
-system.cpu3.iq.int_inst_queue_writes 276071 # Number of integer instruction queue writes
-system.cpu3.iq.int_inst_queue_wakeup_accesses 259793 # Number of integer instruction queue wakeup accesses
-system.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
-system.cpu3.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
-system.cpu3.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
-system.cpu3.iq.int_alu_accesses 261917 # Number of integer alu accesses
-system.cpu3.iq.fp_alu_accesses 0 # Number of floating point alu accesses
-system.cpu3.iew.lsq.thread0.forwLoads 38112 # Number of loads that had data forwarded from stores
-system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu3.iew.lsq.thread0.squashedLoads 2309 # Number of loads squashed
-system.cpu3.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
-system.cpu3.iew.lsq.thread0.memOrderViolation 43 # Number of memory ordering violations
-system.cpu3.iew.lsq.thread0.squashedStores 1414 # Number of stores squashed
-system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu3.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
-system.cpu3.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
-system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu3.iew.iewSquashCycles 2294 # Number of cycles IEW is squashing
-system.cpu3.iew.iewBlockCycles 580 # Number of cycles IEW is blocking
-system.cpu3.iew.iewUnblockCycles 36 # Number of cycles IEW is unblocking
-system.cpu3.iew.iewDispatchedInsts 309373 # Number of instructions dispatched to IQ
-system.cpu3.iew.iewDispSquashedInsts 369 # Number of squashed instructions skipped by dispatch
-system.cpu3.iew.iewDispLoadInsts 90084 # Number of dispatched load instructions
-system.cpu3.iew.iewDispStoreInsts 43367 # Number of dispatched store instructions
-system.cpu3.iew.iewDispNonSpecInsts 1034 # Number of dispatched non-speculative instructions
-system.cpu3.iew.iewIQFullEvents 36 # Number of times the IQ has become full, causing a stall
-system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
-system.cpu3.iew.memOrderViolationEvents 43 # Number of memory order violations
-system.cpu3.iew.predictedTakenIncorrect 465 # Number of branches that were predicted taken incorrectly
-system.cpu3.iew.predictedNotTakenIncorrect 904 # Number of branches that were predicted not taken incorrectly
-system.cpu3.iew.branchMispredicts 1369 # Number of branch mispredicts detected at execute
-system.cpu3.iew.iewExecutedInsts 260458 # Number of executed instructions
-system.cpu3.iew.iewExecLoadInsts 89199 # Number of load instructions executed
-system.cpu3.iew.iewExecSquashedInsts 1187 # Number of squashed instructions skipped in execute
-system.cpu3.iew.exec_swp 0 # number of swp insts executed
-system.cpu3.iew.exec_nop 43769 # number of nop insts executed
-system.cpu3.iew.exec_refs 131812 # number of memory reference insts executed
-system.cpu3.iew.exec_branches 53091 # Number of branches executed
-system.cpu3.iew.exec_stores 42613 # Number of stores executed
-system.cpu3.iew.exec_rate 1.471764 # Inst execution rate
-system.cpu3.iew.wb_sent 260118 # cumulative count of insts sent to commit
-system.cpu3.iew.wb_count 259793 # cumulative count of insts written-back
-system.cpu3.iew.wb_producers 148532 # num instructions producing a value
-system.cpu3.iew.wb_consumers 153197 # num instructions consuming a value
-system.cpu3.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu3.iew.wb_rate 1.468006 # insts written-back per cycle
-system.cpu3.iew.wb_fanout 0.969549 # average fanout of values written-back
-system.cpu3.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu3.commit.commitSquashedInsts 11915 # The number of squashed insts skipped by commit
-system.cpu3.commit.commitNonSpecStalls 5075 # The number of times commit has been forced to stall to communicate backwards
-system.cpu3.commit.branchMispredicts 1257 # The number of times a branch was mispredicted
-system.cpu3.commit.committed_per_cycle::samples 165549 # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::mean 1.796677 # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::stdev 2.064793 # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::0 59727 36.08% 36.08% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::1 51190 30.92% 67.00% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::2 6085 3.68% 70.68% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::3 6030 3.64% 74.32% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::4 1572 0.95% 75.27% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::5 38600 23.32% 98.58% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::6 530 0.32% 98.90% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::7 1000 0.60% 99.51% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::8 815 0.49% 100.00% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::total 165549 # Number of insts commited each cycle
-system.cpu3.commit.committedInsts 297438 # Number of instructions committed
-system.cpu3.commit.committedOps 297438 # Number of ops (including micro ops) committed
-system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu3.commit.refs 129728 # Number of memory references committed
-system.cpu3.commit.loads 87775 # Number of loads committed
-system.cpu3.commit.membars 4366 # Number of memory barriers committed
-system.cpu3.commit.branches 52284 # Number of branches committed
-system.cpu3.commit.fp_insts 0 # Number of committed floating point instructions.
-system.cpu3.commit.int_insts 204138 # Number of committed integer instructions.
-system.cpu3.commit.function_calls 322 # Number of function calls committed.
-system.cpu3.commit.bw_lim_events 815 # number cycles where commit BW limit reached
-system.cpu3.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu3.rob.rob_reads 473500 # The number of ROB reads
-system.cpu3.rob.rob_writes 621006 # The number of ROB writes
-system.cpu3.timesIdled 209 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu3.idleCycles 1388 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu3.quiesceCycles 44638 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu3.committedInsts 249993 # Number of Instructions Simulated
-system.cpu3.committedOps 249993 # Number of Ops (including micro ops) Simulated
-system.cpu3.committedInsts_total 249993 # Number of Instructions Simulated
-system.cpu3.cpi 0.707900 # CPI: Cycles Per Instruction
-system.cpu3.cpi_total 0.707900 # CPI: Total CPI of All Threads
-system.cpu3.ipc 1.412629 # IPC: Instructions Per Cycle
-system.cpu3.ipc_total 1.412629 # IPC: Total IPC of All Threads
-system.cpu3.int_regfile_reads 453881 # number of integer regfile reads
-system.cpu3.int_regfile_writes 211087 # number of integer regfile writes
-system.cpu3.fp_regfile_writes 64 # number of floating regfile writes
-system.cpu3.misc_regfile_reads 133368 # number of misc regfile reads
-system.cpu3.misc_regfile_writes 648 # number of misc regfile writes
-system.cpu3.icache.tags.replacements 319 # number of replacements
-system.cpu3.icache.tags.tagsinuse 77.348761 # Cycle average of tags in use
-system.cpu3.icache.tags.total_refs 17724 # Total number of references to valid blocks.
-system.cpu3.icache.tags.sampled_refs 430 # Sample count of references to valid blocks.
-system.cpu3.icache.tags.avg_refs 41.218605 # Average number of references to valid blocks.
-system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu3.icache.tags.occ_blocks::cpu3.inst 77.348761 # Average occupied blocks per requestor
-system.cpu3.icache.tags.occ_percent::cpu3.inst 0.151072 # Average percentage of cache occupancy
-system.cpu3.icache.tags.occ_percent::total 0.151072 # Average percentage of cache occupancy
-system.cpu3.icache.ReadReq_hits::cpu3.inst 17724 # number of ReadReq hits
-system.cpu3.icache.ReadReq_hits::total 17724 # number of ReadReq hits
-system.cpu3.icache.demand_hits::cpu3.inst 17724 # number of demand (read+write) hits
-system.cpu3.icache.demand_hits::total 17724 # number of demand (read+write) hits
-system.cpu3.icache.overall_hits::cpu3.inst 17724 # number of overall hits
-system.cpu3.icache.overall_hits::total 17724 # number of overall hits
-system.cpu3.icache.ReadReq_misses::cpu3.inst 475 # number of ReadReq misses
-system.cpu3.icache.ReadReq_misses::total 475 # number of ReadReq misses
-system.cpu3.icache.demand_misses::cpu3.inst 475 # number of demand (read+write) misses
-system.cpu3.icache.demand_misses::total 475 # number of demand (read+write) misses
-system.cpu3.icache.overall_misses::cpu3.inst 475 # number of overall misses
-system.cpu3.icache.overall_misses::total 475 # number of overall misses
-system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 6467995 # number of ReadReq miss cycles
-system.cpu3.icache.ReadReq_miss_latency::total 6467995 # number of ReadReq miss cycles
-system.cpu3.icache.demand_miss_latency::cpu3.inst 6467995 # number of demand (read+write) miss cycles
-system.cpu3.icache.demand_miss_latency::total 6467995 # number of demand (read+write) miss cycles
-system.cpu3.icache.overall_miss_latency::cpu3.inst 6467995 # number of overall miss cycles
-system.cpu3.icache.overall_miss_latency::total 6467995 # number of overall miss cycles
-system.cpu3.icache.ReadReq_accesses::cpu3.inst 18199 # number of ReadReq accesses(hits+misses)
-system.cpu3.icache.ReadReq_accesses::total 18199 # number of ReadReq accesses(hits+misses)
-system.cpu3.icache.demand_accesses::cpu3.inst 18199 # number of demand (read+write) accesses
-system.cpu3.icache.demand_accesses::total 18199 # number of demand (read+write) accesses
-system.cpu3.icache.overall_accesses::cpu3.inst 18199 # number of overall (read+write) accesses
-system.cpu3.icache.overall_accesses::total 18199 # number of overall (read+write) accesses
-system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.026100 # miss rate for ReadReq accesses
-system.cpu3.icache.ReadReq_miss_rate::total 0.026100 # miss rate for ReadReq accesses
-system.cpu3.icache.demand_miss_rate::cpu3.inst 0.026100 # miss rate for demand accesses
-system.cpu3.icache.demand_miss_rate::total 0.026100 # miss rate for demand accesses
-system.cpu3.icache.overall_miss_rate::cpu3.inst 0.026100 # miss rate for overall accesses
-system.cpu3.icache.overall_miss_rate::total 0.026100 # miss rate for overall accesses
-system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13616.831579 # average ReadReq miss latency
-system.cpu3.icache.ReadReq_avg_miss_latency::total 13616.831579 # average ReadReq miss latency
-system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13616.831579 # average overall miss latency
-system.cpu3.icache.demand_avg_miss_latency::total 13616.831579 # average overall miss latency
-system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13616.831579 # average overall miss latency
-system.cpu3.icache.overall_avg_miss_latency::total 13616.831579 # average overall miss latency
-system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu3.icache.fast_writes 0 # number of fast writes performed
-system.cpu3.icache.cache_copies 0 # number of cache copies performed
-system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 45 # number of ReadReq MSHR hits
-system.cpu3.icache.ReadReq_mshr_hits::total 45 # number of ReadReq MSHR hits
-system.cpu3.icache.demand_mshr_hits::cpu3.inst 45 # number of demand (read+write) MSHR hits
-system.cpu3.icache.demand_mshr_hits::total 45 # number of demand (read+write) MSHR hits
-system.cpu3.icache.overall_mshr_hits::cpu3.inst 45 # number of overall MSHR hits
-system.cpu3.icache.overall_mshr_hits::total 45 # number of overall MSHR hits
-system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 430 # number of ReadReq MSHR misses
-system.cpu3.icache.ReadReq_mshr_misses::total 430 # number of ReadReq MSHR misses
-system.cpu3.icache.demand_mshr_misses::cpu3.inst 430 # number of demand (read+write) MSHR misses
-system.cpu3.icache.demand_mshr_misses::total 430 # number of demand (read+write) MSHR misses
-system.cpu3.icache.overall_mshr_misses::cpu3.inst 430 # number of overall MSHR misses
-system.cpu3.icache.overall_mshr_misses::total 430 # number of overall MSHR misses
-system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 5219755 # number of ReadReq MSHR miss cycles
-system.cpu3.icache.ReadReq_mshr_miss_latency::total 5219755 # number of ReadReq MSHR miss cycles
-system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 5219755 # number of demand (read+write) MSHR miss cycles
-system.cpu3.icache.demand_mshr_miss_latency::total 5219755 # number of demand (read+write) MSHR miss cycles
-system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 5219755 # number of overall MSHR miss cycles
-system.cpu3.icache.overall_mshr_miss_latency::total 5219755 # number of overall MSHR miss cycles
-system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.023628 # mshr miss rate for ReadReq accesses
-system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.023628 # mshr miss rate for ReadReq accesses
-system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.023628 # mshr miss rate for demand accesses
-system.cpu3.icache.demand_mshr_miss_rate::total 0.023628 # mshr miss rate for demand accesses
-system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.023628 # mshr miss rate for overall accesses
-system.cpu3.icache.overall_mshr_miss_rate::total 0.023628 # mshr miss rate for overall accesses
-system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12138.965116 # average ReadReq mshr miss latency
-system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12138.965116 # average ReadReq mshr miss latency
-system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12138.965116 # average overall mshr miss latency
-system.cpu3.icache.demand_avg_mshr_miss_latency::total 12138.965116 # average overall mshr miss latency
-system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12138.965116 # average overall mshr miss latency
-system.cpu3.icache.overall_avg_mshr_miss_latency::total 12138.965116 # average overall mshr miss latency
-system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu3.dcache.tags.replacements 0 # number of replacements
-system.cpu3.dcache.tags.tagsinuse 23.659946 # Cycle average of tags in use
-system.cpu3.dcache.tags.total_refs 47957 # Total number of references to valid blocks.
-system.cpu3.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks.
-system.cpu3.dcache.tags.avg_refs 1712.750000 # Average number of references to valid blocks.
-system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu3.dcache.tags.occ_blocks::cpu3.data 23.659946 # Average occupied blocks per requestor
-system.cpu3.dcache.tags.occ_percent::cpu3.data 0.046211 # Average percentage of cache occupancy
-system.cpu3.dcache.tags.occ_percent::total 0.046211 # Average percentage of cache occupancy
-system.cpu3.dcache.ReadReq_hits::cpu3.data 50723 # number of ReadReq hits
-system.cpu3.dcache.ReadReq_hits::total 50723 # number of ReadReq hits
-system.cpu3.dcache.WriteReq_hits::cpu3.data 41752 # number of WriteReq hits
-system.cpu3.dcache.WriteReq_hits::total 41752 # number of WriteReq hits
-system.cpu3.dcache.SwapReq_hits::cpu3.data 12 # number of SwapReq hits
-system.cpu3.dcache.SwapReq_hits::total 12 # number of SwapReq hits
-system.cpu3.dcache.demand_hits::cpu3.data 92475 # number of demand (read+write) hits
-system.cpu3.dcache.demand_hits::total 92475 # number of demand (read+write) hits
-system.cpu3.dcache.overall_hits::cpu3.data 92475 # number of overall hits
-system.cpu3.dcache.overall_hits::total 92475 # number of overall hits
-system.cpu3.dcache.ReadReq_misses::cpu3.data 346 # number of ReadReq misses
-system.cpu3.dcache.ReadReq_misses::total 346 # number of ReadReq misses
-system.cpu3.dcache.WriteReq_misses::cpu3.data 138 # number of WriteReq misses
-system.cpu3.dcache.WriteReq_misses::total 138 # number of WriteReq misses
-system.cpu3.dcache.SwapReq_misses::cpu3.data 51 # number of SwapReq misses
-system.cpu3.dcache.SwapReq_misses::total 51 # number of SwapReq misses
-system.cpu3.dcache.demand_misses::cpu3.data 484 # number of demand (read+write) misses
-system.cpu3.dcache.demand_misses::total 484 # number of demand (read+write) misses
-system.cpu3.dcache.overall_misses::cpu3.data 484 # number of overall misses
-system.cpu3.dcache.overall_misses::total 484 # number of overall misses
-system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 4449419 # number of ReadReq miss cycles
-system.cpu3.dcache.ReadReq_miss_latency::total 4449419 # number of ReadReq miss cycles
-system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 2879011 # number of WriteReq miss cycles
-system.cpu3.dcache.WriteReq_miss_latency::total 2879011 # number of WriteReq miss cycles
-system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 478509 # number of SwapReq miss cycles
-system.cpu3.dcache.SwapReq_miss_latency::total 478509 # number of SwapReq miss cycles
-system.cpu3.dcache.demand_miss_latency::cpu3.data 7328430 # number of demand (read+write) miss cycles
-system.cpu3.dcache.demand_miss_latency::total 7328430 # number of demand (read+write) miss cycles
-system.cpu3.dcache.overall_miss_latency::cpu3.data 7328430 # number of overall miss cycles
-system.cpu3.dcache.overall_miss_latency::total 7328430 # number of overall miss cycles
-system.cpu3.dcache.ReadReq_accesses::cpu3.data 51069 # number of ReadReq accesses(hits+misses)
-system.cpu3.dcache.ReadReq_accesses::total 51069 # number of ReadReq accesses(hits+misses)
-system.cpu3.dcache.WriteReq_accesses::cpu3.data 41890 # number of WriteReq accesses(hits+misses)
-system.cpu3.dcache.WriteReq_accesses::total 41890 # number of WriteReq accesses(hits+misses)
-system.cpu3.dcache.SwapReq_accesses::cpu3.data 63 # number of SwapReq accesses(hits+misses)
-system.cpu3.dcache.SwapReq_accesses::total 63 # number of SwapReq accesses(hits+misses)
-system.cpu3.dcache.demand_accesses::cpu3.data 92959 # number of demand (read+write) accesses
-system.cpu3.dcache.demand_accesses::total 92959 # number of demand (read+write) accesses
-system.cpu3.dcache.overall_accesses::cpu3.data 92959 # number of overall (read+write) accesses
-system.cpu3.dcache.overall_accesses::total 92959 # number of overall (read+write) accesses
-system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.006775 # miss rate for ReadReq accesses
-system.cpu3.dcache.ReadReq_miss_rate::total 0.006775 # miss rate for ReadReq accesses
-system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.003294 # miss rate for WriteReq accesses
-system.cpu3.dcache.WriteReq_miss_rate::total 0.003294 # miss rate for WriteReq accesses
-system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.809524 # miss rate for SwapReq accesses
-system.cpu3.dcache.SwapReq_miss_rate::total 0.809524 # miss rate for SwapReq accesses
-system.cpu3.dcache.demand_miss_rate::cpu3.data 0.005207 # miss rate for demand accesses
-system.cpu3.dcache.demand_miss_rate::total 0.005207 # miss rate for demand accesses
-system.cpu3.dcache.overall_miss_rate::cpu3.data 0.005207 # miss rate for overall accesses
-system.cpu3.dcache.overall_miss_rate::total 0.005207 # miss rate for overall accesses
-system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 12859.592486 # average ReadReq miss latency
-system.cpu3.dcache.ReadReq_avg_miss_latency::total 12859.592486 # average ReadReq miss latency
-system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 20862.398551 # average WriteReq miss latency
-system.cpu3.dcache.WriteReq_avg_miss_latency::total 20862.398551 # average WriteReq miss latency
-system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 9382.529412 # average SwapReq miss latency
-system.cpu3.dcache.SwapReq_avg_miss_latency::total 9382.529412 # average SwapReq miss latency
-system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 15141.384298 # average overall miss latency
-system.cpu3.dcache.demand_avg_miss_latency::total 15141.384298 # average overall miss latency
-system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 15141.384298 # average overall miss latency
-system.cpu3.dcache.overall_avg_miss_latency::total 15141.384298 # average overall miss latency
-system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu3.dcache.fast_writes 0 # number of fast writes performed
-system.cpu3.dcache.cache_copies 0 # number of cache copies performed
-system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 195 # number of ReadReq MSHR hits
-system.cpu3.dcache.ReadReq_mshr_hits::total 195 # number of ReadReq MSHR hits
-system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 32 # number of WriteReq MSHR hits
-system.cpu3.dcache.WriteReq_mshr_hits::total 32 # number of WriteReq MSHR hits
-system.cpu3.dcache.demand_mshr_hits::cpu3.data 227 # number of demand (read+write) MSHR hits
-system.cpu3.dcache.demand_mshr_hits::total 227 # number of demand (read+write) MSHR hits
-system.cpu3.dcache.overall_mshr_hits::cpu3.data 227 # number of overall MSHR hits
-system.cpu3.dcache.overall_mshr_hits::total 227 # number of overall MSHR hits
-system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 151 # number of ReadReq MSHR misses
-system.cpu3.dcache.ReadReq_mshr_misses::total 151 # number of ReadReq MSHR misses
-system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 106 # number of WriteReq MSHR misses
-system.cpu3.dcache.WriteReq_mshr_misses::total 106 # number of WriteReq MSHR misses
-system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 51 # number of SwapReq MSHR misses
-system.cpu3.dcache.SwapReq_mshr_misses::total 51 # number of SwapReq MSHR misses
-system.cpu3.dcache.demand_mshr_misses::cpu3.data 257 # number of demand (read+write) MSHR misses
-system.cpu3.dcache.demand_mshr_misses::total 257 # number of demand (read+write) MSHR misses
-system.cpu3.dcache.overall_mshr_misses::cpu3.data 257 # number of overall MSHR misses
-system.cpu3.dcache.overall_mshr_misses::total 257 # number of overall MSHR misses
-system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1003763 # number of ReadReq MSHR miss cycles
-system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1003763 # number of ReadReq MSHR miss cycles
-system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1322239 # number of WriteReq MSHR miss cycles
-system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1322239 # number of WriteReq MSHR miss cycles
-system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 376491 # number of SwapReq MSHR miss cycles
-system.cpu3.dcache.SwapReq_mshr_miss_latency::total 376491 # number of SwapReq MSHR miss cycles
-system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 2326002 # number of demand (read+write) MSHR miss cycles
-system.cpu3.dcache.demand_mshr_miss_latency::total 2326002 # number of demand (read+write) MSHR miss cycles
-system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 2326002 # number of overall MSHR miss cycles
-system.cpu3.dcache.overall_mshr_miss_latency::total 2326002 # number of overall MSHR miss cycles
-system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.002957 # mshr miss rate for ReadReq accesses
-system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.002957 # mshr miss rate for ReadReq accesses
-system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.002530 # mshr miss rate for WriteReq accesses
-system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.002530 # mshr miss rate for WriteReq accesses
-system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.809524 # mshr miss rate for SwapReq accesses
-system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.809524 # mshr miss rate for SwapReq accesses
-system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.002765 # mshr miss rate for demand accesses
-system.cpu3.dcache.demand_mshr_miss_rate::total 0.002765 # mshr miss rate for demand accesses
-system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.002765 # mshr miss rate for overall accesses
-system.cpu3.dcache.overall_mshr_miss_rate::total 0.002765 # mshr miss rate for overall accesses
-system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 6647.437086 # average ReadReq mshr miss latency
-system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 6647.437086 # average ReadReq mshr miss latency
-system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 12473.952830 # average WriteReq mshr miss latency
-system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 12473.952830 # average WriteReq mshr miss latency
-system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 7382.176471 # average SwapReq mshr miss latency
-system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 7382.176471 # average SwapReq mshr miss latency
-system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 9050.591440 # average overall mshr miss latency
-system.cpu3.dcache.demand_avg_mshr_miss_latency::total 9050.591440 # average overall mshr miss latency
-system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 9050.591440 # average overall mshr miss latency
-system.cpu3.dcache.overall_avg_mshr_miss_latency::total 9050.591440 # average overall mshr miss latency
-system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.l2c.tags.replacements 0 # number of replacements
-system.l2c.tags.tagsinuse 416.979851 # Cycle average of tags in use
-system.l2c.tags.total_refs 1443 # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs 526 # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs 2.743346 # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks 0.800256 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst 284.888559 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data 58.382327 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst 7.813679 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data 0.733163 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.inst 55.504569 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.data 5.417548 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3.inst 2.743977 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3.data 0.695773 # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks 0.000012 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst 0.004347 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data 0.000891 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst 0.000119 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data 0.000011 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.inst 0.000847 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.data 0.000083 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu3.inst 0.000042 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu3.data 0.000011 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total 0.006363 # Average percentage of cache occupancy
+system.l2c.tags.replacements 0 # number of replacements
+system.l2c.tags.tagsinuse 416.979851 # Cycle average of tags in use
+system.l2c.tags.total_refs 1443 # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs 526 # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs 2.743346 # Average number of references to valid blocks.
+system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.l2c.tags.occ_blocks::writebacks 0.800256 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst 284.888559 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data 58.382327 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst 7.813679 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data 0.733163 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.inst 55.504569 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.data 5.417548 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu3.inst 2.743977 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu3.data 0.695773 # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks 0.000012 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.inst 0.004347 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data 0.000891 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst 0.000119 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.data 0.000011 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu2.inst 0.000847 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu2.data 0.000083 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu3.inst 0.000042 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu3.data 0.000011 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total 0.006363 # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu0.inst 229 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst 412 # number of ReadReq hits
system.l2c.overall_avg_mshr_miss_latency::cpu3.data 62115.384615 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 58790.150000 # average overall mshr miss latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
+system.toL2Bus.throughput 1691772446 # Throughput (bytes/s)
+system.toL2Bus.trans_dist::ReadReq 2536 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 2535 # Transaction distribution
+system.toL2Bus.trans_dist::Writeback 1 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 290 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 290 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 393 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 393 # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1175 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 586 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 856 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 365 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 850 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 371 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 860 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 352 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 5415 # Packet count per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 37568 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 11136 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 27392 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1536 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 27200 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 27520 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1536 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size::total 135488 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.data_through_bus 135488 # Total data (bytes)
+system.toL2Bus.snoop_data_through_bus 51968 # Total snoop data (bytes)
+system.toL2Bus.reqLayer0.occupancy 1623982 # Layer occupancy (ticks)
+system.toL2Bus.reqLayer0.utilization 1.5 # Layer utilization (%)
+system.toL2Bus.respLayer0.occupancy 2710248 # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.utilization 2.4 # Layer utilization (%)
+system.toL2Bus.respLayer1.occupancy 1462515 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%)
+system.toL2Bus.respLayer2.occupancy 1929494 # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.utilization 1.7 # Layer utilization (%)
+system.toL2Bus.respLayer3.occupancy 1189495 # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.utilization 1.1 # Layer utilization (%)
+system.toL2Bus.respLayer4.occupancy 1927246 # Layer occupancy (ticks)
+system.toL2Bus.respLayer4.utilization 1.7 # Layer utilization (%)
+system.toL2Bus.respLayer5.occupancy 1192987 # Layer occupancy (ticks)
+system.toL2Bus.respLayer5.utilization 1.1 # Layer utilization (%)
+system.toL2Bus.respLayer6.occupancy 1937245 # Layer occupancy (ticks)
+system.toL2Bus.respLayer6.utilization 1.7 # Layer utilization (%)
+system.toL2Bus.respLayer7.occupancy 1118007 # Layer occupancy (ticks)
+system.toL2Bus.respLayer7.utilization 1.0 # Layer utilization (%)
+system.cpu0.branchPred.lookups 82992 # Number of BP lookups
+system.cpu0.branchPred.condPredicted 80791 # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect 1218 # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups 80321 # Number of BTB lookups
+system.cpu0.branchPred.BTBHits 78273 # Number of BTB hits
+system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu0.branchPred.BTBHitPct 97.450231 # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS 512 # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect 132 # Number of incorrect RAS predictions.
+system.cpu0.workload.num_syscalls 89 # Number of system calls
+system.cpu0.numCycles 221610 # number of cpu cycles simulated
+system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu0.fetch.icacheStallCycles 17247 # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts 492529 # Number of instructions fetch has processed
+system.cpu0.fetch.Branches 82992 # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches 78785 # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles 161677 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles 3808 # Number of cycles fetch has spent squashing
+system.cpu0.fetch.BlockedCycles 13819 # Number of cycles fetch has spent blocked
+system.cpu0.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu0.fetch.PendingTrapStallCycles 1570 # Number of stall cycles due to pending traps
+system.cpu0.fetch.CacheLines 5835 # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes 493 # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.rateDist::samples 196760 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean 2.503197 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev 2.215126 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0 35083 17.83% 17.83% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1 80084 40.70% 58.53% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2 578 0.29% 58.83% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3 973 0.49% 59.32% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::4 477 0.24% 59.56% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::5 76189 38.72% 98.28% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::6 571 0.29% 98.57% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::7 349 0.18% 98.75% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::8 2456 1.25% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::total 196760 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate 0.374496 # Number of branch fetches per cycle
+system.cpu0.fetch.rate 2.222503 # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles 17898 # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles 15432 # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles 160701 # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles 287 # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles 2442 # Number of cycles decode is squashing
+system.cpu0.decode.DecodedInsts 489694 # Number of instructions handled by decode
+system.cpu0.rename.SquashCycles 2442 # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles 18563 # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles 848 # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles 13994 # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles 160355 # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles 558 # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts 486837 # Number of instructions processed by rename
+system.cpu0.rename.LSQFullEvents 188 # Number of times rename has blocked due to LSQ full
+system.cpu0.rename.RenamedOperands 332900 # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups 970872 # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups 970872 # Number of integer rename lookups
+system.cpu0.rename.CommittedMaps 319955 # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps 12945 # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts 867 # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts 888 # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts 3605 # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads 155755 # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores 78714 # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads 75965 # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores 75781 # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded 407125 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded 911 # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued 404423 # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued 128 # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined 10748 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined 9686 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedNonSpecRemoved 352 # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.issued_per_cycle::samples 196760 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean 2.055413 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev 1.097364 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0 34065 17.31% 17.31% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1 4908 2.49% 19.81% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2 77935 39.61% 59.42% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3 77266 39.27% 98.69% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4 1571 0.80% 99.48% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5 648 0.33% 99.81% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::6 262 0.13% 99.95% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::7 89 0.05% 99.99% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::8 16 0.01% 100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total 196760 # Number of insts issued each cycle
+system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu 57 25.91% 25.91% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult 0 0.00% 25.91% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntDiv 0 0.00% 25.91% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatAdd 0 0.00% 25.91% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCmp 0 0.00% 25.91% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCvt 0 0.00% 25.91% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult 0 0.00% 25.91% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv 0 0.00% 25.91% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 25.91% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd 0 0.00% 25.91% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 25.91% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAlu 0 0.00% 25.91% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCmp 0 0.00% 25.91% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCvt 0 0.00% 25.91% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMisc 0 0.00% 25.91% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult 0 0.00% 25.91% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 25.91% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift 0 0.00% 25.91% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 25.91% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 25.91% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 25.91% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 25.91% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 25.91% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 25.91% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 25.91% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 25.91% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 25.91% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.91% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 25.91% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead 51 23.18% 49.09% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite 112 50.91% 100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
+system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu 170994 42.28% 42.28% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.28% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.28% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.28% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.28% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.28% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.28% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.28% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.28% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.28% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.28% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.28% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.28% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.28% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.28% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.28% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.28% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.28% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.28% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.28% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.28% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.28% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.28% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.28% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.28% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.28% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.28% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.28% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.28% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead 155300 38.40% 80.68% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite 78129 19.32% 100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::total 404423 # Type of FU issued
+system.cpu0.iq.rate 1.824931 # Inst issue rate
+system.cpu0.iq.fu_busy_cnt 220 # FU busy when requested
+system.cpu0.iq.fu_busy_rate 0.000544 # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads 1005954 # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes 418838 # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses 402603 # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
+system.cpu0.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
+system.cpu0.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
+system.cpu0.iq.int_alu_accesses 404643 # Number of integer alu accesses
+system.cpu0.iq.fp_alu_accesses 0 # Number of floating point alu accesses
+system.cpu0.iew.lsq.thread0.forwLoads 75498 # Number of loads that had data forwarded from stores
+system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
+system.cpu0.iew.lsq.thread0.squashedLoads 2188 # Number of loads squashed
+system.cpu0.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread0.memOrderViolation 54 # Number of memory ordering violations
+system.cpu0.iew.lsq.thread0.squashedStores 1424 # Number of stores squashed
+system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
+system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
+system.cpu0.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
+system.cpu0.iew.lsq.thread0.cacheBlocked 19 # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
+system.cpu0.iew.iewSquashCycles 2442 # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles 391 # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles 33 # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts 484551 # Number of instructions dispatched to IQ
+system.cpu0.iew.iewDispSquashedInsts 313 # Number of squashed instructions skipped by dispatch
+system.cpu0.iew.iewDispLoadInsts 155755 # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts 78714 # Number of dispatched store instructions
+system.cpu0.iew.iewDispNonSpecInsts 799 # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewIQFullEvents 38 # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
+system.cpu0.iew.memOrderViolationEvents 54 # Number of memory order violations
+system.cpu0.iew.predictedTakenIncorrect 343 # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedNotTakenIncorrect 1106 # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts 1449 # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewExecutedInsts 403352 # Number of executed instructions
+system.cpu0.iew.iewExecLoadInsts 154964 # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts 1071 # Number of squashed instructions skipped in execute
+system.cpu0.iew.exec_swp 0 # number of swp insts executed
+system.cpu0.iew.exec_nop 76515 # number of nop insts executed
+system.cpu0.iew.exec_refs 232993 # number of memory reference insts executed
+system.cpu0.iew.exec_branches 80132 # Number of branches executed
+system.cpu0.iew.exec_stores 78029 # Number of stores executed
+system.cpu0.iew.exec_rate 1.820098 # Inst execution rate
+system.cpu0.iew.wb_sent 402944 # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count 402603 # cumulative count of insts written-back
+system.cpu0.iew.wb_producers 238549 # num instructions producing a value
+system.cpu0.iew.wb_consumers 241004 # num instructions consuming a value
+system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
+system.cpu0.iew.wb_rate 1.816719 # insts written-back per cycle
+system.cpu0.iew.wb_fanout 0.989813 # average fanout of values written-back
+system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu0.commit.commitSquashedInsts 12240 # The number of squashed insts skipped by commit
+system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards
+system.cpu0.commit.branchMispredicts 1218 # The number of times a branch was mispredicted
+system.cpu0.commit.committed_per_cycle::samples 194318 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean 2.430470 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev 2.136197 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0 34493 17.75% 17.75% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1 79895 41.12% 58.87% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2 2401 1.24% 60.10% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3 689 0.35% 60.46% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4 530 0.27% 60.73% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5 75316 38.76% 99.49% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6 445 0.23% 99.72% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7 242 0.12% 99.84% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8 307 0.16% 100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::total 194318 # Number of insts commited each cycle
+system.cpu0.commit.committedInsts 472284 # Number of instructions committed
+system.cpu0.commit.committedOps 472284 # Number of ops (including micro ops) committed
+system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
+system.cpu0.commit.refs 230857 # Number of memory references committed
+system.cpu0.commit.loads 153567 # Number of loads committed
+system.cpu0.commit.membars 84 # Number of memory barriers committed
+system.cpu0.commit.branches 79177 # Number of branches committed
+system.cpu0.commit.fp_insts 0 # Number of committed floating point instructions.
+system.cpu0.commit.int_insts 318286 # Number of committed integer instructions.
+system.cpu0.commit.function_calls 223 # Number of function calls committed.
+system.cpu0.commit.bw_lim_events 307 # number cycles where commit BW limit reached
+system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits
+system.cpu0.rob.rob_reads 677374 # The number of ROB reads
+system.cpu0.rob.rob_writes 971507 # The number of ROB writes
+system.cpu0.timesIdled 326 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu0.idleCycles 24850 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu0.committedInsts 396291 # Number of Instructions Simulated
+system.cpu0.committedOps 396291 # Number of Ops (including micro ops) Simulated
+system.cpu0.committedInsts_total 396291 # Number of Instructions Simulated
+system.cpu0.cpi 0.559210 # CPI: Cycles Per Instruction
+system.cpu0.cpi_total 0.559210 # CPI: Total CPI of All Threads
+system.cpu0.ipc 1.788236 # IPC: Instructions Per Cycle
+system.cpu0.ipc_total 1.788236 # IPC: Total IPC of All Threads
+system.cpu0.int_regfile_reads 721592 # number of integer regfile reads
+system.cpu0.int_regfile_writes 325227 # number of integer regfile writes
+system.cpu0.fp_regfile_reads 192 # number of floating regfile reads
+system.cpu0.misc_regfile_reads 234817 # number of misc regfile reads
+system.cpu0.misc_regfile_writes 564 # number of misc regfile writes
+system.cpu0.icache.tags.replacements 297 # number of replacements
+system.cpu0.icache.tags.tagsinuse 241.148232 # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs 5079 # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs 587 # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs 8.652470 # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst 241.148232 # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst 0.470993 # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total 0.470993 # Average percentage of cache occupancy
+system.cpu0.icache.ReadReq_hits::cpu0.inst 5079 # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total 5079 # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst 5079 # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total 5079 # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst 5079 # number of overall hits
+system.cpu0.icache.overall_hits::total 5079 # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst 756 # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total 756 # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst 756 # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total 756 # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst 756 # number of overall misses
+system.cpu0.icache.overall_misses::total 756 # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 35147245 # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total 35147245 # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst 35147245 # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total 35147245 # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst 35147245 # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total 35147245 # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst 5835 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total 5835 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst 5835 # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total 5835 # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst 5835 # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total 5835 # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.129563 # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total 0.129563 # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst 0.129563 # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total 0.129563 # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst 0.129563 # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total 0.129563 # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 46491.064815 # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 46491.064815 # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 46491.064815 # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 46491.064815 # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 46491.064815 # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 46491.064815 # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu0.icache.fast_writes 0 # number of fast writes performed
+system.cpu0.icache.cache_copies 0 # number of cache copies performed
+system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 168 # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total 168 # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu0.inst 168 # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total 168 # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu0.inst 168 # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total 168 # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 588 # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total 588 # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst 588 # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total 588 # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst 588 # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total 588 # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 27250252 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total 27250252 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 27250252 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total 27250252 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 27250252 # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total 27250252 # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.100771 # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.100771 # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.100771 # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total 0.100771 # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.100771 # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total 0.100771 # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 46343.965986 # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 46343.965986 # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 46343.965986 # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 46343.965986 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 46343.965986 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 46343.965986 # average overall mshr miss latency
+system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu0.dcache.tags.replacements 2 # number of replacements
+system.cpu0.dcache.tags.tagsinuse 141.869283 # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs 155614 # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs 170 # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs 915.376471 # Average number of references to valid blocks.
+system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.tags.occ_blocks::cpu0.data 141.869283 # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data 0.277088 # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total 0.277088 # Average percentage of cache occupancy
+system.cpu0.dcache.ReadReq_hits::cpu0.data 78995 # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total 78995 # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data 76703 # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total 76703 # number of WriteReq hits
+system.cpu0.dcache.SwapReq_hits::cpu0.data 21 # number of SwapReq hits
+system.cpu0.dcache.SwapReq_hits::total 21 # number of SwapReq hits
+system.cpu0.dcache.demand_hits::cpu0.data 155698 # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total 155698 # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data 155698 # number of overall hits
+system.cpu0.dcache.overall_hits::total 155698 # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data 410 # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total 410 # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data 545 # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total 545 # number of WriteReq misses
+system.cpu0.dcache.SwapReq_misses::cpu0.data 21 # number of SwapReq misses
+system.cpu0.dcache.SwapReq_misses::total 21 # number of SwapReq misses
+system.cpu0.dcache.demand_misses::cpu0.data 955 # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total 955 # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data 955 # number of overall misses
+system.cpu0.dcache.overall_misses::total 955 # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 13319205 # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total 13319205 # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 35150505 # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total 35150505 # number of WriteReq miss cycles
+system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 418750 # number of SwapReq miss cycles
+system.cpu0.dcache.SwapReq_miss_latency::total 418750 # number of SwapReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data 48469710 # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total 48469710 # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data 48469710 # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total 48469710 # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data 79405 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total 79405 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data 77248 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total 77248 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses)
+system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data 156653 # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total 156653 # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data 156653 # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total 156653 # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.005163 # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total 0.005163 # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007055 # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total 0.007055 # miss rate for WriteReq accesses
+system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.500000 # miss rate for SwapReq accesses
+system.cpu0.dcache.SwapReq_miss_rate::total 0.500000 # miss rate for SwapReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006096 # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total 0.006096 # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006096 # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total 0.006096 # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 32485.865854 # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 32485.865854 # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 64496.339450 # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 64496.339450 # average WriteReq miss latency
+system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 19940.476190 # average SwapReq miss latency
+system.cpu0.dcache.SwapReq_avg_miss_latency::total 19940.476190 # average SwapReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 50753.623037 # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 50753.623037 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 50753.623037 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 50753.623037 # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs 503 # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs 21 # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs 23.952381 # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu0.dcache.fast_writes 0 # number of fast writes performed
+system.cpu0.dcache.cache_copies 0 # number of cache copies performed
+system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks
+system.cpu0.dcache.writebacks::total 1 # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 223 # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total 223 # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 370 # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total 370 # number of WriteReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data 593 # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total 593 # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data 593 # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total 593 # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 187 # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total 187 # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 175 # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total 175 # number of WriteReq MSHR misses
+system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 21 # number of SwapReq MSHR misses
+system.cpu0.dcache.SwapReq_mshr_misses::total 21 # number of SwapReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data 362 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total 362 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data 362 # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total 362 # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 6285007 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6285007 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7788228 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7788228 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 375250 # number of SwapReq MSHR miss cycles
+system.cpu0.dcache.SwapReq_mshr_miss_latency::total 375250 # number of SwapReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 14073235 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total 14073235 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 14073235 # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total 14073235 # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002355 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002355 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002265 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002265 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.500000 # mshr miss rate for SwapReq accesses
+system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SwapReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002311 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total 0.002311 # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002311 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total 0.002311 # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 33609.663102 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 33609.663102 # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 44504.160000 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 44504.160000 # average WriteReq mshr miss latency
+system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 17869.047619 # average SwapReq mshr miss latency
+system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 17869.047619 # average SwapReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 38876.339779 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 38876.339779 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 38876.339779 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 38876.339779 # average overall mshr miss latency
+system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu1.branchPred.lookups 43495 # Number of BP lookups
+system.cpu1.branchPred.condPredicted 40766 # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect 1279 # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups 37360 # Number of BTB lookups
+system.cpu1.branchPred.BTBHits 36580 # Number of BTB hits
+system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu1.branchPred.BTBHitPct 97.912206 # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS 665 # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions.
+system.cpu1.numCycles 177681 # number of cpu cycles simulated
+system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu1.fetch.icacheStallCycles 34028 # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts 233746 # Number of instructions fetch has processed
+system.cpu1.fetch.Branches 43495 # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches 37245 # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles 88254 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles 3762 # Number of cycles fetch has spent squashing
+system.cpu1.fetch.BlockedCycles 42089 # Number of cycles fetch has spent blocked
+system.cpu1.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.NoActiveThreadStallCycles 7739 # Number of stall cycles due to no active thread to fetch from
+system.cpu1.fetch.PendingTrapStallCycles 785 # Number of stall cycles due to pending traps
+system.cpu1.fetch.CacheLines 25656 # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes 258 # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.rateDist::samples 175306 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean 1.333360 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev 1.985884 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0 87052 49.66% 49.66% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1 46435 26.49% 76.15% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2 9084 5.18% 81.33% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3 3194 1.82% 83.15% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::4 686 0.39% 83.54% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::5 23635 13.48% 97.02% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::6 1173 0.67% 97.69% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::7 772 0.44% 98.13% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::8 3275 1.87% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::total 175306 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate 0.244793 # Number of branch fetches per cycle
+system.cpu1.fetch.rate 1.315537 # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles 41969 # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles 35783 # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles 79597 # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles 7812 # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles 2406 # Number of cycles decode is squashing
+system.cpu1.decode.DecodedInsts 230200 # Number of instructions handled by decode
+system.cpu1.rename.SquashCycles 2406 # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles 42677 # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles 23059 # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles 11946 # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles 72053 # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles 15426 # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts 227940 # Number of instructions processed by rename
+system.cpu1.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LSQFullEvents 19 # Number of times rename has blocked due to LSQ full
+system.cpu1.rename.RenamedOperands 156532 # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups 420697 # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups 420697 # Number of integer rename lookups
+system.cpu1.rename.CommittedMaps 143693 # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps 12839 # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts 1114 # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts 1240 # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts 18203 # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads 60713 # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores 26873 # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads 30033 # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores 21821 # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded 184781 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded 9329 # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued 189617 # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued 108 # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined 10957 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined 10934 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved 690 # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples 175306 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean 1.081634 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev 1.264768 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0 84668 48.30% 48.30% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1 30997 17.68% 65.98% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2 27119 15.47% 81.45% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3 27768 15.84% 97.29% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4 3226 1.84% 99.13% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5 1160 0.66% 99.79% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::6 259 0.15% 99.94% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::7 52 0.03% 99.97% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::8 57 0.03% 100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total 175306 # Number of insts issued each cycle
+system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu 12 4.55% 4.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult 0 0.00% 4.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntDiv 0 0.00% 4.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatAdd 0 0.00% 4.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCmp 0 0.00% 4.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCvt 0 0.00% 4.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatMult 0 0.00% 4.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatDiv 0 0.00% 4.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 4.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAdd 0 0.00% 4.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 4.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAlu 0 0.00% 4.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCmp 0 0.00% 4.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCvt 0 0.00% 4.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMisc 0 0.00% 4.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMult 0 0.00% 4.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 4.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShift 0 0.00% 4.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 4.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 4.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 4.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 4.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 4.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 4.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 4.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 4.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 4.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 4.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead 42 15.91% 20.45% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite 210 79.55% 100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
+system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu 95616 50.43% 50.43% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult 0 0.00% 50.43% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 50.43% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 50.43% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 50.43% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 50.43% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 50.43% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 50.43% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 50.43% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 50.43% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 50.43% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 50.43% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 50.43% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 50.43% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 50.43% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 50.43% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 50.43% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 50.43% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 50.43% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 50.43% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 50.43% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 50.43% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 50.43% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 50.43% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 50.43% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 50.43% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 50.43% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 50.43% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 50.43% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead 67820 35.77% 86.19% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite 26181 13.81% 100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::total 189617 # Type of FU issued
+system.cpu1.iq.rate 1.067177 # Inst issue rate
+system.cpu1.iq.fu_busy_cnt 264 # FU busy when requested
+system.cpu1.iq.fu_busy_rate 0.001392 # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads 554912 # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes 205110 # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses 187814 # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
+system.cpu1.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
+system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
+system.cpu1.iq.int_alu_accesses 189881 # Number of integer alu accesses
+system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses
+system.cpu1.iew.lsq.thread0.forwLoads 21562 # Number of loads that had data forwarded from stores
+system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
+system.cpu1.iew.lsq.thread0.squashedLoads 2474 # Number of loads squashed
+system.cpu1.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation 43 # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores 1439 # Number of stores squashed
+system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
+system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
+system.cpu1.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
+system.cpu1.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
+system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
+system.cpu1.iew.iewSquashCycles 2406 # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles 736 # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles 43 # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts 225068 # Number of instructions dispatched to IQ
+system.cpu1.iew.iewDispSquashedInsts 373 # Number of squashed instructions skipped by dispatch
+system.cpu1.iew.iewDispLoadInsts 60713 # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts 26873 # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts 1076 # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents 42 # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
+system.cpu1.iew.memOrderViolationEvents 43 # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect 453 # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect 939 # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts 1392 # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts 188449 # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts 59619 # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts 1168 # Number of squashed instructions skipped in execute
+system.cpu1.iew.exec_swp 0 # number of swp insts executed
+system.cpu1.iew.exec_nop 30958 # number of nop insts executed
+system.cpu1.iew.exec_refs 85720 # number of memory reference insts executed
+system.cpu1.iew.exec_branches 40129 # Number of branches executed
+system.cpu1.iew.exec_stores 26101 # Number of stores executed
+system.cpu1.iew.exec_rate 1.060603 # Inst execution rate
+system.cpu1.iew.wb_sent 188127 # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count 187814 # cumulative count of insts written-back
+system.cpu1.iew.wb_producers 102456 # num instructions producing a value
+system.cpu1.iew.wb_consumers 107134 # num instructions consuming a value
+system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
+system.cpu1.iew.wb_rate 1.057029 # insts written-back per cycle
+system.cpu1.iew.wb_fanout 0.956335 # average fanout of values written-back
+system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu1.commit.commitSquashedInsts 12618 # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls 8639 # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts 1279 # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples 165161 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean 1.286212 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev 1.860966 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0 85256 51.62% 51.62% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1 38272 23.17% 74.79% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2 6084 3.68% 78.48% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3 9527 5.77% 84.24% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4 1571 0.95% 85.20% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5 22201 13.44% 98.64% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6 436 0.26% 98.90% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7 1006 0.61% 99.51% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8 808 0.49% 100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::total 165161 # Number of insts commited each cycle
+system.cpu1.commit.committedInsts 212432 # Number of instructions committed
+system.cpu1.commit.committedOps 212432 # Number of ops (including micro ops) committed
+system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
+system.cpu1.commit.refs 83673 # Number of memory references committed
+system.cpu1.commit.loads 58239 # Number of loads committed
+system.cpu1.commit.membars 7917 # Number of memory barriers committed
+system.cpu1.commit.branches 39308 # Number of branches committed
+system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions.
+system.cpu1.commit.int_insts 145097 # Number of committed integer instructions.
+system.cpu1.commit.function_calls 322 # Number of function calls committed.
+system.cpu1.commit.bw_lim_events 808 # number cycles where commit BW limit reached
+system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits
+system.cpu1.rob.rob_reads 388816 # The number of ROB reads
+system.cpu1.rob.rob_writes 452512 # The number of ROB writes
+system.cpu1.timesIdled 218 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu1.idleCycles 2375 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu1.quiesceCycles 43927 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.committedInsts 174425 # Number of Instructions Simulated
+system.cpu1.committedOps 174425 # Number of Ops (including micro ops) Simulated
+system.cpu1.committedInsts_total 174425 # Number of Instructions Simulated
+system.cpu1.cpi 1.018667 # CPI: Cycles Per Instruction
+system.cpu1.cpi_total 1.018667 # CPI: Total CPI of All Threads
+system.cpu1.ipc 0.981675 # IPC: Instructions Per Cycle
+system.cpu1.ipc_total 0.981675 # IPC: Total IPC of All Threads
+system.cpu1.int_regfile_reads 315718 # number of integer regfile reads
+system.cpu1.int_regfile_writes 148477 # number of integer regfile writes
+system.cpu1.fp_regfile_writes 64 # number of floating regfile writes
+system.cpu1.misc_regfile_reads 87269 # number of misc regfile reads
+system.cpu1.misc_regfile_writes 648 # number of misc regfile writes
+system.cpu1.icache.tags.replacements 318 # number of replacements
+system.cpu1.icache.tags.tagsinuse 79.958659 # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs 25178 # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs 428 # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs 58.827103 # Average number of references to valid blocks.
+system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu1.icache.tags.occ_blocks::cpu1.inst 79.958659 # Average occupied blocks per requestor
+system.cpu1.icache.tags.occ_percent::cpu1.inst 0.156169 # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_percent::total 0.156169 # Average percentage of cache occupancy
+system.cpu1.icache.ReadReq_hits::cpu1.inst 25178 # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total 25178 # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst 25178 # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total 25178 # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst 25178 # number of overall hits
+system.cpu1.icache.overall_hits::total 25178 # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst 478 # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total 478 # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst 478 # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total 478 # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst 478 # number of overall misses
+system.cpu1.icache.overall_misses::total 478 # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7224243 # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total 7224243 # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst 7224243 # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total 7224243 # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst 7224243 # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total 7224243 # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst 25656 # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total 25656 # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst 25656 # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total 25656 # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst 25656 # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total 25656 # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.018631 # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total 0.018631 # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst 0.018631 # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total 0.018631 # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst 0.018631 # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total 0.018631 # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15113.479079 # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total 15113.479079 # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15113.479079 # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total 15113.479079 # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15113.479079 # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total 15113.479079 # average overall miss latency
+system.cpu1.icache.blocked_cycles::no_mshrs 26 # number of cycles access was blocked
+system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu1.icache.blocked::no_mshrs 2 # number of cycles access was blocked
+system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_mshrs 13 # average number of cycles each access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu1.icache.fast_writes 0 # number of fast writes performed
+system.cpu1.icache.cache_copies 0 # number of cache copies performed
+system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 50 # number of ReadReq MSHR hits
+system.cpu1.icache.ReadReq_mshr_hits::total 50 # number of ReadReq MSHR hits
+system.cpu1.icache.demand_mshr_hits::cpu1.inst 50 # number of demand (read+write) MSHR hits
+system.cpu1.icache.demand_mshr_hits::total 50 # number of demand (read+write) MSHR hits
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+system.cpu1.icache.overall_mshr_hits::total 50 # number of overall MSHR hits
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 428 # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::total 428 # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses::cpu1.inst 428 # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses::total 428 # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses::cpu1.inst 428 # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_misses::total 428 # number of overall MSHR misses
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5769006 # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total 5769006 # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5769006 # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total 5769006 # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5769006 # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total 5769006 # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016682 # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.016682 # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.016682 # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total 0.016682 # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.016682 # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total 0.016682 # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13478.985981 # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13478.985981 # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13478.985981 # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total 13478.985981 # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13478.985981 # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total 13478.985981 # average overall mshr miss latency
+system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu1.dcache.tags.replacements 0 # number of replacements
+system.cpu1.dcache.tags.tagsinuse 24.742100 # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs 31558 # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs 1088.206897 # Average number of references to valid blocks.
+system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.tags.occ_blocks::cpu1.data 24.742100 # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.data 0.048324 # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total 0.048324 # Average percentage of cache occupancy
+system.cpu1.dcache.ReadReq_hits::cpu1.data 37722 # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total 37722 # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data 25226 # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total 25226 # number of WriteReq hits
+system.cpu1.dcache.SwapReq_hits::cpu1.data 16 # number of SwapReq hits
+system.cpu1.dcache.SwapReq_hits::total 16 # number of SwapReq hits
+system.cpu1.dcache.demand_hits::cpu1.data 62948 # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total 62948 # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data 62948 # number of overall hits
+system.cpu1.dcache.overall_hits::total 62948 # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data 319 # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total 319 # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data 132 # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total 132 # number of WriteReq misses
+system.cpu1.dcache.SwapReq_misses::cpu1.data 60 # number of SwapReq misses
+system.cpu1.dcache.SwapReq_misses::total 60 # number of SwapReq misses
+system.cpu1.dcache.demand_misses::cpu1.data 451 # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total 451 # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data 451 # number of overall misses
+system.cpu1.dcache.overall_misses::total 451 # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3919891 # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total 3919891 # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2617261 # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total 2617261 # number of WriteReq miss cycles
+system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 548504 # number of SwapReq miss cycles
+system.cpu1.dcache.SwapReq_miss_latency::total 548504 # number of SwapReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data 6537152 # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total 6537152 # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data 6537152 # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total 6537152 # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data 38041 # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total 38041 # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data 25358 # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total 25358 # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.SwapReq_accesses::cpu1.data 76 # number of SwapReq accesses(hits+misses)
+system.cpu1.dcache.SwapReq_accesses::total 76 # number of SwapReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data 63399 # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total 63399 # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data 63399 # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total 63399 # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.008386 # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total 0.008386 # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.005205 # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total 0.005205 # miss rate for WriteReq accesses
+system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.789474 # miss rate for SwapReq accesses
+system.cpu1.dcache.SwapReq_miss_rate::total 0.789474 # miss rate for SwapReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data 0.007114 # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total 0.007114 # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data 0.007114 # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total 0.007114 # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12288.059561 # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 12288.059561 # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 19827.734848 # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 19827.734848 # average WriteReq miss latency
+system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 9141.733333 # average SwapReq miss latency
+system.cpu1.dcache.SwapReq_avg_miss_latency::total 9141.733333 # average SwapReq miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14494.793792 # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 14494.793792 # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14494.793792 # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 14494.793792 # average overall miss latency
+system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu1.dcache.fast_writes 0 # number of fast writes performed
+system.cpu1.dcache.cache_copies 0 # number of cache copies performed
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 154 # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total 154 # number of ReadReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 32 # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::total 32 # number of WriteReq MSHR hits
+system.cpu1.dcache.demand_mshr_hits::cpu1.data 186 # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_hits::total 186 # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits::cpu1.data 186 # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_hits::total 186 # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 165 # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total 165 # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 100 # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total 100 # number of WriteReq MSHR misses
+system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 60 # number of SwapReq MSHR misses
+system.cpu1.dcache.SwapReq_mshr_misses::total 60 # number of SwapReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data 265 # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total 265 # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data 265 # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total 265 # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1138770 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1138770 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1290739 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1290739 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 428496 # number of SwapReq MSHR miss cycles
+system.cpu1.dcache.SwapReq_mshr_miss_latency::total 428496 # number of SwapReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2429509 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total 2429509 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2429509 # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total 2429509 # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.004337 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.004337 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.003944 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.003944 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.789474 # mshr miss rate for SwapReq accesses
+system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.789474 # mshr miss rate for SwapReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.004180 # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total 0.004180 # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.004180 # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total 0.004180 # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 6901.636364 # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 6901.636364 # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 12907.390000 # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 12907.390000 # average WriteReq mshr miss latency
+system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 7141.600000 # average SwapReq mshr miss latency
+system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 7141.600000 # average SwapReq mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 9167.958491 # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 9167.958491 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 9167.958491 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 9167.958491 # average overall mshr miss latency
+system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu2.branchPred.lookups 51236 # Number of BP lookups
+system.cpu2.branchPred.condPredicted 48519 # Number of conditional branches predicted
+system.cpu2.branchPred.condIncorrect 1308 # Number of conditional branches incorrect
+system.cpu2.branchPred.BTBLookups 45052 # Number of BTB lookups
+system.cpu2.branchPred.BTBHits 44357 # Number of BTB hits
+system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu2.branchPred.BTBHitPct 98.457338 # BTB Hit Percentage
+system.cpu2.branchPred.usedRAS 684 # Number of times the RAS was used to get a target.
+system.cpu2.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions.
+system.cpu2.numCycles 177316 # number of cpu cycles simulated
+system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu2.fetch.icacheStallCycles 28846 # Number of cycles fetch is stalled on an Icache miss
+system.cpu2.fetch.Insts 286216 # Number of instructions fetch has processed
+system.cpu2.fetch.Branches 51236 # Number of branches that fetch encountered
+system.cpu2.fetch.predictedBranches 45041 # Number of branches that fetch has predicted taken
+system.cpu2.fetch.Cycles 100902 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu2.fetch.SquashCycles 3805 # Number of cycles fetch has spent squashing
+system.cpu2.fetch.BlockedCycles 31210 # Number of cycles fetch has spent blocked
+system.cpu2.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu2.fetch.NoActiveThreadStallCycles 7739 # Number of stall cycles due to no active thread to fetch from
+system.cpu2.fetch.PendingTrapStallCycles 775 # Number of stall cycles due to pending traps
+system.cpu2.fetch.CacheLines 19767 # Number of cache lines fetched
+system.cpu2.fetch.IcacheSquashes 276 # Number of outstanding Icache misses that were squashed
+system.cpu2.fetch.rateDist::samples 171898 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::mean 1.665034 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::stdev 2.139289 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::0 70996 41.30% 41.30% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::1 51338 29.87% 71.17% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::2 6125 3.56% 74.73% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::3 3190 1.86% 76.59% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::4 695 0.40% 76.99% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::5 34353 19.98% 96.97% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::6 1162 0.68% 97.65% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::7 771 0.45% 98.10% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::8 3268 1.90% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::total 171898 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.branchRate 0.288953 # Number of branch fetches per cycle
+system.cpu2.fetch.rate 1.614158 # Number of inst fetches per cycle
+system.cpu2.decode.IdleCycles 33770 # Number of cycles decode is idle
+system.cpu2.decode.BlockedCycles 27924 # Number of cycles decode is blocked
+system.cpu2.decode.RunCycles 94988 # Number of cycles decode is running
+system.cpu2.decode.UnblockCycles 5055 # Number of cycles decode is unblocking
+system.cpu2.decode.SquashCycles 2422 # Number of cycles decode is squashing
+system.cpu2.decode.DecodedInsts 282690 # Number of instructions handled by decode
+system.cpu2.rename.SquashCycles 2422 # Number of cycles rename is squashing
+system.cpu2.rename.IdleCycles 34480 # Number of cycles rename is idle
+system.cpu2.rename.BlockCycles 14885 # Number of cycles rename is blocking
+system.cpu2.rename.serializeStallCycles 12280 # count of cycles rename stalled for serializing inst
+system.cpu2.rename.RunCycles 90190 # Number of cycles rename is running
+system.cpu2.rename.UnblockCycles 9902 # Number of cycles rename is unblocking
+system.cpu2.rename.RenamedInsts 280450 # Number of instructions processed by rename
+system.cpu2.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full
+system.cpu2.rename.LSQFullEvents 24 # Number of times rename has blocked due to LSQ full
+system.cpu2.rename.RenamedOperands 196553 # Number of destination operands rename has renamed
+system.cpu2.rename.RenameLookups 537620 # Number of register rename lookups that rename has made
+system.cpu2.rename.int_rename_lookups 537620 # Number of integer rename lookups
+system.cpu2.rename.CommittedMaps 183508 # Number of HB maps that are committed
+system.cpu2.rename.UndoneMaps 13045 # Number of HB maps that are undone due to squashing
+system.cpu2.rename.serializingInsts 1112 # count of serializing insts renamed
+system.cpu2.rename.tempSerializingInsts 1237 # count of temporary serializing insts renamed
+system.cpu2.rename.skidInsts 12513 # count of insts added to the skid buffer
+system.cpu2.memDep0.insertedLoads 79191 # Number of loads inserted to the mem dependence unit.
+system.cpu2.memDep0.insertedStores 37564 # Number of stores inserted to the mem dependence unit.
+system.cpu2.memDep0.conflictingLoads 37796 # Number of conflicting loads.
+system.cpu2.memDep0.conflictingStores 32512 # Number of conflicting stores.
+system.cpu2.iq.iqInstsAdded 232563 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu2.iq.iqNonSpecInstsAdded 6341 # Number of non-speculative instructions added to the IQ
+system.cpu2.iq.iqInstsIssued 234561 # Number of instructions issued
+system.cpu2.iq.iqSquashedInstsIssued 83 # Number of squashed instructions issued
+system.cpu2.iq.iqSquashedInstsExamined 11040 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu2.iq.iqSquashedOperandsExamined 10888 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu2.iq.iqSquashedNonSpecRemoved 602 # Number of squashed non-spec instructions that were removed
+system.cpu2.iq.issued_per_cycle::samples 171898 # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::mean 1.364536 # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::stdev 1.313534 # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::0 68441 39.81% 39.81% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::1 22472 13.07% 52.89% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::2 37788 21.98% 74.87% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::3 38389 22.33% 97.20% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::4 3254 1.89% 99.10% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::5 1164 0.68% 99.77% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::6 277 0.16% 99.93% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::7 56 0.03% 99.97% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::8 57 0.03% 100.00% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::total 171898 # Number of insts issued each cycle
+system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntAlu 17 6.14% 6.14% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntMult 0 0.00% 6.14% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntDiv 0 0.00% 6.14% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatAdd 0 0.00% 6.14% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCmp 0 0.00% 6.14% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCvt 0 0.00% 6.14% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatMult 0 0.00% 6.14% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatDiv 0 0.00% 6.14% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 6.14% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAdd 0 0.00% 6.14% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 6.14% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAlu 0 0.00% 6.14% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCmp 0 0.00% 6.14% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCvt 0 0.00% 6.14% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMisc 0 0.00% 6.14% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMult 0 0.00% 6.14% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 6.14% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShift 0 0.00% 6.14% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 6.14% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 6.14% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 6.14% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 6.14% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 6.14% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 6.14% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 6.14% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 6.14% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 6.14% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.14% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 6.14% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemRead 50 18.05% 24.19% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemWrite 210 75.81% 100.00% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
+system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
+system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntAlu 114217 48.69% 48.69% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntMult 0 0.00% 48.69% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 48.69% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 48.69% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 48.69% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 48.69% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 48.69% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 48.69% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 48.69% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 48.69% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 48.69% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 48.69% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 48.69% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 48.69% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 48.69% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 48.69% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 48.69% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 48.69% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.69% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 48.69% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.69% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.69% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.69% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.69% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.69% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.69% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 48.69% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.69% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.69% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemRead 83468 35.58% 84.28% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemWrite 36876 15.72% 100.00% # Type of FU issued
+system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
+system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
+system.cpu2.iq.FU_type_0::total 234561 # Type of FU issued
+system.cpu2.iq.rate 1.322842 # Inst issue rate
+system.cpu2.iq.fu_busy_cnt 277 # FU busy when requested
+system.cpu2.iq.fu_busy_rate 0.001181 # FU busy rate (busy events/executed inst)
+system.cpu2.iq.int_inst_queue_reads 641380 # Number of integer instruction queue reads
+system.cpu2.iq.int_inst_queue_writes 249989 # Number of integer instruction queue writes
+system.cpu2.iq.int_inst_queue_wakeup_accesses 232740 # Number of integer instruction queue wakeup accesses
+system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
+system.cpu2.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
+system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
+system.cpu2.iq.int_alu_accesses 234838 # Number of integer alu accesses
+system.cpu2.iq.fp_alu_accesses 0 # Number of floating point alu accesses
+system.cpu2.iew.lsq.thread0.forwLoads 32248 # Number of loads that had data forwarded from stores
+system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
+system.cpu2.iew.lsq.thread0.squashedLoads 2484 # Number of loads squashed
+system.cpu2.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
+system.cpu2.iew.lsq.thread0.memOrderViolation 45 # Number of memory ordering violations
+system.cpu2.iew.lsq.thread0.squashedStores 1465 # Number of stores squashed
+system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
+system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
+system.cpu2.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
+system.cpu2.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
+system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle
+system.cpu2.iew.iewSquashCycles 2422 # Number of cycles IEW is squashing
+system.cpu2.iew.iewBlockCycles 851 # Number of cycles IEW is blocking
+system.cpu2.iew.iewUnblockCycles 46 # Number of cycles IEW is unblocking
+system.cpu2.iew.iewDispatchedInsts 277610 # Number of instructions dispatched to IQ
+system.cpu2.iew.iewDispSquashedInsts 365 # Number of squashed instructions skipped by dispatch
+system.cpu2.iew.iewDispLoadInsts 79191 # Number of dispatched load instructions
+system.cpu2.iew.iewDispStoreInsts 37564 # Number of dispatched store instructions
+system.cpu2.iew.iewDispNonSpecInsts 1068 # Number of dispatched non-speculative instructions
+system.cpu2.iew.iewIQFullEvents 46 # Number of times the IQ has become full, causing a stall
+system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
+system.cpu2.iew.memOrderViolationEvents 45 # Number of memory order violations
+system.cpu2.iew.predictedTakenIncorrect 466 # Number of branches that were predicted taken incorrectly
+system.cpu2.iew.predictedNotTakenIncorrect 970 # Number of branches that were predicted not taken incorrectly
+system.cpu2.iew.branchMispredicts 1436 # Number of branch mispredicts detected at execute
+system.cpu2.iew.iewExecutedInsts 233403 # Number of executed instructions
+system.cpu2.iew.iewExecLoadInsts 78158 # Number of load instructions executed
+system.cpu2.iew.iewExecSquashedInsts 1158 # Number of squashed instructions skipped in execute
+system.cpu2.iew.exec_swp 0 # number of swp insts executed
+system.cpu2.iew.exec_nop 38706 # number of nop insts executed
+system.cpu2.iew.exec_refs 114950 # number of memory reference insts executed
+system.cpu2.iew.exec_branches 47927 # Number of branches executed
+system.cpu2.iew.exec_stores 36792 # Number of stores executed
+system.cpu2.iew.exec_rate 1.316311 # Inst execution rate
+system.cpu2.iew.wb_sent 233070 # cumulative count of insts sent to commit
+system.cpu2.iew.wb_count 232740 # cumulative count of insts written-back
+system.cpu2.iew.wb_producers 131730 # num instructions producing a value
+system.cpu2.iew.wb_consumers 136434 # num instructions consuming a value
+system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
+system.cpu2.iew.wb_rate 1.312572 # insts written-back per cycle
+system.cpu2.iew.wb_fanout 0.965522 # average fanout of values written-back
+system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu2.commit.commitSquashedInsts 12692 # The number of squashed insts skipped by commit
+system.cpu2.commit.commitNonSpecStalls 5739 # The number of times commit has been forced to stall to communicate backwards
+system.cpu2.commit.branchMispredicts 1308 # The number of times a branch was mispredicted
+system.cpu2.commit.committed_per_cycle::samples 161737 # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::mean 1.637943 # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::stdev 2.020354 # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::0 66243 40.96% 40.96% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::1 46082 28.49% 69.45% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::2 6100 3.77% 73.22% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::3 6659 4.12% 77.34% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::4 1556 0.96% 78.30% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::5 32794 20.28% 98.58% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::6 480 0.30% 98.87% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::7 1001 0.62% 99.49% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::8 822 0.51% 100.00% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::total 161737 # Number of insts commited each cycle
+system.cpu2.commit.committedInsts 264916 # Number of instructions committed
+system.cpu2.commit.committedOps 264916 # Number of ops (including micro ops) committed
+system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed
+system.cpu2.commit.refs 112806 # Number of memory references committed
+system.cpu2.commit.loads 76707 # Number of loads committed
+system.cpu2.commit.membars 5024 # Number of memory barriers committed
+system.cpu2.commit.branches 47088 # Number of branches committed
+system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions.
+system.cpu2.commit.int_insts 182014 # Number of committed integer instructions.
+system.cpu2.commit.function_calls 322 # Number of function calls committed.
+system.cpu2.commit.bw_lim_events 822 # number cycles where commit BW limit reached
+system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits
+system.cpu2.rob.rob_reads 437936 # The number of ROB reads
+system.cpu2.rob.rob_writes 557643 # The number of ROB writes
+system.cpu2.timesIdled 224 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu2.idleCycles 5418 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu2.quiesceCycles 44292 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu2.committedInsts 222015 # Number of Instructions Simulated
+system.cpu2.committedOps 222015 # Number of Ops (including micro ops) Simulated
+system.cpu2.committedInsts_total 222015 # Number of Instructions Simulated
+system.cpu2.cpi 0.798667 # CPI: Cycles Per Instruction
+system.cpu2.cpi_total 0.798667 # CPI: Total CPI of All Threads
+system.cpu2.ipc 1.252087 # IPC: Instructions Per Cycle
+system.cpu2.ipc_total 1.252087 # IPC: Total IPC of All Threads
+system.cpu2.int_regfile_reads 403571 # number of integer regfile reads
+system.cpu2.int_regfile_writes 188531 # number of integer regfile writes
+system.cpu2.fp_regfile_writes 64 # number of floating regfile writes
+system.cpu2.misc_regfile_reads 116514 # number of misc regfile reads
+system.cpu2.misc_regfile_writes 648 # number of misc regfile writes
+system.cpu2.icache.tags.replacements 317 # number of replacements
+system.cpu2.icache.tags.tagsinuse 82.351710 # Cycle average of tags in use
+system.cpu2.icache.tags.total_refs 19274 # Total number of references to valid blocks.
+system.cpu2.icache.tags.sampled_refs 425 # Sample count of references to valid blocks.
+system.cpu2.icache.tags.avg_refs 45.350588 # Average number of references to valid blocks.
+system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu2.icache.tags.occ_blocks::cpu2.inst 82.351710 # Average occupied blocks per requestor
+system.cpu2.icache.tags.occ_percent::cpu2.inst 0.160843 # Average percentage of cache occupancy
+system.cpu2.icache.tags.occ_percent::total 0.160843 # Average percentage of cache occupancy
+system.cpu2.icache.ReadReq_hits::cpu2.inst 19274 # number of ReadReq hits
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+system.cpu2.icache.demand_hits::cpu2.inst 19274 # number of demand (read+write) hits
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+system.cpu2.icache.overall_hits::total 19274 # number of overall hits
+system.cpu2.icache.ReadReq_misses::cpu2.inst 493 # number of ReadReq misses
+system.cpu2.icache.ReadReq_misses::total 493 # number of ReadReq misses
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+system.cpu2.icache.overall_misses::total 493 # number of overall misses
+system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 11521742 # number of ReadReq miss cycles
+system.cpu2.icache.ReadReq_miss_latency::total 11521742 # number of ReadReq miss cycles
+system.cpu2.icache.demand_miss_latency::cpu2.inst 11521742 # number of demand (read+write) miss cycles
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+system.cpu2.icache.overall_miss_latency::cpu2.inst 11521742 # number of overall miss cycles
+system.cpu2.icache.overall_miss_latency::total 11521742 # number of overall miss cycles
+system.cpu2.icache.ReadReq_accesses::cpu2.inst 19767 # number of ReadReq accesses(hits+misses)
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+system.cpu2.icache.ReadReq_avg_miss_latency::total 23370.673428 # average ReadReq miss latency
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+system.cpu2.icache.demand_avg_miss_latency::total 23370.673428 # average overall miss latency
+system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 23370.673428 # average overall miss latency
+system.cpu2.icache.overall_avg_miss_latency::total 23370.673428 # average overall miss latency
+system.cpu2.icache.blocked_cycles::no_mshrs 85 # number of cycles access was blocked
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+system.cpu2.icache.blocked::no_mshrs 1 # number of cycles access was blocked
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+system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 21651.185882 # average overall mshr miss latency
+system.cpu2.icache.overall_avg_mshr_miss_latency::total 21651.185882 # average overall mshr miss latency
+system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu2.dcache.tags.replacements 0 # number of replacements
+system.cpu2.dcache.tags.tagsinuse 26.191522 # Cycle average of tags in use
+system.cpu2.dcache.tags.total_refs 42135 # Total number of references to valid blocks.
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+system.cpu2.dcache.tags.avg_refs 1504.821429 # Average number of references to valid blocks.
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+system.cpu2.dcache.tags.occ_blocks::cpu2.data 26.191522 # Average occupied blocks per requestor
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+system.cpu2.dcache.tags.occ_percent::total 0.051155 # Average percentage of cache occupancy
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+system.cpu2.dcache.demand_avg_miss_latency::total 17874.870637 # average overall miss latency
+system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 17874.870637 # average overall miss latency
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+system.cpu2.dcache.overall_mshr_hits::total 216 # number of overall MSHR hits
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+system.cpu2.dcache.overall_mshr_misses::total 271 # number of overall MSHR misses
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+system.cpu2.dcache.demand_mshr_miss_latency::total 3041020 # number of demand (read+write) MSHR miss cycles
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+system.cpu2.dcache.overall_mshr_miss_latency::total 3041020 # number of overall MSHR miss cycles
+system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003530 # mshr miss rate for ReadReq accesses
+system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003530 # mshr miss rate for ReadReq accesses
+system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.003025 # mshr miss rate for WriteReq accesses
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+system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.826087 # mshr miss rate for SwapReq accesses
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+system.cpu2.dcache.demand_mshr_miss_rate::total 0.003308 # mshr miss rate for demand accesses
+system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003308 # mshr miss rate for overall accesses
+system.cpu2.dcache.overall_mshr_miss_rate::total 0.003308 # mshr miss rate for overall accesses
+system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 9424.567901 # average ReadReq mshr miss latency
+system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 9424.567901 # average ReadReq mshr miss latency
+system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 13892.110092 # average WriteReq mshr miss latency
+system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 13892.110092 # average WriteReq mshr miss latency
+system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 8087.596491 # average SwapReq mshr miss latency
+system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 8087.596491 # average SwapReq mshr miss latency
+system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 11221.476015 # average overall mshr miss latency
+system.cpu2.dcache.demand_avg_mshr_miss_latency::total 11221.476015 # average overall mshr miss latency
+system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 11221.476015 # average overall mshr miss latency
+system.cpu2.dcache.overall_avg_mshr_miss_latency::total 11221.476015 # average overall mshr miss latency
+system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu3.branchPred.lookups 56317 # Number of BP lookups
+system.cpu3.branchPred.condPredicted 53592 # Number of conditional branches predicted
+system.cpu3.branchPred.condIncorrect 1257 # Number of conditional branches incorrect
+system.cpu3.branchPred.BTBLookups 50318 # Number of BTB lookups
+system.cpu3.branchPred.BTBHits 49441 # Number of BTB hits
+system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu3.branchPred.BTBHitPct 98.257085 # BTB Hit Percentage
+system.cpu3.branchPred.usedRAS 649 # Number of times the RAS was used to get a target.
+system.cpu3.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions.
+system.cpu3.numCycles 176970 # number of cpu cycles simulated
+system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu3.fetch.icacheStallCycles 26467 # Number of cycles fetch is stalled on an Icache miss
+system.cpu3.fetch.Insts 318235 # Number of instructions fetch has processed
+system.cpu3.fetch.Branches 56317 # Number of branches that fetch encountered
+system.cpu3.fetch.predictedBranches 50090 # Number of branches that fetch has predicted taken
+system.cpu3.fetch.Cycles 110248 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu3.fetch.SquashCycles 3629 # Number of cycles fetch has spent squashing
+system.cpu3.fetch.BlockedCycles 28039 # Number of cycles fetch has spent blocked
+system.cpu3.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu3.fetch.NoActiveThreadStallCycles 7739 # Number of stall cycles due to no active thread to fetch from
+system.cpu3.fetch.PendingTrapStallCycles 790 # Number of stall cycles due to pending traps
+system.cpu3.fetch.CacheLines 18199 # Number of cache lines fetched
+system.cpu3.fetch.IcacheSquashes 258 # Number of outstanding Icache misses that were squashed
+system.cpu3.fetch.rateDist::samples 175582 # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::mean 1.812458 # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::stdev 2.180606 # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::0 65334 37.21% 37.21% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::1 55610 31.67% 68.88% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::2 5389 3.07% 71.95% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::3 3177 1.81% 73.76% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::4 669 0.38% 74.14% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::5 40119 22.85% 96.99% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::6 1237 0.70% 97.70% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::7 753 0.43% 98.12% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::8 3294 1.88% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::total 175582 # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.branchRate 0.318229 # Number of branch fetches per cycle
+system.cpu3.fetch.rate 1.798243 # Number of inst fetches per cycle
+system.cpu3.decode.IdleCycles 31057 # Number of cycles decode is idle
+system.cpu3.decode.BlockedCycles 25106 # Number of cycles decode is blocked
+system.cpu3.decode.RunCycles 104911 # Number of cycles decode is running
+system.cpu3.decode.UnblockCycles 4475 # Number of cycles decode is unblocking
+system.cpu3.decode.SquashCycles 2294 # Number of cycles decode is squashing
+system.cpu3.decode.DecodedInsts 314540 # Number of instructions handled by decode
+system.cpu3.rename.SquashCycles 2294 # Number of cycles rename is squashing
+system.cpu3.rename.IdleCycles 31713 # Number of cycles rename is idle
+system.cpu3.rename.BlockCycles 12844 # Number of cycles rename is blocking
+system.cpu3.rename.serializeStallCycles 11527 # count of cycles rename stalled for serializing inst
+system.cpu3.rename.RunCycles 100723 # Number of cycles rename is running
+system.cpu3.rename.UnblockCycles 8742 # Number of cycles rename is unblocking
+system.cpu3.rename.RenamedInsts 312369 # Number of instructions processed by rename
+system.cpu3.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full
+system.cpu3.rename.LSQFullEvents 22 # Number of times rename has blocked due to LSQ full
+system.cpu3.rename.RenamedOperands 219058 # Number of destination operands rename has renamed
+system.cpu3.rename.RenameLookups 604346 # Number of register rename lookups that rename has made
+system.cpu3.rename.int_rename_lookups 604346 # Number of integer rename lookups
+system.cpu3.rename.CommittedMaps 206290 # Number of HB maps that are committed
+system.cpu3.rename.UndoneMaps 12768 # Number of HB maps that are undone due to squashing
+system.cpu3.rename.serializingInsts 1082 # count of serializing insts renamed
+system.cpu3.rename.tempSerializingInsts 1202 # count of temporary serializing insts renamed
+system.cpu3.rename.skidInsts 11332 # count of insts added to the skid buffer
+system.cpu3.memDep0.insertedLoads 90084 # Number of loads inserted to the mem dependence unit.
+system.cpu3.memDep0.insertedStores 43367 # Number of stores inserted to the mem dependence unit.
+system.cpu3.memDep0.conflictingLoads 42837 # Number of conflicting loads.
+system.cpu3.memDep0.conflictingStores 38342 # Number of conflicting stores.
+system.cpu3.iq.iqInstsAdded 260031 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu3.iq.iqNonSpecInstsAdded 5573 # Number of non-speculative instructions added to the IQ
+system.cpu3.iq.iqInstsIssued 261645 # Number of instructions issued
+system.cpu3.iq.iqSquashedInstsIssued 62 # Number of squashed instructions issued
+system.cpu3.iq.iqSquashedInstsExamined 10424 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu3.iq.iqSquashedOperandsExamined 10297 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu3.iq.iqSquashedNonSpecRemoved 498 # Number of squashed non-spec instructions that were removed
+system.cpu3.iq.issued_per_cycle::samples 175582 # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::mean 1.490158 # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::stdev 1.307816 # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::0 62519 35.61% 35.61% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::1 20435 11.64% 47.25% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::2 43580 24.82% 72.07% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::3 44218 25.18% 97.25% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::4 3288 1.87% 99.12% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::5 1176 0.67% 99.79% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::6 257 0.15% 99.94% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::7 50 0.03% 99.97% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::8 59 0.03% 100.00% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::total 175582 # Number of insts issued each cycle
+system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
+system.cpu3.iq.fu_full::IntAlu 17 6.25% 6.25% # attempts to use FU when none available
+system.cpu3.iq.fu_full::IntMult 0 0.00% 6.25% # attempts to use FU when none available
+system.cpu3.iq.fu_full::IntDiv 0 0.00% 6.25% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatAdd 0 0.00% 6.25% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatCmp 0 0.00% 6.25% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatCvt 0 0.00% 6.25% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatMult 0 0.00% 6.25% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatDiv 0 0.00% 6.25% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 6.25% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdAdd 0 0.00% 6.25% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 6.25% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdAlu 0 0.00% 6.25% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdCmp 0 0.00% 6.25% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdCvt 0 0.00% 6.25% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdMisc 0 0.00% 6.25% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdMult 0 0.00% 6.25% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 6.25% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdShift 0 0.00% 6.25% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 6.25% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 6.25% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 6.25% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 6.25% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 6.25% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 6.25% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 6.25% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 6.25% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 6.25% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.25% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 6.25% # attempts to use FU when none available
+system.cpu3.iq.fu_full::MemRead 45 16.54% 22.79% # attempts to use FU when none available
+system.cpu3.iq.fu_full::MemWrite 210 77.21% 100.00% # attempts to use FU when none available
+system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
+system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
+system.cpu3.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
+system.cpu3.iq.FU_type_0::IntAlu 125105 47.81% 47.81% # Type of FU issued
+system.cpu3.iq.FU_type_0::IntMult 0 0.00% 47.81% # Type of FU issued
+system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 47.81% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 47.81% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 47.81% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 47.81% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 47.81% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 47.81% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 47.81% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 47.81% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 47.81% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 47.81% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 47.81% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 47.81% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 47.81% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 47.81% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 47.81% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 47.81% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 47.81% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 47.81% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.81% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.81% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.81% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.81% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.81% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 47.81% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 47.81% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.81% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.81% # Type of FU issued
+system.cpu3.iq.FU_type_0::MemRead 93850 35.87% 83.68% # Type of FU issued
+system.cpu3.iq.FU_type_0::MemWrite 42690 16.32% 100.00% # Type of FU issued
+system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
+system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
+system.cpu3.iq.FU_type_0::total 261645 # Type of FU issued
+system.cpu3.iq.rate 1.478471 # Inst issue rate
+system.cpu3.iq.fu_busy_cnt 272 # FU busy when requested
+system.cpu3.iq.fu_busy_rate 0.001040 # FU busy rate (busy events/executed inst)
+system.cpu3.iq.int_inst_queue_reads 699206 # Number of integer instruction queue reads
+system.cpu3.iq.int_inst_queue_writes 276071 # Number of integer instruction queue writes
+system.cpu3.iq.int_inst_queue_wakeup_accesses 259793 # Number of integer instruction queue wakeup accesses
+system.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
+system.cpu3.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
+system.cpu3.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
+system.cpu3.iq.int_alu_accesses 261917 # Number of integer alu accesses
+system.cpu3.iq.fp_alu_accesses 0 # Number of floating point alu accesses
+system.cpu3.iew.lsq.thread0.forwLoads 38112 # Number of loads that had data forwarded from stores
+system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
+system.cpu3.iew.lsq.thread0.squashedLoads 2309 # Number of loads squashed
+system.cpu3.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
+system.cpu3.iew.lsq.thread0.memOrderViolation 43 # Number of memory ordering violations
+system.cpu3.iew.lsq.thread0.squashedStores 1414 # Number of stores squashed
+system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
+system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
+system.cpu3.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
+system.cpu3.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
+system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle
+system.cpu3.iew.iewSquashCycles 2294 # Number of cycles IEW is squashing
+system.cpu3.iew.iewBlockCycles 580 # Number of cycles IEW is blocking
+system.cpu3.iew.iewUnblockCycles 36 # Number of cycles IEW is unblocking
+system.cpu3.iew.iewDispatchedInsts 309373 # Number of instructions dispatched to IQ
+system.cpu3.iew.iewDispSquashedInsts 369 # Number of squashed instructions skipped by dispatch
+system.cpu3.iew.iewDispLoadInsts 90084 # Number of dispatched load instructions
+system.cpu3.iew.iewDispStoreInsts 43367 # Number of dispatched store instructions
+system.cpu3.iew.iewDispNonSpecInsts 1034 # Number of dispatched non-speculative instructions
+system.cpu3.iew.iewIQFullEvents 36 # Number of times the IQ has become full, causing a stall
+system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
+system.cpu3.iew.memOrderViolationEvents 43 # Number of memory order violations
+system.cpu3.iew.predictedTakenIncorrect 465 # Number of branches that were predicted taken incorrectly
+system.cpu3.iew.predictedNotTakenIncorrect 904 # Number of branches that were predicted not taken incorrectly
+system.cpu3.iew.branchMispredicts 1369 # Number of branch mispredicts detected at execute
+system.cpu3.iew.iewExecutedInsts 260458 # Number of executed instructions
+system.cpu3.iew.iewExecLoadInsts 89199 # Number of load instructions executed
+system.cpu3.iew.iewExecSquashedInsts 1187 # Number of squashed instructions skipped in execute
+system.cpu3.iew.exec_swp 0 # number of swp insts executed
+system.cpu3.iew.exec_nop 43769 # number of nop insts executed
+system.cpu3.iew.exec_refs 131812 # number of memory reference insts executed
+system.cpu3.iew.exec_branches 53091 # Number of branches executed
+system.cpu3.iew.exec_stores 42613 # Number of stores executed
+system.cpu3.iew.exec_rate 1.471764 # Inst execution rate
+system.cpu3.iew.wb_sent 260118 # cumulative count of insts sent to commit
+system.cpu3.iew.wb_count 259793 # cumulative count of insts written-back
+system.cpu3.iew.wb_producers 148532 # num instructions producing a value
+system.cpu3.iew.wb_consumers 153197 # num instructions consuming a value
+system.cpu3.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
+system.cpu3.iew.wb_rate 1.468006 # insts written-back per cycle
+system.cpu3.iew.wb_fanout 0.969549 # average fanout of values written-back
+system.cpu3.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu3.commit.commitSquashedInsts 11915 # The number of squashed insts skipped by commit
+system.cpu3.commit.commitNonSpecStalls 5075 # The number of times commit has been forced to stall to communicate backwards
+system.cpu3.commit.branchMispredicts 1257 # The number of times a branch was mispredicted
+system.cpu3.commit.committed_per_cycle::samples 165549 # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::mean 1.796677 # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::stdev 2.064793 # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::0 59727 36.08% 36.08% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::1 51190 30.92% 67.00% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::2 6085 3.68% 70.68% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::3 6030 3.64% 74.32% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::4 1572 0.95% 75.27% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::5 38600 23.32% 98.58% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::6 530 0.32% 98.90% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::7 1000 0.60% 99.51% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::8 815 0.49% 100.00% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::total 165549 # Number of insts commited each cycle
+system.cpu3.commit.committedInsts 297438 # Number of instructions committed
+system.cpu3.commit.committedOps 297438 # Number of ops (including micro ops) committed
+system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed
+system.cpu3.commit.refs 129728 # Number of memory references committed
+system.cpu3.commit.loads 87775 # Number of loads committed
+system.cpu3.commit.membars 4366 # Number of memory barriers committed
+system.cpu3.commit.branches 52284 # Number of branches committed
+system.cpu3.commit.fp_insts 0 # Number of committed floating point instructions.
+system.cpu3.commit.int_insts 204138 # Number of committed integer instructions.
+system.cpu3.commit.function_calls 322 # Number of function calls committed.
+system.cpu3.commit.bw_lim_events 815 # number cycles where commit BW limit reached
+system.cpu3.commit.bw_limited 0 # number of insts not committed due to BW limits
+system.cpu3.rob.rob_reads 473500 # The number of ROB reads
+system.cpu3.rob.rob_writes 621006 # The number of ROB writes
+system.cpu3.timesIdled 209 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu3.idleCycles 1388 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu3.quiesceCycles 44638 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu3.committedInsts 249993 # Number of Instructions Simulated
+system.cpu3.committedOps 249993 # Number of Ops (including micro ops) Simulated
+system.cpu3.committedInsts_total 249993 # Number of Instructions Simulated
+system.cpu3.cpi 0.707900 # CPI: Cycles Per Instruction
+system.cpu3.cpi_total 0.707900 # CPI: Total CPI of All Threads
+system.cpu3.ipc 1.412629 # IPC: Instructions Per Cycle
+system.cpu3.ipc_total 1.412629 # IPC: Total IPC of All Threads
+system.cpu3.int_regfile_reads 453881 # number of integer regfile reads
+system.cpu3.int_regfile_writes 211087 # number of integer regfile writes
+system.cpu3.fp_regfile_writes 64 # number of floating regfile writes
+system.cpu3.misc_regfile_reads 133368 # number of misc regfile reads
+system.cpu3.misc_regfile_writes 648 # number of misc regfile writes
+system.cpu3.icache.tags.replacements 319 # number of replacements
+system.cpu3.icache.tags.tagsinuse 77.348761 # Cycle average of tags in use
+system.cpu3.icache.tags.total_refs 17724 # Total number of references to valid blocks.
+system.cpu3.icache.tags.sampled_refs 430 # Sample count of references to valid blocks.
+system.cpu3.icache.tags.avg_refs 41.218605 # Average number of references to valid blocks.
+system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu3.icache.tags.occ_blocks::cpu3.inst 77.348761 # Average occupied blocks per requestor
+system.cpu3.icache.tags.occ_percent::cpu3.inst 0.151072 # Average percentage of cache occupancy
+system.cpu3.icache.tags.occ_percent::total 0.151072 # Average percentage of cache occupancy
+system.cpu3.icache.ReadReq_hits::cpu3.inst 17724 # number of ReadReq hits
+system.cpu3.icache.ReadReq_hits::total 17724 # number of ReadReq hits
+system.cpu3.icache.demand_hits::cpu3.inst 17724 # number of demand (read+write) hits
+system.cpu3.icache.demand_hits::total 17724 # number of demand (read+write) hits
+system.cpu3.icache.overall_hits::cpu3.inst 17724 # number of overall hits
+system.cpu3.icache.overall_hits::total 17724 # number of overall hits
+system.cpu3.icache.ReadReq_misses::cpu3.inst 475 # number of ReadReq misses
+system.cpu3.icache.ReadReq_misses::total 475 # number of ReadReq misses
+system.cpu3.icache.demand_misses::cpu3.inst 475 # number of demand (read+write) misses
+system.cpu3.icache.demand_misses::total 475 # number of demand (read+write) misses
+system.cpu3.icache.overall_misses::cpu3.inst 475 # number of overall misses
+system.cpu3.icache.overall_misses::total 475 # number of overall misses
+system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 6467995 # number of ReadReq miss cycles
+system.cpu3.icache.ReadReq_miss_latency::total 6467995 # number of ReadReq miss cycles
+system.cpu3.icache.demand_miss_latency::cpu3.inst 6467995 # number of demand (read+write) miss cycles
+system.cpu3.icache.demand_miss_latency::total 6467995 # number of demand (read+write) miss cycles
+system.cpu3.icache.overall_miss_latency::cpu3.inst 6467995 # number of overall miss cycles
+system.cpu3.icache.overall_miss_latency::total 6467995 # number of overall miss cycles
+system.cpu3.icache.ReadReq_accesses::cpu3.inst 18199 # number of ReadReq accesses(hits+misses)
+system.cpu3.icache.ReadReq_accesses::total 18199 # number of ReadReq accesses(hits+misses)
+system.cpu3.icache.demand_accesses::cpu3.inst 18199 # number of demand (read+write) accesses
+system.cpu3.icache.demand_accesses::total 18199 # number of demand (read+write) accesses
+system.cpu3.icache.overall_accesses::cpu3.inst 18199 # number of overall (read+write) accesses
+system.cpu3.icache.overall_accesses::total 18199 # number of overall (read+write) accesses
+system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.026100 # miss rate for ReadReq accesses
+system.cpu3.icache.ReadReq_miss_rate::total 0.026100 # miss rate for ReadReq accesses
+system.cpu3.icache.demand_miss_rate::cpu3.inst 0.026100 # miss rate for demand accesses
+system.cpu3.icache.demand_miss_rate::total 0.026100 # miss rate for demand accesses
+system.cpu3.icache.overall_miss_rate::cpu3.inst 0.026100 # miss rate for overall accesses
+system.cpu3.icache.overall_miss_rate::total 0.026100 # miss rate for overall accesses
+system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13616.831579 # average ReadReq miss latency
+system.cpu3.icache.ReadReq_avg_miss_latency::total 13616.831579 # average ReadReq miss latency
+system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13616.831579 # average overall miss latency
+system.cpu3.icache.demand_avg_miss_latency::total 13616.831579 # average overall miss latency
+system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13616.831579 # average overall miss latency
+system.cpu3.icache.overall_avg_miss_latency::total 13616.831579 # average overall miss latency
+system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu3.icache.fast_writes 0 # number of fast writes performed
+system.cpu3.icache.cache_copies 0 # number of cache copies performed
+system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 45 # number of ReadReq MSHR hits
+system.cpu3.icache.ReadReq_mshr_hits::total 45 # number of ReadReq MSHR hits
+system.cpu3.icache.demand_mshr_hits::cpu3.inst 45 # number of demand (read+write) MSHR hits
+system.cpu3.icache.demand_mshr_hits::total 45 # number of demand (read+write) MSHR hits
+system.cpu3.icache.overall_mshr_hits::cpu3.inst 45 # number of overall MSHR hits
+system.cpu3.icache.overall_mshr_hits::total 45 # number of overall MSHR hits
+system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 430 # number of ReadReq MSHR misses
+system.cpu3.icache.ReadReq_mshr_misses::total 430 # number of ReadReq MSHR misses
+system.cpu3.icache.demand_mshr_misses::cpu3.inst 430 # number of demand (read+write) MSHR misses
+system.cpu3.icache.demand_mshr_misses::total 430 # number of demand (read+write) MSHR misses
+system.cpu3.icache.overall_mshr_misses::cpu3.inst 430 # number of overall MSHR misses
+system.cpu3.icache.overall_mshr_misses::total 430 # number of overall MSHR misses
+system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 5219755 # number of ReadReq MSHR miss cycles
+system.cpu3.icache.ReadReq_mshr_miss_latency::total 5219755 # number of ReadReq MSHR miss cycles
+system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 5219755 # number of demand (read+write) MSHR miss cycles
+system.cpu3.icache.demand_mshr_miss_latency::total 5219755 # number of demand (read+write) MSHR miss cycles
+system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 5219755 # number of overall MSHR miss cycles
+system.cpu3.icache.overall_mshr_miss_latency::total 5219755 # number of overall MSHR miss cycles
+system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.023628 # mshr miss rate for ReadReq accesses
+system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.023628 # mshr miss rate for ReadReq accesses
+system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.023628 # mshr miss rate for demand accesses
+system.cpu3.icache.demand_mshr_miss_rate::total 0.023628 # mshr miss rate for demand accesses
+system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.023628 # mshr miss rate for overall accesses
+system.cpu3.icache.overall_mshr_miss_rate::total 0.023628 # mshr miss rate for overall accesses
+system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12138.965116 # average ReadReq mshr miss latency
+system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12138.965116 # average ReadReq mshr miss latency
+system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12138.965116 # average overall mshr miss latency
+system.cpu3.icache.demand_avg_mshr_miss_latency::total 12138.965116 # average overall mshr miss latency
+system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12138.965116 # average overall mshr miss latency
+system.cpu3.icache.overall_avg_mshr_miss_latency::total 12138.965116 # average overall mshr miss latency
+system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu3.dcache.tags.replacements 0 # number of replacements
+system.cpu3.dcache.tags.tagsinuse 23.659946 # Cycle average of tags in use
+system.cpu3.dcache.tags.total_refs 47957 # Total number of references to valid blocks.
+system.cpu3.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks.
+system.cpu3.dcache.tags.avg_refs 1712.750000 # Average number of references to valid blocks.
+system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu3.dcache.tags.occ_blocks::cpu3.data 23.659946 # Average occupied blocks per requestor
+system.cpu3.dcache.tags.occ_percent::cpu3.data 0.046211 # Average percentage of cache occupancy
+system.cpu3.dcache.tags.occ_percent::total 0.046211 # Average percentage of cache occupancy
+system.cpu3.dcache.ReadReq_hits::cpu3.data 50723 # number of ReadReq hits
+system.cpu3.dcache.ReadReq_hits::total 50723 # number of ReadReq hits
+system.cpu3.dcache.WriteReq_hits::cpu3.data 41752 # number of WriteReq hits
+system.cpu3.dcache.WriteReq_hits::total 41752 # number of WriteReq hits
+system.cpu3.dcache.SwapReq_hits::cpu3.data 12 # number of SwapReq hits
+system.cpu3.dcache.SwapReq_hits::total 12 # number of SwapReq hits
+system.cpu3.dcache.demand_hits::cpu3.data 92475 # number of demand (read+write) hits
+system.cpu3.dcache.demand_hits::total 92475 # number of demand (read+write) hits
+system.cpu3.dcache.overall_hits::cpu3.data 92475 # number of overall hits
+system.cpu3.dcache.overall_hits::total 92475 # number of overall hits
+system.cpu3.dcache.ReadReq_misses::cpu3.data 346 # number of ReadReq misses
+system.cpu3.dcache.ReadReq_misses::total 346 # number of ReadReq misses
+system.cpu3.dcache.WriteReq_misses::cpu3.data 138 # number of WriteReq misses
+system.cpu3.dcache.WriteReq_misses::total 138 # number of WriteReq misses
+system.cpu3.dcache.SwapReq_misses::cpu3.data 51 # number of SwapReq misses
+system.cpu3.dcache.SwapReq_misses::total 51 # number of SwapReq misses
+system.cpu3.dcache.demand_misses::cpu3.data 484 # number of demand (read+write) misses
+system.cpu3.dcache.demand_misses::total 484 # number of demand (read+write) misses
+system.cpu3.dcache.overall_misses::cpu3.data 484 # number of overall misses
+system.cpu3.dcache.overall_misses::total 484 # number of overall misses
+system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 4449419 # number of ReadReq miss cycles
+system.cpu3.dcache.ReadReq_miss_latency::total 4449419 # number of ReadReq miss cycles
+system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 2879011 # number of WriteReq miss cycles
+system.cpu3.dcache.WriteReq_miss_latency::total 2879011 # number of WriteReq miss cycles
+system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 478509 # number of SwapReq miss cycles
+system.cpu3.dcache.SwapReq_miss_latency::total 478509 # number of SwapReq miss cycles
+system.cpu3.dcache.demand_miss_latency::cpu3.data 7328430 # number of demand (read+write) miss cycles
+system.cpu3.dcache.demand_miss_latency::total 7328430 # number of demand (read+write) miss cycles
+system.cpu3.dcache.overall_miss_latency::cpu3.data 7328430 # number of overall miss cycles
+system.cpu3.dcache.overall_miss_latency::total 7328430 # number of overall miss cycles
+system.cpu3.dcache.ReadReq_accesses::cpu3.data 51069 # number of ReadReq accesses(hits+misses)
+system.cpu3.dcache.ReadReq_accesses::total 51069 # number of ReadReq accesses(hits+misses)
+system.cpu3.dcache.WriteReq_accesses::cpu3.data 41890 # number of WriteReq accesses(hits+misses)
+system.cpu3.dcache.WriteReq_accesses::total 41890 # number of WriteReq accesses(hits+misses)
+system.cpu3.dcache.SwapReq_accesses::cpu3.data 63 # number of SwapReq accesses(hits+misses)
+system.cpu3.dcache.SwapReq_accesses::total 63 # number of SwapReq accesses(hits+misses)
+system.cpu3.dcache.demand_accesses::cpu3.data 92959 # number of demand (read+write) accesses
+system.cpu3.dcache.demand_accesses::total 92959 # number of demand (read+write) accesses
+system.cpu3.dcache.overall_accesses::cpu3.data 92959 # number of overall (read+write) accesses
+system.cpu3.dcache.overall_accesses::total 92959 # number of overall (read+write) accesses
+system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.006775 # miss rate for ReadReq accesses
+system.cpu3.dcache.ReadReq_miss_rate::total 0.006775 # miss rate for ReadReq accesses
+system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.003294 # miss rate for WriteReq accesses
+system.cpu3.dcache.WriteReq_miss_rate::total 0.003294 # miss rate for WriteReq accesses
+system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.809524 # miss rate for SwapReq accesses
+system.cpu3.dcache.SwapReq_miss_rate::total 0.809524 # miss rate for SwapReq accesses
+system.cpu3.dcache.demand_miss_rate::cpu3.data 0.005207 # miss rate for demand accesses
+system.cpu3.dcache.demand_miss_rate::total 0.005207 # miss rate for demand accesses
+system.cpu3.dcache.overall_miss_rate::cpu3.data 0.005207 # miss rate for overall accesses
+system.cpu3.dcache.overall_miss_rate::total 0.005207 # miss rate for overall accesses
+system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 12859.592486 # average ReadReq miss latency
+system.cpu3.dcache.ReadReq_avg_miss_latency::total 12859.592486 # average ReadReq miss latency
+system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 20862.398551 # average WriteReq miss latency
+system.cpu3.dcache.WriteReq_avg_miss_latency::total 20862.398551 # average WriteReq miss latency
+system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 9382.529412 # average SwapReq miss latency
+system.cpu3.dcache.SwapReq_avg_miss_latency::total 9382.529412 # average SwapReq miss latency
+system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 15141.384298 # average overall miss latency
+system.cpu3.dcache.demand_avg_miss_latency::total 15141.384298 # average overall miss latency
+system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 15141.384298 # average overall miss latency
+system.cpu3.dcache.overall_avg_miss_latency::total 15141.384298 # average overall miss latency
+system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu3.dcache.fast_writes 0 # number of fast writes performed
+system.cpu3.dcache.cache_copies 0 # number of cache copies performed
+system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 195 # number of ReadReq MSHR hits
+system.cpu3.dcache.ReadReq_mshr_hits::total 195 # number of ReadReq MSHR hits
+system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 32 # number of WriteReq MSHR hits
+system.cpu3.dcache.WriteReq_mshr_hits::total 32 # number of WriteReq MSHR hits
+system.cpu3.dcache.demand_mshr_hits::cpu3.data 227 # number of demand (read+write) MSHR hits
+system.cpu3.dcache.demand_mshr_hits::total 227 # number of demand (read+write) MSHR hits
+system.cpu3.dcache.overall_mshr_hits::cpu3.data 227 # number of overall MSHR hits
+system.cpu3.dcache.overall_mshr_hits::total 227 # number of overall MSHR hits
+system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 151 # number of ReadReq MSHR misses
+system.cpu3.dcache.ReadReq_mshr_misses::total 151 # number of ReadReq MSHR misses
+system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 106 # number of WriteReq MSHR misses
+system.cpu3.dcache.WriteReq_mshr_misses::total 106 # number of WriteReq MSHR misses
+system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 51 # number of SwapReq MSHR misses
+system.cpu3.dcache.SwapReq_mshr_misses::total 51 # number of SwapReq MSHR misses
+system.cpu3.dcache.demand_mshr_misses::cpu3.data 257 # number of demand (read+write) MSHR misses
+system.cpu3.dcache.demand_mshr_misses::total 257 # number of demand (read+write) MSHR misses
+system.cpu3.dcache.overall_mshr_misses::cpu3.data 257 # number of overall MSHR misses
+system.cpu3.dcache.overall_mshr_misses::total 257 # number of overall MSHR misses
+system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1003763 # number of ReadReq MSHR miss cycles
+system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1003763 # number of ReadReq MSHR miss cycles
+system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1322239 # number of WriteReq MSHR miss cycles
+system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1322239 # number of WriteReq MSHR miss cycles
+system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 376491 # number of SwapReq MSHR miss cycles
+system.cpu3.dcache.SwapReq_mshr_miss_latency::total 376491 # number of SwapReq MSHR miss cycles
+system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 2326002 # number of demand (read+write) MSHR miss cycles
+system.cpu3.dcache.demand_mshr_miss_latency::total 2326002 # number of demand (read+write) MSHR miss cycles
+system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 2326002 # number of overall MSHR miss cycles
+system.cpu3.dcache.overall_mshr_miss_latency::total 2326002 # number of overall MSHR miss cycles
+system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.002957 # mshr miss rate for ReadReq accesses
+system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.002957 # mshr miss rate for ReadReq accesses
+system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.002530 # mshr miss rate for WriteReq accesses
+system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.002530 # mshr miss rate for WriteReq accesses
+system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.809524 # mshr miss rate for SwapReq accesses
+system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.809524 # mshr miss rate for SwapReq accesses
+system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.002765 # mshr miss rate for demand accesses
+system.cpu3.dcache.demand_mshr_miss_rate::total 0.002765 # mshr miss rate for demand accesses
+system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.002765 # mshr miss rate for overall accesses
+system.cpu3.dcache.overall_mshr_miss_rate::total 0.002765 # mshr miss rate for overall accesses
+system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 6647.437086 # average ReadReq mshr miss latency
+system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 6647.437086 # average ReadReq mshr miss latency
+system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 12473.952830 # average WriteReq mshr miss latency
+system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 12473.952830 # average WriteReq mshr miss latency
+system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 7382.176471 # average SwapReq mshr miss latency
+system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 7382.176471 # average SwapReq mshr miss latency
+system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 9050.591440 # average overall mshr miss latency
+system.cpu3.dcache.demand_avg_mshr_miss_latency::total 9050.591440 # average overall mshr miss latency
+system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 9050.591440 # average overall mshr miss latency
+system.cpu3.dcache.overall_avg_mshr_miss_latency::total 9050.591440 # average overall mshr miss latency
+system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
sim_ticks 262794500 # Number of ticks simulated
final_tick 262794500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 146225 # Simulator instruction rate (inst/s)
-host_op_rate 146224 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 57909206 # Simulator tick rate (ticks/s)
-host_mem_usage 244388 # Number of bytes of host memory used
-host_seconds 4.54 # Real time elapsed on the host
+host_inst_rate 681070 # Simulator instruction rate (inst/s)
+host_op_rate 681053 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 269712940 # Simulator tick rate (ticks/s)
+host_mem_usage 243700 # Number of bytes of host memory used
+host_seconds 0.97 # Real time elapsed on the host
sim_insts 663567 # Number of instructions simulated
sim_ops 663567 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu0.inst 18240 # Number of bytes read from this memory
system.membus.trans_dist::UpgradeResp 77 # Transaction distribution
system.membus.trans_dist::ReadExReq 208 # Transaction distribution
system.membus.trans_dist::ReadExResp 142 # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side 1559 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count 1559 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side 36608 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size 36608 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1559 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 1559 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 36608 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total 36608 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 36608 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.membus.reqLayer0.occupancy 852296 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.3 # Layer utilization (%)
system.membus.respLayer1.occupancy 5420500 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 2.1 # Layer utilization (%)
-system.toL2Bus.throughput 646588875 # Throughput (bytes/s)
-system.toL2Bus.trans_dist::ReadReq 2225 # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp 2225 # Transaction distribution
-system.toL2Bus.trans_dist::Writeback 1 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq 274 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp 274 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 429 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 429 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 934 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 580 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.icache.mem_side 732 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side 355 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu2.icache.mem_side 732 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side 352 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu3.icache.mem_side 734 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side 401 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count 4820 # Packet count per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 29888 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 10944 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side 23424 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side 1664 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu2.icache.mem_side 23424 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu2.dcache.mem_side 1600 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu3.icache.mem_side 23488 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu3.dcache.mem_side 1600 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size 116032 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.data_through_bus 116032 # Total data (bytes)
-system.toL2Bus.snoop_data_through_bus 53888 # Total snoop data (bytes)
-system.toL2Bus.reqLayer0.occupancy 1473490 # Layer occupancy (ticks)
-system.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy 2101500 # Layer occupancy (ticks)
-system.toL2Bus.respLayer0.utilization 0.8 # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy 1430481 # Layer occupancy (ticks)
-system.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy 1650488 # Layer occupancy (ticks)
-system.toL2Bus.respLayer2.utilization 0.6 # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy 1157483 # Layer occupancy (ticks)
-system.toL2Bus.respLayer3.utilization 0.4 # Layer utilization (%)
-system.toL2Bus.respLayer4.occupancy 1651988 # Layer occupancy (ticks)
-system.toL2Bus.respLayer4.utilization 0.6 # Layer utilization (%)
-system.toL2Bus.respLayer5.occupancy 1147981 # Layer occupancy (ticks)
-system.toL2Bus.respLayer5.utilization 0.4 # Layer utilization (%)
-system.toL2Bus.respLayer6.occupancy 1651999 # Layer occupancy (ticks)
-system.toL2Bus.respLayer6.utilization 0.6 # Layer utilization (%)
-system.toL2Bus.respLayer7.occupancy 1327473 # Layer occupancy (ticks)
-system.toL2Bus.respLayer7.utilization 0.5 # Layer utilization (%)
-system.cpu0.workload.num_syscalls 89 # Number of system calls
-system.cpu0.numCycles 525589 # number of cpu cycles simulated
-system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.committedInsts 158574 # Number of instructions committed
-system.cpu0.committedOps 158574 # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses 109208 # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses
-system.cpu0.num_func_calls 390 # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts 26032 # number of instructions that are conditional controls
-system.cpu0.num_int_insts 109208 # number of integer instructions
-system.cpu0.num_fp_insts 0 # number of float instructions
-system.cpu0.num_int_register_reads 315782 # number of times the integer registers were read
-system.cpu0.num_int_register_writes 110814 # number of times the integer registers were written
-system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read
-system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu0.num_mem_refs 74021 # number of memory refs
-system.cpu0.num_load_insts 49007 # Number of load instructions
-system.cpu0.num_store_insts 25014 # Number of store instructions
-system.cpu0.num_idle_cycles 0 # Number of idle cycles
-system.cpu0.num_busy_cycles 525589 # Number of busy cycles
-system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu0.idle_fraction 0 # Percentage of idle cycles
-system.cpu0.icache.tags.replacements 215 # number of replacements
-system.cpu0.icache.tags.tagsinuse 212.401822 # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs 158170 # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs 467 # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs 338.693790 # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst 212.401822 # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst 0.414847 # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total 0.414847 # Average percentage of cache occupancy
-system.cpu0.icache.ReadReq_hits::cpu0.inst 158170 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total 158170 # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst 158170 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total 158170 # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst 158170 # number of overall hits
-system.cpu0.icache.overall_hits::total 158170 # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst 467 # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total 467 # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst 467 # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total 467 # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst 467 # number of overall misses
-system.cpu0.icache.overall_misses::total 467 # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 18148000 # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total 18148000 # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst 18148000 # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total 18148000 # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst 18148000 # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total 18148000 # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst 158637 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total 158637 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst 158637 # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total 158637 # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst 158637 # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total 158637 # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002944 # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total 0.002944 # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002944 # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total 0.002944 # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002944 # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total 0.002944 # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 38860.813704 # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 38860.813704 # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 38860.813704 # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 38860.813704 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 38860.813704 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 38860.813704 # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu0.icache.fast_writes 0 # number of fast writes performed
-system.cpu0.icache.cache_copies 0 # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 467 # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total 467 # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst 467 # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total 467 # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst 467 # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total 467 # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 17214000 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total 17214000 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 17214000 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total 17214000 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 17214000 # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total 17214000 # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.002944 # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.002944 # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.002944 # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total 0.002944 # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.002944 # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total 0.002944 # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 36860.813704 # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 36860.813704 # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 36860.813704 # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 36860.813704 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 36860.813704 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 36860.813704 # average overall mshr miss latency
-system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.dcache.tags.replacements 2 # number of replacements
-system.cpu0.dcache.tags.tagsinuse 145.571924 # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs 73489 # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs 167 # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs 440.053892 # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data 145.571924 # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data 0.284320 # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total 0.284320 # Average percentage of cache occupancy
-system.cpu0.dcache.ReadReq_hits::cpu0.data 48827 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total 48827 # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data 24780 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total 24780 # number of WriteReq hits
-system.cpu0.dcache.SwapReq_hits::cpu0.data 16 # number of SwapReq hits
-system.cpu0.dcache.SwapReq_hits::total 16 # number of SwapReq hits
-system.cpu0.dcache.demand_hits::cpu0.data 73607 # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total 73607 # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data 73607 # number of overall hits
-system.cpu0.dcache.overall_hits::total 73607 # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data 170 # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total 170 # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data 183 # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total 183 # number of WriteReq misses
-system.cpu0.dcache.SwapReq_misses::cpu0.data 26 # number of SwapReq misses
-system.cpu0.dcache.SwapReq_misses::total 26 # number of SwapReq misses
-system.cpu0.dcache.demand_misses::cpu0.data 353 # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total 353 # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data 353 # number of overall misses
-system.cpu0.dcache.overall_misses::total 353 # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4586981 # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total 4586981 # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 6974000 # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total 6974000 # number of WriteReq miss cycles
-system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 360500 # number of SwapReq miss cycles
-system.cpu0.dcache.SwapReq_miss_latency::total 360500 # number of SwapReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data 11560981 # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 11560981 # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data 11560981 # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 11560981 # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data 48997 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total 48997 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data 24963 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total 24963 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses)
-system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data 73960 # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total 73960 # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data 73960 # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total 73960 # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.003470 # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total 0.003470 # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007331 # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total 0.007331 # miss rate for WriteReq accesses
-system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.619048 # miss rate for SwapReq accesses
-system.cpu0.dcache.SwapReq_miss_rate::total 0.619048 # miss rate for SwapReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data 0.004773 # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total 0.004773 # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data 0.004773 # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total 0.004773 # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 26982.241176 # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 26982.241176 # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38109.289617 # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 38109.289617 # average WriteReq miss latency
-system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 13865.384615 # average SwapReq miss latency
-system.cpu0.dcache.SwapReq_avg_miss_latency::total 13865.384615 # average SwapReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 32750.654391 # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 32750.654391 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 32750.654391 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 32750.654391 # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu0.dcache.fast_writes 0 # number of fast writes performed
-system.cpu0.dcache.cache_copies 0 # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks
-system.cpu0.dcache.writebacks::total 1 # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 170 # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total 170 # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 183 # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total 183 # number of WriteReq MSHR misses
-system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 26 # number of SwapReq MSHR misses
-system.cpu0.dcache.SwapReq_mshr_misses::total 26 # number of SwapReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data 353 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total 353 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data 353 # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total 353 # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4237019 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4237019 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6608000 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6608000 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 308500 # number of SwapReq MSHR miss cycles
-system.cpu0.dcache.SwapReq_mshr_miss_latency::total 308500 # number of SwapReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10845019 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total 10845019 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10845019 # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total 10845019 # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.003470 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.003470 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.007331 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007331 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.619048 # mshr miss rate for SwapReq accesses
-system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.619048 # mshr miss rate for SwapReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.004773 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total 0.004773 # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.004773 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total 0.004773 # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 24923.641176 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 24923.641176 # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36109.289617 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36109.289617 # average WriteReq mshr miss latency
-system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 11865.384615 # average SwapReq mshr miss latency
-system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 11865.384615 # average SwapReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 30722.433428 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 30722.433428 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 30722.433428 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 30722.433428 # average overall mshr miss latency
-system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.numCycles 525588 # number of cpu cycles simulated
-system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.committedInsts 163471 # Number of instructions committed
-system.cpu1.committedOps 163471 # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses 111731 # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses
-system.cpu1.num_func_calls 637 # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts 29880 # number of instructions that are conditional controls
-system.cpu1.num_int_insts 111731 # number of integer instructions
-system.cpu1.num_fp_insts 0 # number of float instructions
-system.cpu1.num_int_register_reads 289610 # number of times the integer registers were read
-system.cpu1.num_int_register_writes 111151 # number of times the integer registers were written
-system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read
-system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu1.num_mem_refs 58020 # number of memory refs
-system.cpu1.num_load_insts 41540 # Number of load instructions
-system.cpu1.num_store_insts 16480 # Number of store instructions
-system.cpu1.num_idle_cycles 69347.869793 # Number of idle cycles
-system.cpu1.num_busy_cycles 456240.130207 # Number of busy cycles
-system.cpu1.not_idle_fraction 0.868057 # Percentage of non-idle cycles
-system.cpu1.idle_fraction 0.131943 # Percentage of idle cycles
-system.cpu1.icache.tags.replacements 280 # number of replacements
-system.cpu1.icache.tags.tagsinuse 70.017506 # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs 163138 # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs 366 # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs 445.732240 # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst 70.017506 # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst 0.136753 # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total 0.136753 # Average percentage of cache occupancy
-system.cpu1.icache.ReadReq_hits::cpu1.inst 163138 # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total 163138 # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst 163138 # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total 163138 # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst 163138 # number of overall hits
-system.cpu1.icache.overall_hits::total 163138 # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst 366 # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total 366 # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst 366 # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total 366 # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst 366 # number of overall misses
-system.cpu1.icache.overall_misses::total 366 # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7546988 # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total 7546988 # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst 7546988 # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total 7546988 # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst 7546988 # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total 7546988 # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst 163504 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total 163504 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst 163504 # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total 163504 # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst 163504 # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total 163504 # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002238 # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total 0.002238 # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002238 # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total 0.002238 # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002238 # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total 0.002238 # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 20620.185792 # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 20620.185792 # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 20620.185792 # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 20620.185792 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 20620.185792 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 20620.185792 # average overall miss latency
-system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu1.icache.fast_writes 0 # number of fast writes performed
-system.cpu1.icache.cache_copies 0 # number of cache copies performed
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 366 # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total 366 # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst 366 # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst 366 # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total 366 # number of overall MSHR misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6808012 # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total 6808012 # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6808012 # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total 6808012 # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6808012 # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total 6808012 # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.002238 # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.002238 # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.002238 # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total 0.002238 # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.002238 # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total 0.002238 # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 18601.125683 # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 18601.125683 # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 18601.125683 # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total 18601.125683 # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 18601.125683 # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total 18601.125683 # average overall mshr miss latency
-system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.dcache.tags.replacements 0 # number of replacements
-system.cpu1.dcache.tags.tagsinuse 27.720196 # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs 35348 # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs 30 # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs 1178.266667 # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data 27.720196 # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data 0.054141 # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total 0.054141 # Average percentage of cache occupancy
-system.cpu1.dcache.ReadReq_hits::cpu1.data 41378 # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total 41378 # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data 16307 # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total 16307 # number of WriteReq hits
-system.cpu1.dcache.SwapReq_hits::cpu1.data 11 # number of SwapReq hits
-system.cpu1.dcache.SwapReq_hits::total 11 # number of SwapReq hits
-system.cpu1.dcache.demand_hits::cpu1.data 57685 # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total 57685 # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data 57685 # number of overall hits
-system.cpu1.dcache.overall_hits::total 57685 # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data 154 # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total 154 # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data 109 # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total 109 # number of WriteReq misses
-system.cpu1.dcache.SwapReq_misses::cpu1.data 51 # number of SwapReq misses
-system.cpu1.dcache.SwapReq_misses::total 51 # number of SwapReq misses
-system.cpu1.dcache.demand_misses::cpu1.data 263 # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total 263 # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data 263 # number of overall misses
-system.cpu1.dcache.overall_misses::total 263 # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2495483 # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total 2495483 # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1980000 # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total 1980000 # number of WriteReq miss cycles
-system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 209500 # number of SwapReq miss cycles
-system.cpu1.dcache.SwapReq_miss_latency::total 209500 # number of SwapReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data 4475483 # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total 4475483 # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data 4475483 # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total 4475483 # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data 41532 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total 41532 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data 16416 # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total 16416 # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.SwapReq_accesses::cpu1.data 62 # number of SwapReq accesses(hits+misses)
-system.cpu1.dcache.SwapReq_accesses::total 62 # number of SwapReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data 57948 # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total 57948 # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data 57948 # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total 57948 # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.003708 # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total 0.003708 # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.006640 # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total 0.006640 # miss rate for WriteReq accesses
-system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.822581 # miss rate for SwapReq accesses
-system.cpu1.dcache.SwapReq_miss_rate::total 0.822581 # miss rate for SwapReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data 0.004539 # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total 0.004539 # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data 0.004539 # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total 0.004539 # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16204.435065 # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 16204.435065 # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18165.137615 # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 18165.137615 # average WriteReq miss latency
-system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 4107.843137 # average SwapReq miss latency
-system.cpu1.dcache.SwapReq_avg_miss_latency::total 4107.843137 # average SwapReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17017.045627 # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 17017.045627 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17017.045627 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 17017.045627 # average overall miss latency
-system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu1.dcache.fast_writes 0 # number of fast writes performed
-system.cpu1.dcache.cache_copies 0 # number of cache copies performed
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 154 # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total 154 # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 109 # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total 109 # number of WriteReq MSHR misses
-system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 51 # number of SwapReq MSHR misses
-system.cpu1.dcache.SwapReq_mshr_misses::total 51 # number of SwapReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data 263 # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total 263 # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data 263 # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total 263 # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2170517 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2170517 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1762000 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1762000 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 107500 # number of SwapReq MSHR miss cycles
-system.cpu1.dcache.SwapReq_mshr_miss_latency::total 107500 # number of SwapReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3932517 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total 3932517 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3932517 # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total 3932517 # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003708 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003708 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.006640 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.006640 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.822581 # mshr miss rate for SwapReq accesses
-system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.822581 # mshr miss rate for SwapReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.004539 # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total 0.004539 # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.004539 # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total 0.004539 # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14094.266234 # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14094.266234 # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16165.137615 # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16165.137615 # average WriteReq mshr miss latency
-system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 2107.843137 # average SwapReq mshr miss latency
-system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 2107.843137 # average SwapReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14952.536122 # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14952.536122 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14952.536122 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14952.536122 # average overall mshr miss latency
-system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu2.numCycles 525588 # number of cpu cycles simulated
-system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu2.committedInsts 164866 # Number of instructions committed
-system.cpu2.committedOps 164866 # Number of ops (including micro ops) committed
-system.cpu2.num_int_alu_accesses 112988 # Number of integer alu accesses
-system.cpu2.num_fp_alu_accesses 0 # Number of float alu accesses
-system.cpu2.num_func_calls 637 # number of times a function call or return occured
-system.cpu2.num_conditional_control_insts 29949 # number of instructions that are conditional controls
-system.cpu2.num_int_insts 112988 # number of integer instructions
-system.cpu2.num_fp_insts 0 # number of float instructions
-system.cpu2.num_int_register_reads 294363 # number of times the integer registers were read
-system.cpu2.num_int_register_writes 112900 # number of times the integer registers were written
-system.cpu2.num_fp_register_reads 0 # number of times the floating registers were read
-system.cpu2.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu2.num_mem_refs 59208 # number of memory refs
-system.cpu2.num_load_insts 42171 # Number of load instructions
-system.cpu2.num_store_insts 17037 # Number of store instructions
-system.cpu2.num_idle_cycles 69604.869303 # Number of idle cycles
-system.cpu2.num_busy_cycles 455983.130697 # Number of busy cycles
-system.cpu2.not_idle_fraction 0.867568 # Percentage of non-idle cycles
-system.cpu2.idle_fraction 0.132432 # Percentage of idle cycles
-system.cpu2.icache.tags.replacements 280 # number of replacements
-system.cpu2.icache.tags.tagsinuse 67.624969 # Cycle average of tags in use
-system.cpu2.icache.tags.total_refs 164533 # Total number of references to valid blocks.
-system.cpu2.icache.tags.sampled_refs 366 # Sample count of references to valid blocks.
-system.cpu2.icache.tags.avg_refs 449.543716 # Average number of references to valid blocks.
-system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu2.icache.tags.occ_blocks::cpu2.inst 67.624969 # Average occupied blocks per requestor
-system.cpu2.icache.tags.occ_percent::cpu2.inst 0.132080 # Average percentage of cache occupancy
-system.cpu2.icache.tags.occ_percent::total 0.132080 # Average percentage of cache occupancy
-system.cpu2.icache.ReadReq_hits::cpu2.inst 164533 # number of ReadReq hits
-system.cpu2.icache.ReadReq_hits::total 164533 # number of ReadReq hits
-system.cpu2.icache.demand_hits::cpu2.inst 164533 # number of demand (read+write) hits
-system.cpu2.icache.demand_hits::total 164533 # number of demand (read+write) hits
-system.cpu2.icache.overall_hits::cpu2.inst 164533 # number of overall hits
-system.cpu2.icache.overall_hits::total 164533 # number of overall hits
-system.cpu2.icache.ReadReq_misses::cpu2.inst 366 # number of ReadReq misses
-system.cpu2.icache.ReadReq_misses::total 366 # number of ReadReq misses
-system.cpu2.icache.demand_misses::cpu2.inst 366 # number of demand (read+write) misses
-system.cpu2.icache.demand_misses::total 366 # number of demand (read+write) misses
-system.cpu2.icache.overall_misses::cpu2.inst 366 # number of overall misses
-system.cpu2.icache.overall_misses::total 366 # number of overall misses
-system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 5255488 # number of ReadReq miss cycles
-system.cpu2.icache.ReadReq_miss_latency::total 5255488 # number of ReadReq miss cycles
-system.cpu2.icache.demand_miss_latency::cpu2.inst 5255488 # number of demand (read+write) miss cycles
-system.cpu2.icache.demand_miss_latency::total 5255488 # number of demand (read+write) miss cycles
-system.cpu2.icache.overall_miss_latency::cpu2.inst 5255488 # number of overall miss cycles
-system.cpu2.icache.overall_miss_latency::total 5255488 # number of overall miss cycles
-system.cpu2.icache.ReadReq_accesses::cpu2.inst 164899 # number of ReadReq accesses(hits+misses)
-system.cpu2.icache.ReadReq_accesses::total 164899 # number of ReadReq accesses(hits+misses)
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-system.cpu2.icache.demand_miss_rate::total 0.002220 # miss rate for demand accesses
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-system.cpu2.icache.ReadReq_avg_miss_latency::total 14359.256831 # average ReadReq miss latency
-system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 14359.256831 # average overall miss latency
-system.cpu2.icache.demand_avg_miss_latency::total 14359.256831 # average overall miss latency
-system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 14359.256831 # average overall miss latency
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-system.cpu2.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses
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-system.cpu2.icache.overall_mshr_misses::total 366 # number of overall MSHR misses
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-system.cpu2.icache.ReadReq_mshr_miss_latency::total 4513512 # number of ReadReq MSHR miss cycles
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-system.cpu2.icache.demand_mshr_miss_latency::total 4513512 # number of demand (read+write) MSHR miss cycles
-system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 4513512 # number of overall MSHR miss cycles
-system.cpu2.icache.overall_mshr_miss_latency::total 4513512 # number of overall MSHR miss cycles
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-system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.002220 # mshr miss rate for ReadReq accesses
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-system.cpu2.icache.demand_mshr_miss_rate::total 0.002220 # mshr miss rate for demand accesses
-system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.002220 # mshr miss rate for overall accesses
-system.cpu2.icache.overall_mshr_miss_rate::total 0.002220 # mshr miss rate for overall accesses
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-system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 12332 # average ReadReq mshr miss latency
-system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 12332 # average overall mshr miss latency
-system.cpu2.icache.demand_avg_mshr_miss_latency::total 12332 # average overall mshr miss latency
-system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 12332 # average overall mshr miss latency
-system.cpu2.icache.overall_avg_mshr_miss_latency::total 12332 # average overall mshr miss latency
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-system.cpu2.dcache.ReadReq_miss_latency::total 2129481 # number of ReadReq miss cycles
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-system.cpu2.dcache.overall_miss_latency::total 4059981 # number of overall miss cycles
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-system.cpu2.dcache.WriteReq_avg_miss_latency::total 17550 # average WriteReq miss latency
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-system.cpu2.dcache.SwapReq_avg_miss_latency::total 4090 # average SwapReq miss latency
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-system.cpu2.dcache.demand_avg_miss_latency::total 15496.110687 # average overall miss latency
-system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 15496.110687 # average overall miss latency
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-system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1809519 # number of ReadReq MSHR miss cycles
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-system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 13435.187023 # average overall mshr miss latency
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-system.cpu3.num_conditional_control_insts 38223 # number of instructions that are conditional controls
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-system.cpu3.num_load_insts 39753 # Number of load instructions
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-system.cpu3.icache.ReadReq_miss_latency::total 5147499 # number of ReadReq miss cycles
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-system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.002077 # mshr miss rate for demand accesses
-system.cpu3.icache.demand_mshr_miss_rate::total 0.002077 # mshr miss rate for demand accesses
-system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.002077 # mshr miss rate for overall accesses
-system.cpu3.icache.overall_mshr_miss_rate::total 0.002077 # mshr miss rate for overall accesses
-system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12023.163488 # average ReadReq mshr miss latency
-system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12023.163488 # average ReadReq mshr miss latency
-system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12023.163488 # average overall mshr miss latency
-system.cpu3.icache.demand_avg_mshr_miss_latency::total 12023.163488 # average overall mshr miss latency
-system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12023.163488 # average overall mshr miss latency
-system.cpu3.icache.overall_avg_mshr_miss_latency::total 12023.163488 # average overall mshr miss latency
-system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu3.dcache.tags.replacements 0 # number of replacements
-system.cpu3.dcache.tags.tagsinuse 25.915086 # Cycle average of tags in use
-system.cpu3.dcache.tags.total_refs 15020 # Total number of references to valid blocks.
-system.cpu3.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks.
-system.cpu3.dcache.tags.avg_refs 517.931034 # Average number of references to valid blocks.
-system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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-system.cpu3.dcache.tags.occ_percent::total 0.050615 # Average percentage of cache occupancy
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-system.cpu3.dcache.ReadReq_hits::total 39563 # number of ReadReq hits
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-system.cpu3.dcache.WriteReq_hits::total 6216 # number of WriteReq hits
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-system.cpu3.dcache.SwapReq_hits::total 19 # number of SwapReq hits
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-system.cpu3.dcache.overall_hits::total 45779 # number of overall hits
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-system.cpu3.dcache.ReadReq_misses::total 183 # number of ReadReq misses
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-system.cpu3.dcache.demand_misses::total 288 # number of demand (read+write) misses
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-system.cpu3.dcache.overall_misses::total 288 # number of overall misses
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-system.cpu3.dcache.ReadReq_miss_latency::total 3156473 # number of ReadReq miss cycles
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-system.cpu3.dcache.demand_miss_latency::total 5254973 # number of demand (read+write) miss cycles
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-system.cpu3.dcache.overall_miss_latency::total 5254973 # number of overall miss cycles
-system.cpu3.dcache.ReadReq_accesses::cpu3.data 39746 # number of ReadReq accesses(hits+misses)
-system.cpu3.dcache.ReadReq_accesses::total 39746 # number of ReadReq accesses(hits+misses)
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-system.cpu3.dcache.WriteReq_accesses::total 6321 # number of WriteReq accesses(hits+misses)
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-system.cpu3.dcache.SwapReq_accesses::total 88 # number of SwapReq accesses(hits+misses)
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-system.cpu3.dcache.demand_accesses::total 46067 # number of demand (read+write) accesses
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-system.cpu3.dcache.SwapReq_miss_rate::total 0.784091 # miss rate for SwapReq accesses
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-system.cpu3.dcache.ReadReq_avg_miss_latency::total 17248.486339 # average ReadReq miss latency
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-system.cpu3.dcache.WriteReq_avg_miss_latency::total 19985.714286 # average WriteReq miss latency
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-system.cpu3.dcache.SwapReq_avg_miss_latency::total 4057.971014 # average SwapReq miss latency
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-system.cpu3.dcache.demand_avg_miss_latency::total 18246.434028 # average overall miss latency
-system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 18246.434028 # average overall miss latency
-system.cpu3.dcache.overall_avg_miss_latency::total 18246.434028 # average overall miss latency
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-system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
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-system.cpu3.dcache.fast_writes 0 # number of fast writes performed
-system.cpu3.dcache.cache_copies 0 # number of cache copies performed
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-system.cpu3.dcache.ReadReq_mshr_misses::total 183 # number of ReadReq MSHR misses
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-system.cpu3.dcache.overall_mshr_misses::total 288 # number of overall MSHR misses
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-system.cpu3.dcache.ReadReq_mshr_miss_latency::total 2772527 # number of ReadReq MSHR miss cycles
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-system.cpu3.dcache.overall_mshr_miss_latency::total 4661027 # number of overall MSHR miss cycles
-system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.004604 # mshr miss rate for ReadReq accesses
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-system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.784091 # mshr miss rate for SwapReq accesses
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-system.cpu3.dcache.demand_mshr_miss_rate::total 0.006252 # mshr miss rate for demand accesses
-system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.006252 # mshr miss rate for overall accesses
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-system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 15150.420765 # average ReadReq mshr miss latency
-system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 17985.714286 # average WriteReq mshr miss latency
-system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 17985.714286 # average WriteReq mshr miss latency
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-system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 2057.971014 # average SwapReq mshr miss latency
-system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 16184.121528 # average overall mshr miss latency
-system.cpu3.dcache.demand_avg_mshr_miss_latency::total 16184.121528 # average overall mshr miss latency
-system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 16184.121528 # average overall mshr miss latency
-system.cpu3.dcache.overall_avg_mshr_miss_latency::total 16184.121528 # average overall mshr miss latency
-system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.l2c.tags.replacements 0 # number of replacements
-system.l2c.tags.tagsinuse 349.046072 # Cycle average of tags in use
-system.l2c.tags.total_refs 1220 # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs 429 # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs 2.843823 # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks 0.889005 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst 231.790437 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data 54.207948 # Average occupied blocks per requestor
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-system.l2c.tags.occ_blocks::cpu1.data 6.123914 # Average occupied blocks per requestor
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-system.l2c.tags.occ_blocks::cpu2.data 0.843760 # Average occupied blocks per requestor
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-system.l2c.tags.occ_blocks::cpu3.data 0.831024 # Average occupied blocks per requestor
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system.l2c.ReadReq_hits::cpu0.inst 182 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst 300 # number of ReadReq hits
system.l2c.overall_avg_mshr_miss_latency::cpu3.data 40000 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 40108.391608 # average overall mshr miss latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
+system.toL2Bus.throughput 646588875 # Throughput (bytes/s)
+system.toL2Bus.trans_dist::ReadReq 2225 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 2225 # Transaction distribution
+system.toL2Bus.trans_dist::Writeback 1 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 274 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 274 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 429 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 429 # Transaction distribution
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+system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 355 # Packet count per connected master and slave (bytes)
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+system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 352 # Packet count per connected master and slave (bytes)
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+system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 401 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 4820 # Packet count per connected master and slave (bytes)
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+system.toL2Bus.tot_pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes)
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+system.toL2Bus.tot_pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size::total 116032 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.data_through_bus 116032 # Total data (bytes)
+system.toL2Bus.snoop_data_through_bus 53888 # Total snoop data (bytes)
+system.toL2Bus.reqLayer0.occupancy 1473490 # Layer occupancy (ticks)
+system.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%)
+system.toL2Bus.respLayer0.occupancy 2101500 # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.utilization 0.8 # Layer utilization (%)
+system.toL2Bus.respLayer1.occupancy 1430481 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%)
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+system.toL2Bus.respLayer2.utilization 0.6 # Layer utilization (%)
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+system.toL2Bus.respLayer3.utilization 0.4 # Layer utilization (%)
+system.toL2Bus.respLayer4.occupancy 1651988 # Layer occupancy (ticks)
+system.toL2Bus.respLayer4.utilization 0.6 # Layer utilization (%)
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+system.toL2Bus.respLayer5.utilization 0.4 # Layer utilization (%)
+system.toL2Bus.respLayer6.occupancy 1651999 # Layer occupancy (ticks)
+system.toL2Bus.respLayer6.utilization 0.6 # Layer utilization (%)
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+system.toL2Bus.respLayer7.utilization 0.5 # Layer utilization (%)
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+system.cpu0.num_func_calls 390 # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts 26032 # number of instructions that are conditional controls
+system.cpu0.num_int_insts 109208 # number of integer instructions
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+system.cpu0.num_int_register_reads 315782 # number of times the integer registers were read
+system.cpu0.num_int_register_writes 110814 # number of times the integer registers were written
+system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read
+system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written
+system.cpu0.num_mem_refs 74021 # number of memory refs
+system.cpu0.num_load_insts 49007 # Number of load instructions
+system.cpu0.num_store_insts 25014 # Number of store instructions
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+system.cpu0.num_busy_cycles 525589 # Number of busy cycles
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+system.cpu0.idle_fraction 0 # Percentage of idle cycles
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+system.cpu0.icache.tags.tagsinuse 212.401822 # Cycle average of tags in use
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+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 18601.125683 # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total 18601.125683 # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 18601.125683 # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total 18601.125683 # average overall mshr miss latency
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+system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 14359.256831 # average overall miss latency
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+system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 12332 # average overall mshr miss latency
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+system.cpu3.dcache.WriteReq_accesses::total 6321 # number of WriteReq accesses(hits+misses)
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+system.cpu3.dcache.SwapReq_accesses::total 88 # number of SwapReq accesses(hits+misses)
+system.cpu3.dcache.demand_accesses::cpu3.data 46067 # number of demand (read+write) accesses
+system.cpu3.dcache.demand_accesses::total 46067 # number of demand (read+write) accesses
+system.cpu3.dcache.overall_accesses::cpu3.data 46067 # number of overall (read+write) accesses
+system.cpu3.dcache.overall_accesses::total 46067 # number of overall (read+write) accesses
+system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.004604 # miss rate for ReadReq accesses
+system.cpu3.dcache.ReadReq_miss_rate::total 0.004604 # miss rate for ReadReq accesses
+system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.016611 # miss rate for WriteReq accesses
+system.cpu3.dcache.WriteReq_miss_rate::total 0.016611 # miss rate for WriteReq accesses
+system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.784091 # miss rate for SwapReq accesses
+system.cpu3.dcache.SwapReq_miss_rate::total 0.784091 # miss rate for SwapReq accesses
+system.cpu3.dcache.demand_miss_rate::cpu3.data 0.006252 # miss rate for demand accesses
+system.cpu3.dcache.demand_miss_rate::total 0.006252 # miss rate for demand accesses
+system.cpu3.dcache.overall_miss_rate::cpu3.data 0.006252 # miss rate for overall accesses
+system.cpu3.dcache.overall_miss_rate::total 0.006252 # miss rate for overall accesses
+system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 17248.486339 # average ReadReq miss latency
+system.cpu3.dcache.ReadReq_avg_miss_latency::total 17248.486339 # average ReadReq miss latency
+system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 19985.714286 # average WriteReq miss latency
+system.cpu3.dcache.WriteReq_avg_miss_latency::total 19985.714286 # average WriteReq miss latency
+system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 4057.971014 # average SwapReq miss latency
+system.cpu3.dcache.SwapReq_avg_miss_latency::total 4057.971014 # average SwapReq miss latency
+system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 18246.434028 # average overall miss latency
+system.cpu3.dcache.demand_avg_miss_latency::total 18246.434028 # average overall miss latency
+system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 18246.434028 # average overall miss latency
+system.cpu3.dcache.overall_avg_miss_latency::total 18246.434028 # average overall miss latency
+system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu3.dcache.fast_writes 0 # number of fast writes performed
+system.cpu3.dcache.cache_copies 0 # number of cache copies performed
+system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 183 # number of ReadReq MSHR misses
+system.cpu3.dcache.ReadReq_mshr_misses::total 183 # number of ReadReq MSHR misses
+system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 105 # number of WriteReq MSHR misses
+system.cpu3.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses
+system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 69 # number of SwapReq MSHR misses
+system.cpu3.dcache.SwapReq_mshr_misses::total 69 # number of SwapReq MSHR misses
+system.cpu3.dcache.demand_mshr_misses::cpu3.data 288 # number of demand (read+write) MSHR misses
+system.cpu3.dcache.demand_mshr_misses::total 288 # number of demand (read+write) MSHR misses
+system.cpu3.dcache.overall_mshr_misses::cpu3.data 288 # number of overall MSHR misses
+system.cpu3.dcache.overall_mshr_misses::total 288 # number of overall MSHR misses
+system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 2772527 # number of ReadReq MSHR miss cycles
+system.cpu3.dcache.ReadReq_mshr_miss_latency::total 2772527 # number of ReadReq MSHR miss cycles
+system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1888500 # number of WriteReq MSHR miss cycles
+system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1888500 # number of WriteReq MSHR miss cycles
+system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 142000 # number of SwapReq MSHR miss cycles
+system.cpu3.dcache.SwapReq_mshr_miss_latency::total 142000 # number of SwapReq MSHR miss cycles
+system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 4661027 # number of demand (read+write) MSHR miss cycles
+system.cpu3.dcache.demand_mshr_miss_latency::total 4661027 # number of demand (read+write) MSHR miss cycles
+system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 4661027 # number of overall MSHR miss cycles
+system.cpu3.dcache.overall_mshr_miss_latency::total 4661027 # number of overall MSHR miss cycles
+system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.004604 # mshr miss rate for ReadReq accesses
+system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.004604 # mshr miss rate for ReadReq accesses
+system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.016611 # mshr miss rate for WriteReq accesses
+system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.016611 # mshr miss rate for WriteReq accesses
+system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.784091 # mshr miss rate for SwapReq accesses
+system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.784091 # mshr miss rate for SwapReq accesses
+system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.006252 # mshr miss rate for demand accesses
+system.cpu3.dcache.demand_mshr_miss_rate::total 0.006252 # mshr miss rate for demand accesses
+system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.006252 # mshr miss rate for overall accesses
+system.cpu3.dcache.overall_mshr_miss_rate::total 0.006252 # mshr miss rate for overall accesses
+system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 15150.420765 # average ReadReq mshr miss latency
+system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 15150.420765 # average ReadReq mshr miss latency
+system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 17985.714286 # average WriteReq mshr miss latency
+system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 17985.714286 # average WriteReq mshr miss latency
+system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 2057.971014 # average SwapReq mshr miss latency
+system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 2057.971014 # average SwapReq mshr miss latency
+system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 16184.121528 # average overall mshr miss latency
+system.cpu3.dcache.demand_avg_mshr_miss_latency::total 16184.121528 # average overall mshr miss latency
+system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 16184.121528 # average overall mshr miss latency
+system.cpu3.dcache.overall_avg_mshr_miss_latency::total 16184.121528 # average overall mshr miss latency
+system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
sim_ticks 652606500 # Number of ticks simulated
final_tick 652606500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_tick_rate 176079756 # Simulator tick rate (ticks/s)
-host_mem_usage 355636 # Number of bytes of host memory used
-host_seconds 3.71 # Real time elapsed on the host
+host_tick_rate 158104978 # Simulator tick rate (ticks/s)
+host_mem_usage 355504 # Number of bytes of host memory used
+host_seconds 4.13 # Real time elapsed on the host
system.physmem.bytes_read::cpu0 80014 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1 82049 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2 81047 # Number of bytes read from this memory
system.membus.trans_dist::UpgradeResp 46744 # Transaction distribution
system.membus.trans_dist::ReadExReq 48586 # Transaction distribution
system.membus.trans_dist::ReadExResp 3092 # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side 417062 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count 417062 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side 1086481 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size 1086481 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 417062 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 417062 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 1086481 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total 1086481 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 1086481 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.membus.reqLayer0.occupancy 286485584 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 43.9 # Layer utilization (%)
system.membus.respLayer0.occupancy 311361500 # Layer occupancy (ticks)
system.membus.respLayer0.utilization 47.7 # Layer utilization (%)
-system.l2c.tags.replacements 13254 # number of replacements
-system.l2c.tags.tagsinuse 783.820018 # Cycle average of tags in use
-system.l2c.tags.total_refs 149317 # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs 14065 # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs 10.616210 # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks 726.472153 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0 7.679894 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1 7.566050 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2 7.311161 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3 6.856177 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu4 7.195523 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu5 6.988954 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu6 6.739476 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu7 7.010629 # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks 0.709445 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0 0.007500 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1 0.007389 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2 0.007140 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu3 0.006695 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu4 0.007027 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu5 0.006825 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu6 0.006582 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu7 0.006846 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total 0.765449 # Average percentage of cache occupancy
+system.l2c.tags.replacements 13254 # number of replacements
+system.l2c.tags.tagsinuse 783.820018 # Cycle average of tags in use
+system.l2c.tags.total_refs 149317 # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs 14065 # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs 10.616210 # Average number of references to valid blocks.
+system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.l2c.tags.occ_blocks::writebacks 726.472153 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0 7.679894 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1 7.566050 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2 7.311161 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu3 6.856177 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu4 7.195523 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu5 6.988954 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu6 6.739476 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu7 7.010629 # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks 0.709445 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0 0.007500 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1 0.007389 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu2 0.007140 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu3 0.006695 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu4 0.007027 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu5 0.006825 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu6 0.006582 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu7 0.006846 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total 0.765449 # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu0 10635 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1 10552 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2 10744 # number of ReadReq hits
system.toL2Bus.trans_dist::UpgradeResp 28718 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 155928 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 155926 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side 118285 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side 118639 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side 118896 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side 119078 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side 118813 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side 118602 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side 118904 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side 119137 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count 950354 # Packet count per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.l1c.mem_side 1731443 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu1.l1c.mem_side 1726092 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu2.l1c.mem_side 1741657 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu3.l1c.mem_side 1748194 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu4.l1c.mem_side 1742487 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu5.l1c.mem_side 1735937 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu6.l1c.mem_side 1741406 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu7.l1c.mem_side 1745057 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size 13912273 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 118285 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 118639 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 118896 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 119078 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 118813 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 118602 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 118904 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 119137 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 950354 # Packet count per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1731443 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1726092 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1741657 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1748194 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1742487 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1735937 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1741406 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1745057 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size::total 13912273 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.data_through_bus 13912273 # Total data (bytes)
system.toL2Bus.snoop_data_through_bus 19421888 # Total snoop data (bytes)
system.toL2Bus.reqLayer0.occupancy 652560490 # Layer occupancy (ticks)
system.cpu0.num_reads 98977 # number of read accesses completed
system.cpu0.num_writes 53590 # number of write accesses completed
system.cpu0.num_copies 0 # number of copy accesses completed
-system.cpu0.l1c.tags.replacements 21970 # number of replacements
-system.cpu0.l1c.tags.tagsinuse 393.709596 # Cycle average of tags in use
-system.cpu0.l1c.tags.total_refs 13350 # Total number of references to valid blocks.
-system.cpu0.l1c.tags.sampled_refs 22370 # Sample count of references to valid blocks.
-system.cpu0.l1c.tags.avg_refs 0.596781 # Average number of references to valid blocks.
-system.cpu0.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu0.l1c.tags.occ_blocks::cpu0 393.709596 # Average occupied blocks per requestor
-system.cpu0.l1c.tags.occ_percent::cpu0 0.768964 # Average percentage of cache occupancy
-system.cpu0.l1c.tags.occ_percent::total 0.768964 # Average percentage of cache occupancy
+system.cpu0.l1c.tags.replacements 21970 # number of replacements
+system.cpu0.l1c.tags.tagsinuse 393.709596 # Cycle average of tags in use
+system.cpu0.l1c.tags.total_refs 13350 # Total number of references to valid blocks.
+system.cpu0.l1c.tags.sampled_refs 22370 # Sample count of references to valid blocks.
+system.cpu0.l1c.tags.avg_refs 0.596781 # Average number of references to valid blocks.
+system.cpu0.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu0.l1c.tags.occ_blocks::cpu0 393.709596 # Average occupied blocks per requestor
+system.cpu0.l1c.tags.occ_percent::cpu0 0.768964 # Average percentage of cache occupancy
+system.cpu0.l1c.tags.occ_percent::total 0.768964 # Average percentage of cache occupancy
system.cpu0.l1c.ReadReq_hits::cpu0 8685 # number of ReadReq hits
system.cpu0.l1c.ReadReq_hits::total 8685 # number of ReadReq hits
system.cpu0.l1c.WriteReq_hits::cpu0 1118 # number of WriteReq hits
system.cpu1.num_reads 99824 # number of read accesses completed
system.cpu1.num_writes 53636 # number of write accesses completed
system.cpu1.num_copies 0 # number of copy accesses completed
-system.cpu1.l1c.tags.replacements 22223 # number of replacements
-system.cpu1.l1c.tags.tagsinuse 395.298418 # Cycle average of tags in use
-system.cpu1.l1c.tags.total_refs 13436 # Total number of references to valid blocks.
-system.cpu1.l1c.tags.sampled_refs 22630 # Sample count of references to valid blocks.
-system.cpu1.l1c.tags.avg_refs 0.593725 # Average number of references to valid blocks.
-system.cpu1.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu1.l1c.tags.occ_blocks::cpu1 395.298418 # Average occupied blocks per requestor
-system.cpu1.l1c.tags.occ_percent::cpu1 0.772067 # Average percentage of cache occupancy
-system.cpu1.l1c.tags.occ_percent::total 0.772067 # Average percentage of cache occupancy
+system.cpu1.l1c.tags.replacements 22223 # number of replacements
+system.cpu1.l1c.tags.tagsinuse 395.298418 # Cycle average of tags in use
+system.cpu1.l1c.tags.total_refs 13436 # Total number of references to valid blocks.
+system.cpu1.l1c.tags.sampled_refs 22630 # Sample count of references to valid blocks.
+system.cpu1.l1c.tags.avg_refs 0.593725 # Average number of references to valid blocks.
+system.cpu1.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu1.l1c.tags.occ_blocks::cpu1 395.298418 # Average occupied blocks per requestor
+system.cpu1.l1c.tags.occ_percent::cpu1 0.772067 # Average percentage of cache occupancy
+system.cpu1.l1c.tags.occ_percent::total 0.772067 # Average percentage of cache occupancy
system.cpu1.l1c.ReadReq_hits::cpu1 8757 # number of ReadReq hits
system.cpu1.l1c.ReadReq_hits::total 8757 # number of ReadReq hits
system.cpu1.l1c.WriteReq_hits::cpu1 1135 # number of WriteReq hits
system.cpu2.num_reads 99336 # number of read accesses completed
system.cpu2.num_writes 53403 # number of write accesses completed
system.cpu2.num_copies 0 # number of copy accesses completed
-system.cpu2.l1c.tags.replacements 22214 # number of replacements
-system.cpu2.l1c.tags.tagsinuse 394.859577 # Cycle average of tags in use
-system.cpu2.l1c.tags.total_refs 13307 # Total number of references to valid blocks.
-system.cpu2.l1c.tags.sampled_refs 22614 # Sample count of references to valid blocks.
-system.cpu2.l1c.tags.avg_refs 0.588441 # Average number of references to valid blocks.
-system.cpu2.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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sim_ticks 100000000000 # Number of ticks simulated
final_tick 100000000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
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system.physmem.bytes_read::cpu 213331136 # Number of bytes read from this memory
system.physmem.bytes_read::total 213331136 # Number of bytes read from this memory
system.physmem.num_reads::cpu 3333299 # Number of read requests responded to by this memory
system.physmem.bw_read::total 2133311360 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu 2133311360 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 2133311360 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bytesRead 213331136 # Total number of bytes read from memory
system.physmem.bytesWritten 0 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 213331136 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
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system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 217600 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 217600 # Track reads on a per bank basis
system.membus.throughput 2133311360 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 3333300 # Transaction distribution
system.membus.trans_dist::ReadResp 3333299 # Transaction distribution
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system.membus.data_through_bus 213331136 # Total data (bytes)
system.membus.reqLayer0.occupancy 6333270000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 6.3 # Layer utilization (%)
system.membus.respLayer0.occupancy 17184426300 # Layer occupancy (ticks)
system.membus.respLayer0.utilization 17.2 # Layer utilization (%)
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system.monitor.readBurstLengthHist::samples 3333300 # Histogram of burst lengths of transmitted packets
system.monitor.readBurstLengthHist::mean 64 # Histogram of burst lengths of transmitted packets
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system.monitor.writeTransHist::18 0 0.00% 100.00% # Histogram of read transactions per sample period
system.monitor.writeTransHist::19 0 0.00% 100.00% # Histogram of read transactions per sample period
system.monitor.writeTransHist::total 100 # Histogram of read transactions per sample period
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---------- End Simulation Statistics ----------
sim_ticks 100000000000 # Number of ticks simulated
final_tick 100000000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
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system.physmem.bytes_read::cpu 64 # Number of bytes read from this memory
system.physmem.bytes_read::total 64 # Number of bytes read from this memory
system.physmem.bytes_written::cpu 213329152 # Number of bytes written to this memory
system.membus.trans_dist::ReadResp 1 # Transaction distribution
system.membus.trans_dist::WriteReq 3333268 # Transaction distribution
system.membus.trans_dist::WriteResp 3333267 # Transaction distribution
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system.membus.data_through_bus 213329216 # Total data (bytes)
system.membus.reqLayer0.occupancy 16666342328 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 16.7 # Layer utilization (%)
system.membus.respLayer0.occupancy 3333272000 # Layer occupancy (ticks)
system.membus.respLayer0.utilization 3.3 # Layer utilization (%)
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system.monitor.readBurstLengthHist::samples 1 # Histogram of burst lengths of transmitted packets
system.monitor.readBurstLengthHist::mean 64 # Histogram of burst lengths of transmitted packets
system.monitor.readBurstLengthHist::gmean 64.000000 # Histogram of burst lengths of transmitted packets
system.monitor.writeTransHist::36864-38911 0 0.00% 100.00% # Histogram of read transactions per sample period
system.monitor.writeTransHist::38912-40959 0 0.00% 100.00% # Histogram of read transactions per sample period
system.monitor.writeTransHist::total 100 # Histogram of read transactions per sample period
+system.cpu.numPackets 3333269 # Number of packets generated
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---------- End Simulation Statistics ----------
projects / gem5.git / commitdiff